Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_1ch_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_1ch_Refdesign\project\fpga_project\src\a.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_1ch_Refdesign\project\fpga_project\src\fpga_project.sdc
GOWIN version	V1.9.7.02Beta
Part Number	GW1NR-LV9MG100PAC7/I6
Device	GW1NR-9C
Created Time	Tue Mar 09 17:10:52 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C
Hold Delay Model	Fast 1.26V 0C
Numbers of Paths Analyzed	4401
Numbers of Endpoints Analyzed	4471
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk_x2p	Base	7.143	139.997	0.000	3.571			u_psram_memory_interface_top/u_apsram_top/clk_x2p
clk_d	Base	28.571	35.001	0.000	14.286			clk_d
clk_x2	Base	7.143	139.997	0.000	3.571			u_psram_memory_interface_top/u_apsram_top/clk_x2
clk	Base	20.000	50.000	0.000	10.000			clk
clk_x1	Base	14.286	69.999	0.000	7.143			clk_x1
your_instance_name/rpll_inst/CLKOUT.default_gen_clk	Generated	6.250	160.000	0.000	3.125	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUT
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Generated	6.250	160.000	1.563	4.688	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTP
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Generated	18.750	53.333	0.000	9.375	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk_d	35.001(MHz)	152.169(MHz)	4	TOP
2	clk_x1	69.999(MHz)	98.668(MHz)	6	TOP

No timing paths to get frequency of clk_x2p!

No timing paths to get frequency of clk_x2!

No timing paths to get frequency of clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk_x2p	Setup	0.000	0
clk_x2p	Hold	0.000	0
clk_d	Setup	0.000	0
clk_d	Hold	0.000	0
clk_x2	Setup	0.000	0
clk_x2	Hold	0.000	0
clk	Setup	0.000	0
clk	Hold	0.000	0
clk_x1	Setup	0.000	0
clk_x1	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.799	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.236
2	4.032	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.003
3	4.151	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_124_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.839
4	4.154	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	2.881
5	4.155	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	2.881
6	4.155	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	2.881
7	4.168	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	2.868
8	4.168	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	2.868
9	4.237	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_119_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.752
10	4.237	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_120_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.752
11	4.237	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_121_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.752
12	4.241	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_116_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.749
13	4.241	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_122_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.749
14	4.241	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_123_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.749
15	4.241	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_126_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.749
16	4.264	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/c_state.IDLE_s0/Q	u_test/curr_state.CMD_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.725
17	4.277	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	2.758
18	4.277	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	2.758
19	4.290	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_113_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.700
20	4.290	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_115_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.700
21	4.293	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_125_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.697
22	4.296	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_127_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.693
23	4.304	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_110_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.685
24	4.354	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_104_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.636
25	4.354	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_105_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	9.636

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.412	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CE	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.423
2	0.422	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s2/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s5/CE	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.433
3	0.457	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s2/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s68/AD[0]	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.468
4	0.524	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_0_s3/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
5	0.524	u_test/wr_data_add_17_s1/Q	u_test/wr_data_add_17_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
6	0.524	u_test/wr_data_add_37_s1/Q	u_test/wr_data_add_37_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
7	0.524	u_test/wr_data_add_79_s1/Q	u_test/wr_data_add_79_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
8	0.524	u_test/wr_data_add_111_s1/Q	u_test/wr_data_add_111_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
9	0.524	u_test/wr_data_add_117_s1/Q	u_test/wr_data_add_117_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
10	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/D	clk_d:[R]	clk_d:[R]	0.000	0.000	0.524
11	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].times_reg_0_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].times_reg_0_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
12	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
13	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].check_cnt_2_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].check_cnt_2_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
14	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_5_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_5_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
15	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_8_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_8_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
16	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
17	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_9_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_9_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
18	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_10_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_10_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
19	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_1_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_1_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
20	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_2_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_2_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
21	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
22	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
23	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
24	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
25	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CLK_WAITE_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CLK_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_127_s0
2	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_111_s0
3	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_103_s0
4	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_99_s0
5	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_97_s0
6	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_96_s0
7	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_32_s0
8	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dq_14_s0
9	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/burst_cnt_9_s1
10	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_test/addr_1_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.799
Data Arrival Time	3.417
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.520	0.340	tC2Q	RF	12	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
3.417	2.896	tNET	FF	1	IOL2[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	73	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOL2[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4
7.216	0.000	tSu		1	IOL2[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.896, 89.504%; tC2Q: 0.340, 10.496%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path2

Path Summary:

Slack	4.032
Data Arrival Time	3.184
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.520	0.340	tC2Q	RF	12	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
3.184	2.663	tNET	FF	1	IOL3[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	73	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOL3[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4
7.216	0.000	tSu		1	IOL3[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.663, 88.690%; tC2Q: 0.340, 11.310%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path3

Path Summary:

Slack	4.151
Data Arrival Time	10.019
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_124_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.410	2.311	tNET	FF	1	R12C13[0][B]	u_test/n910_s1/I0
10.019	0.609	tINS	FF	1	R12C13[0][B]	u_test/n910_s1/F
10.019	0.000	tNET	FF	1	R12C13[0][B]	u_test/wr_data_add_124_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R12C13[0][B]	u_test/wr_data_add_124_s1/CLK
14.170	-0.296	tSu		1	R12C13[0][B]	u_test/wr_data_add_124_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.261, 33.146%; route: 6.238, 63.402%; tC2Q: 0.340, 3.452%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path4

Path Summary:

Slack	4.154
Data Arrival Time	3.062
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.520	0.340	tC2Q	RF	12	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
3.062	2.542	tNET	FF	1	IOL6[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	73	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOL6[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4
7.216	0.000	tSu		1	IOL6[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.542, 88.213%; tC2Q: 0.340, 11.787%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path5

Path Summary:

Slack	4.155
Data Arrival Time	3.061
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.520	0.340	tC2Q	RF	12	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
3.061	2.541	tNET	FF	1	IOL8[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	73	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOL8[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4
7.216	0.000	tSu		1	IOL8[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.541, 88.210%; tC2Q: 0.340, 11.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path6

Path Summary:

Slack	4.155
Data Arrival Time	3.061
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.520	0.340	tC2Q	RF	12	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
3.061	2.541	tNET	FF	1	IOL4[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	73	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOL4[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4
7.216	0.000	tSu		1	IOL4[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.541, 88.210%; tC2Q: 0.340, 11.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path7

Path Summary:

Slack	4.168
Data Arrival Time	3.048
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R17C24[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0/CLK
0.520	0.340	tC2Q	RF	12	R17C24[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0/Q
3.048	2.528	tNET	FF	1	IOL27[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	73	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOL27[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4
7.216	0.000	tSu		1	IOL27[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.528, 88.157%; tC2Q: 0.340, 11.843%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path8

Path Summary:

Slack	4.168
Data Arrival Time	3.048
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R14C27[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/CLK
0.520	0.340	tC2Q	RF	12	R14C27[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q
3.048	2.528	tNET	FF	1	IOR3[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	73	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR3[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4
7.216	0.000	tSu		1	IOR3[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.528, 88.157%; tC2Q: 0.340, 11.843%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path9

Path Summary:

Slack	4.237
Data Arrival Time	9.933
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_119_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.169	2.069	tNET	FF	1	R13C12[1][A]	u_test/n915_s1/I0
9.933	0.765	tINS	FF	1	R13C12[1][A]	u_test/n915_s1/F
9.933	0.000	tNET	FF	1	R13C12[1][A]	u_test/wr_data_add_119_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C12[1][A]	u_test/wr_data_add_119_s1/CLK
14.170	-0.296	tSu		1	R13C12[1][A]	u_test/wr_data_add_119_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.417, 35.035%; route: 5.996, 61.483%; tC2Q: 0.340, 3.482%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path10

Path Summary:

Slack	4.237
Data Arrival Time	9.933
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_120_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.169	2.069	tNET	FF	1	R13C12[1][B]	u_test/n914_s1/I0
9.933	0.765	tINS	FF	1	R13C12[1][B]	u_test/n914_s1/F
9.933	0.000	tNET	FF	1	R13C12[1][B]	u_test/wr_data_add_120_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C12[1][B]	u_test/wr_data_add_120_s1/CLK
14.170	-0.296	tSu		1	R13C12[1][B]	u_test/wr_data_add_120_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.417, 35.035%; route: 5.996, 61.483%; tC2Q: 0.340, 3.482%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path11

Path Summary:

Slack	4.237
Data Arrival Time	9.933
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_121_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.169	2.069	tNET	FF	1	R13C12[2][A]	u_test/n913_s1/I0
9.933	0.765	tINS	FF	1	R13C12[2][A]	u_test/n913_s1/F
9.933	0.000	tNET	FF	1	R13C12[2][A]	u_test/wr_data_add_121_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C12[2][A]	u_test/wr_data_add_121_s1/CLK
14.170	-0.296	tSu		1	R13C12[2][A]	u_test/wr_data_add_121_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.417, 35.035%; route: 5.996, 61.483%; tC2Q: 0.340, 3.482%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path12

Path Summary:

Slack	4.241
Data Arrival Time	9.930
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_116_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.165	2.066	tNET	FF	1	R12C13[0][A]	u_test/n918_s1/I0
9.930	0.765	tINS	FF	1	R12C13[0][A]	u_test/n918_s1/F
9.930	0.000	tNET	FF	1	R12C13[0][A]	u_test/wr_data_add_116_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R12C13[0][A]	u_test/wr_data_add_116_s1/CLK
14.170	-0.296	tSu		1	R12C13[0][A]	u_test/wr_data_add_116_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.417, 35.047%; route: 5.993, 61.469%; tC2Q: 0.340, 3.484%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path13

Path Summary:

Slack	4.241
Data Arrival Time	9.930
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_122_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.165	2.066	tNET	FF	1	R12C13[2][A]	u_test/n912_s1/I0
9.930	0.765	tINS	FF	1	R12C13[2][A]	u_test/n912_s1/F
9.930	0.000	tNET	FF	1	R12C13[2][A]	u_test/wr_data_add_122_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R12C13[2][A]	u_test/wr_data_add_122_s1/CLK
14.170	-0.296	tSu		1	R12C13[2][A]	u_test/wr_data_add_122_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.417, 35.047%; route: 5.993, 61.469%; tC2Q: 0.340, 3.484%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path14

Path Summary:

Slack	4.241
Data Arrival Time	9.930
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_123_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.165	2.066	tNET	FF	1	R12C12[0][B]	u_test/n911_s1/I0
9.930	0.765	tINS	FF	1	R12C12[0][B]	u_test/n911_s1/F
9.930	0.000	tNET	FF	1	R12C12[0][B]	u_test/wr_data_add_123_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R12C12[0][B]	u_test/wr_data_add_123_s1/CLK
14.170	-0.296	tSu		1	R12C12[0][B]	u_test/wr_data_add_123_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.417, 35.047%; route: 5.993, 61.469%; tC2Q: 0.340, 3.484%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path15

Path Summary:

Slack	4.241
Data Arrival Time	9.930
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_126_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.165	2.066	tNET	FF	1	R12C12[2][A]	u_test/n908_s1/I0
9.930	0.765	tINS	FF	1	R12C12[2][A]	u_test/n908_s1/F
9.930	0.000	tNET	FF	1	R12C12[2][A]	u_test/wr_data_add_126_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R12C12[2][A]	u_test/wr_data_add_126_s1/CLK
14.170	-0.296	tSu		1	R12C12[2][A]	u_test/wr_data_add_126_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.417, 35.047%; route: 5.993, 61.469%; tC2Q: 0.340, 3.484%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path16

Path Summary:

Slack	4.264
Data Arrival Time	9.906
Data Required Time	14.170
From	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/c_state.IDLE_s0
To	u_test/curr_state.CMD_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R22C38[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/c_state.IDLE_s0/CLK
0.520	0.340	tC2Q	RF	23	R22C38[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/c_state.IDLE_s0/Q
2.099	1.578	tNET	FF	1	R17C32[0][A]	u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s0/I3
2.708	0.609	tINS	FF	1	R17C32[0][A]	u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s0/F
3.907	1.199	tNET	FF	1	R17C16[0][A]	u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/I1
4.516	0.609	tINS	FF	9	R17C16[0][A]	u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/F
5.488	0.972	tNET	FF	1	R18C9[3][A]	u_test/next_state.IDLE_s16/I0
6.274	0.786	tINS	FR	2	R18C9[3][A]	u_test/next_state.IDLE_s16/F
6.586	0.312	tNET	RR	1	R18C8[3][A]	u_test/next_state.CYC_DONE_s14/I2
7.400	0.814	tINS	RF	3	R18C8[3][A]	u_test/next_state.CYC_DONE_s14/F
8.020	0.620	tNET	FF	1	R20C8[2][B]	u_test/next_state.CMD_WAITE_s12/I3
8.780	0.760	tINS	FR	2	R20C8[2][B]	u_test/next_state.CMD_WAITE_s12/F
9.092	0.312	tNET	RR	1	R21C8[2][A]	u_test/next_state.CMD_WAITE_s11/I0
9.906	0.814	tINS	RF	1	R21C8[2][A]	u_test/next_state.CMD_WAITE_s11/F
9.906	0.000	tNET	FF	1	R21C8[2][A]	u_test/curr_state.CMD_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R21C8[2][A]	u_test/curr_state.CMD_WAITE_s0/CLK
14.170	-0.296	tSu		1	R21C8[2][A]	u_test/curr_state.CMD_WAITE_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 4.393, 45.175%; route: 4.992, 51.333%; tC2Q: 0.340, 3.492%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path17

Path Summary:

Slack	4.277
Data Arrival Time	2.939
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R17C24[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0/CLK
0.520	0.340	tC2Q	RF	12	R17C24[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0/Q
2.939	2.419	tNET	FF	1	IOL26[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	73	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOL26[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4
7.216	0.000	tSu		1	IOL26[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.419, 87.687%; tC2Q: 0.340, 12.313%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path18

Path Summary:

Slack	4.277
Data Arrival Time	2.939
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R17C24[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0/CLK
0.520	0.340	tC2Q	RF	12	R17C24[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_1_s0/Q
2.939	2.419	tNET	FF	1	IOL26[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	73	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOL26[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4
7.216	0.000	tSu		1	IOL26[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.419, 87.687%; tC2Q: 0.340, 12.313%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path19

Path Summary:

Slack	4.290
Data Arrival Time	9.881
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_113_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.066	1.967	tNET	FF	1	R12C14[1][A]	u_test/n921_s1/I0
9.881	0.814	tINS	FF	1	R12C14[1][A]	u_test/n921_s1/F
9.881	0.000	tNET	FF	1	R12C14[1][A]	u_test/wr_data_add_113_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R12C14[1][A]	u_test/wr_data_add_113_s1/CLK
14.170	-0.296	tSu		1	R12C14[1][A]	u_test/wr_data_add_113_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.466, 35.737%; route: 5.894, 60.762%; tC2Q: 0.340, 3.501%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path20

Path Summary:

Slack	4.290
Data Arrival Time	9.881
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_115_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.066	1.967	tNET	FF	1	R12C14[2][A]	u_test/n919_s1/I0
9.881	0.814	tINS	FF	1	R12C14[2][A]	u_test/n919_s1/F
9.881	0.000	tNET	FF	1	R12C14[2][A]	u_test/wr_data_add_115_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R12C14[2][A]	u_test/wr_data_add_115_s1/CLK
14.170	-0.296	tSu		1	R12C14[2][A]	u_test/wr_data_add_115_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.466, 35.737%; route: 5.894, 60.762%; tC2Q: 0.340, 3.501%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path21

Path Summary:

Slack	4.293
Data Arrival Time	9.878
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_125_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.414	2.315	tNET	FF	1	R13C12[2][B]	u_test/n909_s1/I0
9.878	0.464	tINS	FF	1	R13C12[2][B]	u_test/n909_s1/F
9.878	0.000	tNET	FF	1	R13C12[2][B]	u_test/wr_data_add_125_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C12[2][B]	u_test/wr_data_add_125_s1/CLK
14.170	-0.296	tSu		1	R13C12[2][B]	u_test/wr_data_add_125_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.116, 32.133%; route: 6.241, 64.364%; tC2Q: 0.340, 3.502%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path22

Path Summary:

Slack	4.296
Data Arrival Time	9.874
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_127_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.410	2.311	tNET	FF	1	R12C12[2][B]	u_test/n907_s1/I0
9.874	0.464	tINS	FF	1	R12C12[2][B]	u_test/n907_s1/F
9.874	0.000	tNET	FF	1	R12C12[2][B]	u_test/wr_data_add_127_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R12C12[2][B]	u_test/wr_data_add_127_s1/CLK
14.170	-0.296	tSu		1	R12C12[2][B]	u_test/wr_data_add_127_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.116, 32.145%; route: 6.238, 64.352%; tC2Q: 0.340, 3.504%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path23

Path Summary:

Slack	4.304
Data Arrival Time	9.866
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_110_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.052	1.953	tNET	FF	1	R13C14[2][B]	u_test/n924_s1/I0
9.866	0.814	tINS	FF	1	R13C14[2][B]	u_test/n924_s1/F
9.866	0.000	tNET	FF	1	R13C14[2][B]	u_test/wr_data_add_110_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C14[2][B]	u_test/wr_data_add_110_s1/CLK
14.170	-0.296	tSu		1	R13C14[2][B]	u_test/wr_data_add_110_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.466, 35.790%; route: 5.879, 60.703%; tC2Q: 0.340, 3.507%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path24

Path Summary:

Slack	4.354
Data Arrival Time	9.816
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_104_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.052	1.953	tNET	FF	1	R12C15[0][B]	u_test/n930_s1/I1
9.816	0.765	tINS	FF	1	R12C15[0][B]	u_test/n930_s1/F
9.816	0.000	tNET	FF	1	R12C15[0][B]	u_test/wr_data_add_104_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R12C15[0][B]	u_test/wr_data_add_104_s1/CLK
14.170	-0.296	tSu		1	R12C15[0][B]	u_test/wr_data_add_104_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.417, 35.459%; route: 5.879, 61.016%; tC2Q: 0.340, 3.525%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path25

Path Summary:

Slack	4.354
Data Arrival Time	9.816
Data Required Time	14.170
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_105_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.520	0.340	tC2Q	RF	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
1.730	1.210	tNET	FF	1	R14C8[3][A]	u_test/n1030_s2/I1
2.544	0.814	tINS	FF	7	R14C8[3][A]	u_test/n1030_s2/F
3.410	0.865	tNET	FF	1	R13C7[3][B]	u_test/n1021_s2/I1
4.174	0.765	tINS	FF	13	R13C7[3][B]	u_test/n1021_s2/F
5.284	1.109	tNET	FF	1	R8C9[2][A]	u_test/n976_s2/I0
5.747	0.464	tINS	FF	21	R8C9[2][A]	u_test/n976_s2/F
6.490	0.742	tNET	FF	1	R12C9[1][A]	u_test/n931_s2/I0
7.099	0.609	tINS	FF	25	R12C9[1][A]	u_test/n931_s2/F
9.052	1.953	tNET	FF	1	R13C15[1][A]	u_test/n929_s1/I0
9.816	0.765	tINS	FF	1	R13C15[1][A]	u_test/n929_s1/F
9.816	0.000	tNET	FF	1	R13C15[1][A]	u_test/wr_data_add_105_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C15[1][A]	u_test/wr_data_add_105_s1/CLK
14.170	-0.296	tSu		1	R13C15[1][A]	u_test/wr_data_add_105_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.417, 35.459%; route: 5.879, 61.016%; tC2Q: 0.340, 3.525%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.412
Data Arrival Time	0.560
Data Required Time	0.148
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C26[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.384	0.247	tC2Q	RR	2	R14C26[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q
0.560	0.176	tNET	RR	1	R14C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.148	0.011	tHld		1	R14C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path2

Path Summary:

Slack	0.422
Data Arrival Time	0.569
Data Required Time	0.148
From	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s2
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s5
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s2/CLK
0.384	0.247	tC2Q	RR	74	R13C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s2/Q
0.569	0.186	tNET	RR	1	R13C35[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s5/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C35[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s5/CLK
0.148	0.011	tHld		1	R13C35[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.186, 42.912%; tC2Q: 0.247, 57.088%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path3

Path Summary:

Slack	0.457
Data Arrival Time	0.605
Data Required Time	0.148
From	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s2
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s68
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s2/CLK
0.384	0.247	tC2Q	RF	74	R13C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s2/Q
0.605	0.221	tNET	FF	1	R14C35	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s68/AD[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C35	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s68/CLK
0.148	0.011	tHld		1	R14C35	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_s68

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.221, 47.210%; tC2Q: 0.247, 52.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path4

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.384	0.247	tC2Q	RR	6	R20C6[0][A]	u_test/wr_data_add_0_s3/Q
0.386	0.002	tNET	RR	1	R20C6[0][A]	u_test/n1034_s3/I1
0.661	0.276	tINS	RF	1	R20C6[0][A]	u_test/n1034_s3/F
0.661	0.000	tNET	FF	1	R20C6[0][A]	u_test/wr_data_add_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R20C6[0][A]	u_test/wr_data_add_0_s3/CLK
0.137	0.000	tHld		1	R20C6[0][A]	u_test/wr_data_add_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path5

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_17_s1
To	u_test/wr_data_add_17_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C8[0][A]	u_test/wr_data_add_17_s1/CLK
0.384	0.247	tC2Q	RR	3	R13C8[0][A]	u_test/wr_data_add_17_s1/Q
0.386	0.002	tNET	RR	1	R13C8[0][A]	u_test/n1017_s1/I2
0.661	0.276	tINS	RF	1	R13C8[0][A]	u_test/n1017_s1/F
0.661	0.000	tNET	FF	1	R13C8[0][A]	u_test/wr_data_add_17_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C8[0][A]	u_test/wr_data_add_17_s1/CLK
0.137	0.000	tHld		1	R13C8[0][A]	u_test/wr_data_add_17_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path6

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_37_s1
To	u_test/wr_data_add_37_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R7C10[0][A]	u_test/wr_data_add_37_s1/CLK
0.384	0.247	tC2Q	RR	4	R7C10[0][A]	u_test/wr_data_add_37_s1/Q
0.386	0.002	tNET	RR	1	R7C10[0][A]	u_test/n997_s1/I2
0.661	0.276	tINS	RF	1	R7C10[0][A]	u_test/n997_s1/F
0.661	0.000	tNET	FF	1	R7C10[0][A]	u_test/wr_data_add_37_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R7C10[0][A]	u_test/wr_data_add_37_s1/CLK
0.137	0.000	tHld		1	R7C10[0][A]	u_test/wr_data_add_37_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path7

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_79_s1
To	u_test/wr_data_add_79_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C13[0][A]	u_test/wr_data_add_79_s1/CLK
0.384	0.247	tC2Q	RR	4	R9C13[0][A]	u_test/wr_data_add_79_s1/Q
0.386	0.002	tNET	RR	1	R9C13[0][A]	u_test/n955_s1/I2
0.661	0.276	tINS	RF	1	R9C13[0][A]	u_test/n955_s1/F
0.661	0.000	tNET	FF	1	R9C13[0][A]	u_test/wr_data_add_79_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C13[0][A]	u_test/wr_data_add_79_s1/CLK
0.137	0.000	tHld		1	R9C13[0][A]	u_test/wr_data_add_79_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path8

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_111_s1
To	u_test/wr_data_add_111_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C15[0][A]	u_test/wr_data_add_111_s1/CLK
0.384	0.247	tC2Q	RR	4	R12C15[0][A]	u_test/wr_data_add_111_s1/Q
0.386	0.002	tNET	RR	1	R12C15[0][A]	u_test/n923_s1/I2
0.661	0.276	tINS	RF	1	R12C15[0][A]	u_test/n923_s1/F
0.661	0.000	tNET	FF	1	R12C15[0][A]	u_test/wr_data_add_111_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C15[0][A]	u_test/wr_data_add_111_s1/CLK
0.137	0.000	tHld		1	R12C15[0][A]	u_test/wr_data_add_111_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path9

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_117_s1
To	u_test/wr_data_add_117_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C9[1][A]	u_test/wr_data_add_117_s1/CLK
0.384	0.247	tC2Q	RR	3	R13C9[1][A]	u_test/wr_data_add_117_s1/Q
0.386	0.002	tNET	RR	1	R13C9[1][A]	u_test/n917_s1/I2
0.661	0.276	tINS	RF	1	R13C9[1][A]	u_test/n917_s1/F
0.661	0.000	tNET	FF	1	R13C9[1][A]	u_test/wr_data_add_117_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C9[1][A]	u_test/wr_data_add_117_s1/CLK
0.137	0.000	tHld		1	R13C9[1][A]	u_test/wr_data_add_117_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path10

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3
To	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3
Launch Clk	clk_d:[R]
Latch Clk	clk_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R7C37[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK
0.384	0.247	tC2Q	RR	5	R7C37[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q
0.386	0.002	tNET	RR	1	R7C37[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/n50_s4/I2
0.661	0.276	tINS	RF	1	R7C37[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/n50_s4/F
0.661	0.000	tNET	FF	1	R7C37[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R7C37[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK
0.137	0.000	tHld		1	R7C37[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path11

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].times_reg_0_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].times_reg_0_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].times_reg_0_s1/CLK
0.384	0.247	tC2Q	RR	3	R12C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].times_reg_0_s1/Q
0.386	0.002	tNET	RR	1	R12C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3991_s3/I1
0.661	0.276	tINS	RF	1	R12C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3991_s3/F
0.661	0.000	tNET	FF	1	R12C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].times_reg_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].times_reg_0_s1/CLK
0.137	0.000	tHld		1	R12C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].times_reg_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path12

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/CLK
0.384	0.247	tC2Q	RR	2	R18C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/Q
0.386	0.002	tNET	RR	1	R18C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3883_s1/I3
0.661	0.276	tINS	RF	1	R18C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3883_s1/F
0.661	0.000	tNET	FF	1	R18C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/CLK
0.137	0.000	tHld		1	R18C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path13

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].check_cnt_2_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].check_cnt_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R20C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].check_cnt_2_s1/CLK
0.384	0.247	tC2Q	RR	4	R20C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].check_cnt_2_s1/Q
0.386	0.002	tNET	RR	1	R20C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3422_s3/I1
0.661	0.276	tINS	RF	1	R20C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3422_s3/F
0.661	0.000	tNET	FF	1	R20C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].check_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R20C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].check_cnt_2_s1/CLK
0.137	0.000	tHld		1	R20C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].check_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path14

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_5_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R21C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_5_s1/CLK
0.384	0.247	tC2Q	RR	2	R21C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_5_s1/Q
0.386	0.002	tNET	RR	1	R21C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2955_s1/I3
0.661	0.276	tINS	RF	1	R21C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2955_s1/F
0.661	0.000	tNET	FF	1	R21C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R21C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_5_s1/CLK
0.137	0.000	tHld		1	R21C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path15

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_8_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_8_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_8_s1/CLK
0.384	0.247	tC2Q	RR	2	R17C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_8_s1/Q
0.386	0.002	tNET	RR	1	R17C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2191_s1/I3
0.661	0.276	tINS	RF	1	R17C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2191_s1/F
0.661	0.000	tNET	FF	1	R17C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_8_s1/CLK
0.137	0.000	tHld		1	R17C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path16

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/CLK
0.384	0.247	tC2Q	RR	3	R14C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/Q
0.386	0.002	tNET	RR	1	R14C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n576_s1/I1
0.661	0.276	tINS	RF	1	R14C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n576_s1/F
0.661	0.000	tNET	FF	1	R14C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/CLK
0.137	0.000	tHld		1	R14C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path17

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_9_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_9_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_9_s1/CLK
0.384	0.247	tC2Q	RR	4	R11C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_9_s1/Q
0.386	0.002	tNET	RR	1	R11C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n444_s3/I3
0.661	0.276	tINS	RF	1	R11C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n444_s3/F
0.661	0.000	tNET	FF	1	R11C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_9_s1/CLK
0.137	0.000	tHld		1	R11C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path18

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_10_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_10_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_10_s1/CLK
0.384	0.247	tC2Q	RR	3	R11C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_10_s1/Q
0.386	0.002	tNET	RR	1	R11C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n443_s1/I3
0.661	0.276	tINS	RF	1	R11C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n443_s1/F
0.661	0.000	tNET	FF	1	R11C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_10_s1/CLK
0.137	0.000	tHld		1	R11C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path19

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_1_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_1_s0/CLK
0.384	0.247	tC2Q	RR	3	R9C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_1_s0/Q
0.386	0.002	tNET	RR	1	R9C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3751_s1/I1
0.661	0.276	tINS	RF	1	R9C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3751_s1/F
0.661	0.000	tNET	FF	1	R9C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_1_s0/CLK
0.137	0.000	tHld		1	R9C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path20

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_2_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_2_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_2_s0/CLK
0.384	0.247	tC2Q	RR	2	R9C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_2_s0/Q
0.386	0.002	tNET	RR	1	R9C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3750_s1/I2
0.661	0.276	tINS	RF	1	R9C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3750_s1/F
0.661	0.000	tNET	FF	1	R9C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_2_s0/CLK
0.137	0.000	tHld		1	R9C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].add_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path21

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R8C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/CLK
0.384	0.247	tC2Q	RR	3	R8C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/Q
0.386	0.002	tNET	RR	1	R8C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2823_s1/I1
0.661	0.276	tINS	RF	1	R8C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2823_s1/F
0.661	0.000	tNET	FF	1	R8C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R8C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/CLK
0.137	0.000	tHld		1	R8C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path22

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/CLK
0.384	0.247	tC2Q	RR	2	R13C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/Q
0.386	0.002	tNET	RR	1	R13C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2358_s1/I2
0.661	0.276	tINS	RF	1	R13C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2358_s1/F
0.661	0.000	tNET	FF	1	R13C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/CLK
0.137	0.000	tHld		1	R13C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path23

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C26[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.384	0.247	tC2Q	RR	2	R14C26[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q
0.386	0.002	tNET	RR	1	R14C26[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_DONE_s27/I1
0.661	0.276	tINS	RF	1	R14C26[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_DONE_s27/F
0.661	0.000	tNET	FF	1	R14C26[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C26[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.137	0.000	tHld		1	R14C26[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path24

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C24[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/CLK
0.384	0.247	tC2Q	RR	2	R15C24[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/Q
0.386	0.002	tNET	RR	1	R15C24[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_WAITE_s27/I3
0.661	0.276	tINS	RF	1	R15C24[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_WAITE_s27/F
0.661	0.000	tNET	FF	1	R15C24[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C24[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/CLK
0.137	0.000	tHld		1	R15C24[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path25

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CLK_WAITE_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CLK_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CLK_WAITE_s0/CLK
0.384	0.247	tC2Q	RR	3	R15C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CLK_WAITE_s0/Q
0.386	0.002	tNET	RR	1	R15C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.CLK_WAITE_s26/I3
0.661	0.276	tINS	RF	1	R15C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.CLK_WAITE_s26/F
0.661	0.000	tNET	FF	1	R15C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CLK_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1556	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CLK_WAITE_s0/CLK
0.137	0.000	tHld		1	R15C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CLK_WAITE_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_127_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_127_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_127_s0/CLK

MPW2

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_111_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_111_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_111_s0/CLK

MPW3

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_103_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_103_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_103_s0/CLK

MPW4

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_99_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_99_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_99_s0/CLK

MPW5

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_97_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_97_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_97_s0/CLK

MPW6

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_96_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_96_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_96_s0/CLK

MPW7

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_32_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_32_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_32_s0/CLK

MPW8

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dq_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dq_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dq_14_s0/CLK

MPW9

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/burst_cnt_9_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/burst_cnt_9_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/burst_cnt_9_s1/CLK

MPW10

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_test/addr_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_test/addr_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_test/addr_1_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
1556	clk_x1	3.799	0.195
282	curr_state.WRITE_BURST	7.536	2.324
225	init_calib_d	4.814	3.170
152	config_done_Z	7.153	3.496
150	wr_data_127_11	6.590	3.163
129	rd_data_valid_d0	6.889	2.660
127	wr_data_add_127_10	6.342	3.146
74	wr_data_d0_0_5	11.791	1.655
66	n2516_3	5.562	2.401
66	n3908_3	6.160	2.660

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R15C24	63.89%
R13C30	62.50%
R15C20	55.56%
R11C16	54.17%
R14C24	54.17%
R13C39	54.17%
R20C8	54.17%
R20C31	54.17%
R13C35	52.78%
R20C9	50.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk_x2p -period 7.143 -waveform {0 3.571} [get_nets {u_psram_memory_interface_top/u_apsram_top/clk_x2p}]
TC_CLOCK	Actived	create_clock -name clk_d -period 28.571 -waveform {0 14.286} [get_nets {clk_d}]
TC_CLOCK	Actived	create_clock -name clk_x2 -period 7.143 -waveform {0 3.571} [get_nets {u_psram_memory_interface_top/u_apsram_top/clk_x2}]
TC_CLOCK	Actived	create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name clk_x1 -period 14.286 -waveform {0 7.143} [get_nets {clk_x1}]