| Report Title |
Gowin Power Analysis Report |
| Design File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_1ch_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_1ch_Refdesign\project\fpga_project\src\a.cst |
| Timing Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_1ch_Refdesign\project\fpga_project\src\fpga_project.sdc |
| GOWIN Version |
V1.9.7.02Beta |
| Part Number |
GW1NR-LV9MG100PAC7/I6 |
| Device |
GW1NR-9C |
| Created Time |
Tue Mar 09 17:10:52 2021
|
| Legal Announcement |
Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
58.507 |
| Quiescent Power (mW) |
4.905 |
| Dynamic Power (mW) |
53.602 |
| Psram Power (mW) |
172.000 |
| Junction Temperature |
25.609 |
| Theta JA |
10.500 |
| Max Allowed Ambient Temperature |
84.391 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.200 |
41.522 |
2.605 |
52.952 |
| VCCX |
2.500 |
0.880 |
0.415 |
3.238 |
| VCCO18 |
1.800 |
0.876 |
0.411 |
2.317 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
7.566 |
NA |
8.640 |
| IO |
7.251
| 2.278
| 17.571
|
| PLL |
3.720
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
Routing Dynamic Power(mW) |
| syn_top |
48.645 |
11.286(11.286) |
37.358(37.328) |
| syn_top/u_psram_memory_interface_top/ |
32.430 |
4.972(4.972) |
27.458(27.458) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/ |
32.430 |
4.972(4.215) |
27.458(23.818) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_init/ |
11.919 |
2.242(0.000) |
9.677(0.000) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_sync/ |
0.498 |
0.081(0.000) |
0.417(0.000) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_wd/ |
15.616 |
1.893(1.884) |
13.723(13.609) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
6.648 |
0.711(0.000) |
5.937(0.000) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/ |
3.186 |
0.390(0.000) |
2.796(0.000) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/ |
2.867 |
0.392(0.000) |
2.475(0.000) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/ |
2.791 |
0.390(0.000) |
2.401(0.000) |
| syn_top/u_test/ |
12.250 |
2.594(0.000) |
9.657(0.000) |
| syn_top/your_instance_name/ |
3.934 |
3.720(0.000) |
0.213(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| clk_x1 |
69.999 |
44.158 |
| clk_d |
35.001 |
0.528 |
| NO CLOCK DOMAIN |
0.000 |
0.000 |
| clk |
50.000 |
3.751 |
| your_instance_name/rpll_inst/CLKOUT.default_gen_clk |
160.000 |
0.096 |
| your_instance_name/rpll_inst/CLKOUTP.default_gen_clk |
160.000 |
0.096 |