Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_1ch_Refdesign\project\fpga_project\src\apsram_syn_top.v
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_1ch_Refdesign\project\fpga_project\src\apsram_test.v
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_1ch_Refdesign\project\fpga_project\src\gowin_rpll\gowin_rpll.v
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_1ch_Refdesign\project\fpga_project\src\uhs_psram_memory_interface_v2\uhs_psram_memory_interface_v2.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW1NR-LV9MG100PAC7/I6
Device GW1NR-9C
Created Time Tue Mar 09 17:10:45 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module syn_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.679s, Peak memory usage = 250.398MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 250.398MB
    Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 250.398MB
    Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.108s, Peak memory usage = 250.398MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 250.398MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 250.398MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 250.398MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 250.398MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 250.398MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.125s, Peak memory usage = 250.398MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 250.398MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 250.398MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.206s, Peak memory usage = 250.398MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 250.398MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 250.398MB

Resource

Resource Usage Summary

I/O Port 4
Emedded Port 52
I/O Buf 52
    IBUF 2
    OBUF 6
    TBUF 4
    IOBUF 36
    ELVDS_OBUF 4
Register 1471
    DFF 1
    DFFP 9
    DFFPE 12
    DFFC 709
    DFFCE 740
LUT 2330
    LUT2 716
    LUT3 626
    LUT4 988
ALU 139
    ALU 139
SSRAM 36
    RAM16S4 36
INV 28
    INV 28
IOLOGIC 112
    IDES4 32
    OSER4 48
    IODELAY 32
CLOCK 4
    CLKDIV 1
    DHCEN 2
    rPLL 1

Resource Utilization Summary

Logic 2713(2358 LUTs, 139 ALUs, 36 SSRAMs) / 8640 31%
Register 1471 / 6900 21%
  --Register as Latch 0 / 6900 0%
  --Register as FF 1471 / 6900 21%
BSRAM 0 / 26 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
your_instance_name/rpll_inst/CLKOUT.default_gen_clk Generated 6.250 160.0 0.000 3.125 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUT
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk Generated 6.250 160.0 1.563 4.688 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTP
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk Generated 25.000 40.0 0.000 12.500 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk Generated 18.750 53.3 0.000 9.375 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD3
u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk Generated 12.500 80.0 0.000 6.250 your_instance_name/rpll_inst/CLKOUT your_instance_name/rpll_inst/CLKOUT.default_gen_clk u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk 40.0(MHz) 176.3(MHz) 5 TOP
2 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk 80.0(MHz) 135.9(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.342
Data Arrival Time 2.224
Data Required Time 4.565
From u_psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0
To u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2
Launch Clk your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F]
Latch Clk your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk
1.259 1.259 tCL RR 31 your_instance_name/rpll_inst/CLKOUTD
1.528 0.269 tNET RR 1 u_psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/CLK
1.868 0.340 tC2Q RF 8 u_psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/Q
2.224 0.356 tNET FF 1 u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
3.125 0.000 your_instance_name/rpll_inst/CLKOUT.default_gen_clk
4.427 1.302 tCL FF 1 your_instance_name/rpll_inst/CLKOUT
4.783 0.356 tNET FF 3 u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN
4.753 -0.030 tUnc u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2
4.565 -0.188 tSu 1 u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2
Path Statistics:
Clock Skew: 0.130
Setup Relationship: 3.125
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.356, 100.000%

Path 2

Path Summary:
Slack 3.876
Data Arrival Time 2.224
Data Required Time 6.100
From u_psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0
To u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2p
Launch Clk your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F]
Latch Clk your_instance_name/rpll_inst/CLKOUTP.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk
1.259 1.259 tCL RR 31 your_instance_name/rpll_inst/CLKOUTD
1.528 0.269 tNET RR 1 u_psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/CLK
1.868 0.340 tC2Q RF 8 u_psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/Q
2.224 0.356 tNET FF 1 u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
4.688 0.000 your_instance_name/rpll_inst/CLKOUTP.default_gen_clk
5.962 1.275 tCL FF 1 your_instance_name/rpll_inst/CLKOUTP
6.318 0.356 tNET FF 3 u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2p/CLKIN
6.288 -0.030 tUnc u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2p
6.100 -0.188 tSu 1 u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2p
Path Statistics:
Clock Skew: 0.102
Setup Relationship: 4.688
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.356, 100.000%

Path 3

Path Summary:
Slack 5.143
Data Arrival Time 7.599
Data Required Time 12.742
From u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.IDLE_s0
To u_test/curr_state.CYC_DONE_WAITE_s0
Launch Clk u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk
0.269 0.269 tCL RR 1556 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.538 0.269 tNET RR 1 u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.IDLE_s0/CLK
0.878 0.340 tC2Q RF 24 u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.IDLE_s0/Q
1.234 0.356 tNET FF 1 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s0/I1
2.048 0.814 tINS FF 1 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s0/F
2.404 0.356 tNET FF 1 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/I1
3.218 0.814 tINS FF 9 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/F
3.574 0.356 tNET FF 1 u_test/next_state.IDLE_s16/I0
4.338 0.765 tINS FF 2 u_test/next_state.IDLE_s16/F
4.694 0.356 tNET FF 1 u_test/next_state.CYC_DONE_s14/I2
5.303 0.609 tINS FF 3 u_test/next_state.CYC_DONE_s14/F
5.659 0.356 tNET FF 1 u_test/next_state.CMD_WAITE_s12/I3
6.123 0.464 tINS FF 2 u_test/next_state.CMD_WAITE_s12/F
6.478 0.356 tNET FF 1 u_test/next_state.CYC_DONE_WAITE_s12/I0
7.243 0.765 tINS FF 1 u_test/next_state.CYC_DONE_WAITE_s12/F
7.599 0.356 tNET FF 1 u_test/curr_state.CYC_DONE_WAITE_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
12.500 0.000 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk
12.769 0.269 tCL RR 1556 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
13.038 0.269 tNET RR 1 u_test/curr_state.CYC_DONE_WAITE_s0/CLK
12.742 -0.296 tSu 1 u_test/curr_state.CYC_DONE_WAITE_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 12.500
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 4.231, 59.927%; route: 2.490, 35.263%; tC2Q: 0.340, 4.810%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%

Path 4

Path Summary:
Slack 5.143
Data Arrival Time 7.599
Data Required Time 12.742
From u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.IDLE_s0
To u_test/curr_state.CMD_WAITE_s0
Launch Clk u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk
0.269 0.269 tCL RR 1556 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.538 0.269 tNET RR 1 u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.IDLE_s0/CLK
0.878 0.340 tC2Q RF 24 u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.IDLE_s0/Q
1.234 0.356 tNET FF 1 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s0/I1
2.048 0.814 tINS FF 1 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s0/F
2.404 0.356 tNET FF 1 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/I1
3.218 0.814 tINS FF 9 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/F
3.574 0.356 tNET FF 1 u_test/next_state.IDLE_s16/I0
4.338 0.765 tINS FF 2 u_test/next_state.IDLE_s16/F
4.694 0.356 tNET FF 1 u_test/next_state.CYC_DONE_s14/I2
5.303 0.609 tINS FF 3 u_test/next_state.CYC_DONE_s14/F
5.659 0.356 tNET FF 1 u_test/next_state.CMD_WAITE_s12/I3
6.123 0.464 tINS FF 2 u_test/next_state.CMD_WAITE_s12/F
6.478 0.356 tNET FF 1 u_test/next_state.CMD_WAITE_s11/I0
7.243 0.765 tINS FF 1 u_test/next_state.CMD_WAITE_s11/F
7.599 0.356 tNET FF 1 u_test/curr_state.CMD_WAITE_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
12.500 0.000 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk
12.769 0.269 tCL RR 1556 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
13.038 0.269 tNET RR 1 u_test/curr_state.CMD_WAITE_s0/CLK
12.742 -0.296 tSu 1 u_test/curr_state.CMD_WAITE_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 12.500
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 4.231, 59.927%; route: 2.490, 35.263%; tC2Q: 0.340, 4.810%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%

Path 5

Path Summary:
Slack 5.143
Data Arrival Time 7.599
Data Required Time 12.742
From u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.IDLE_s0
To u_test/curr_state.READ_BURST_s0
Launch Clk u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk
0.269 0.269 tCL RR 1556 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.538 0.269 tNET RR 1 u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.IDLE_s0/CLK
0.878 0.340 tC2Q RF 24 u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.IDLE_s0/Q
1.234 0.356 tNET FF 1 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s0/I1
2.048 0.814 tINS FF 1 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s0/F
2.404 0.356 tNET FF 1 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/I1
3.218 0.814 tINS FF 9 u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/F
3.574 0.356 tNET FF 1 u_test/next_state.IDLE_s16/I0
4.338 0.765 tINS FF 2 u_test/next_state.IDLE_s16/F
4.694 0.356 tNET FF 1 u_test/next_state.CYC_DONE_s14/I2
5.303 0.609 tINS FF 3 u_test/next_state.CYC_DONE_s14/F
5.659 0.356 tNET FF 1 u_test/next_state.READ_BURST_s13/I3
6.123 0.464 tINS FF 1 u_test/next_state.READ_BURST_s13/F
6.478 0.356 tNET FF 1 u_test/next_state.READ_BURST_s12/I0
7.243 0.765 tINS FF 1 u_test/next_state.READ_BURST_s12/F
7.599 0.356 tNET FF 1 u_test/curr_state.READ_BURST_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
12.500 0.000 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk
12.769 0.269 tCL RR 1556 u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
13.038 0.269 tNET RR 1 u_test/curr_state.READ_BURST_s0/CLK
12.742 -0.296 tSu 1 u_test/curr_state.READ_BURST_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 12.500
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 4.231, 59.927%; route: 2.490, 35.263%; tC2Q: 0.340, 4.810%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%