Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\gwide\49086\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\UHS_PSRAM_2\data\PSRAM_256_TOP.v E:\gwide\49086\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\UHS_PSRAM_2\data\apsram_256_code.v |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
| Part Number | GW1NR-LV9QN88PC6/I5 |
| Device | GW1NR-9C |
| Created Time | Wed Mar 10 08:57:17 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | UHS_PSRAM_Memory_Interface_V2_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 40.313MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 40.313MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 40.313MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 40.313MB Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 40.313MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 40.313MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 40.313MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 40.313MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 40.313MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 40.313MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 40.313MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 40.313MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 55.918MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 55.918MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 55.918MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 55.918MB |
Resource
Resource Usage Summary
| I/O Port | 126 |
| I/O Buf | 126 |
| IBUF | 79 |
| OBUF | 38 |
| IOBUF | 9 |
| Register | 410 |
| DFFP | 5 |
| DFFPE | 3 |
| DFFC | 228 |
| DFFCE | 174 |
| LUT | 673 |
| LUT2 | 208 |
| LUT3 | 203 |
| LUT4 | 262 |
| ALU | 26 |
| ALU | 26 |
| INV | 8 |
| INV | 8 |
| IOLOGIC | 27 |
| IDES4 | 8 |
| OSER4 | 11 |
| IODELAY | 8 |
| BSRAM | 1 |
| SDPX9B | 1 |
| CLOCK | 5 |
| DLL | 1 |
| CLKDIV | 2 |
| DHCEN | 2 |
Resource Utilization Summary
| Logic | 707(681 LUTs, 26 ALUs) / 8640 | 8% |
| Register | 410 / 6693 | 6% |
| --Register as Latch | 0 / 6693 | 0% |
| --Register as FF | 410 / 6693 | 6% |
| BSRAM | 1 / 26 | 4% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
| memory_clk_p | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_p_ibuf/I | ||
| clk_d | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_d_ibuf/I | ||
| u_apsram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | memory_clk_ibuf/I | memory_clk | u_apsram_top/clkdiv/CLKOUT |
| u_apsram_top/clkdivp/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | memory_clk_p_ibuf/I | memory_clk_p | u_apsram_top/clkdivp/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_d | 100.0(MHz) | 130.6(MHz) | 5 | TOP |
| 2 | u_apsram_top/clkdiv/CLKOUT.default_gen_clk | 50.0(MHz) | 122.5(MHz) | 6 | TOP |
| 3 | u_apsram_top/clkdivp/CLKOUT.default_gen_clk | 50.0(MHz) | 747.2(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.346 |
| Data Arrival Time | 8.599 |
| Data Required Time | 10.945 |
| From | u_apsram_top/u_psram_sync/lock_cnt_1_s3 |
| To | u_apsram_top/u_psram_sync/lock_cnt_12_s3 |
| Launch Clk | clk_d[R] |
| Latch Clk | clk_d[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_d | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 31 | clk_d_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK |
| 1.803 | 0.458 | tC2Q | RF | 5 | u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q |
| 2.283 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n47_s2/I1 |
| 3.382 | 1.099 | tINS | FF | 4 | u_apsram_top/u_psram_sync/n47_s2/F |
| 3.862 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n44_s3/I1 |
| 4.961 | 1.099 | tINS | FF | 6 | u_apsram_top/u_psram_sync/n44_s3/F |
| 5.441 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n39_s2/I1 |
| 6.540 | 1.099 | tINS | FF | 4 | u_apsram_top/u_psram_sync/n39_s2/F |
| 7.020 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n39_s5/I1 |
| 8.119 | 1.099 | tINS | FF | 1 | u_apsram_top/u_psram_sync/n39_s5/F |
| 8.599 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/lock_cnt_12_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_d | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 10.982 | 0.982 | tINS | RR | 31 | clk_d_ibuf/O |
| 11.345 | 0.363 | tNET | RR | 1 | u_apsram_top/u_psram_sync/lock_cnt_12_s3/CLK |
| 10.945 | -0.400 | tSu | 1 | u_apsram_top/u_psram_sync/lock_cnt_12_s3 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 2
Path Summary:| Slack | 2.346 |
| Data Arrival Time | 8.599 |
| Data Required Time | 10.945 |
| From | u_apsram_top/u_psram_sync/lock_cnt_1_s3 |
| To | u_apsram_top/u_psram_sync/lock_cnt_13_s1 |
| Launch Clk | clk_d[R] |
| Latch Clk | clk_d[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_d | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 31 | clk_d_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK |
| 1.803 | 0.458 | tC2Q | RF | 5 | u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q |
| 2.283 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n47_s2/I1 |
| 3.382 | 1.099 | tINS | FF | 4 | u_apsram_top/u_psram_sync/n47_s2/F |
| 3.862 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n44_s3/I1 |
| 4.961 | 1.099 | tINS | FF | 6 | u_apsram_top/u_psram_sync/n44_s3/F |
| 5.441 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n39_s2/I1 |
| 6.540 | 1.099 | tINS | FF | 4 | u_apsram_top/u_psram_sync/n39_s2/F |
| 7.020 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n38_s1/I1 |
| 8.119 | 1.099 | tINS | FF | 1 | u_apsram_top/u_psram_sync/n38_s1/F |
| 8.599 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/lock_cnt_13_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_d | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 10.982 | 0.982 | tINS | RR | 31 | clk_d_ibuf/O |
| 11.345 | 0.363 | tNET | RR | 1 | u_apsram_top/u_psram_sync/lock_cnt_13_s1/CLK |
| 10.945 | -0.400 | tSu | 1 | u_apsram_top/u_psram_sync/lock_cnt_13_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 3
Path Summary:| Slack | 2.413 |
| Data Arrival Time | 8.532 |
| Data Required Time | 10.945 |
| From | u_apsram_top/u_psram_sync/lock_cnt_1_s3 |
| To | u_apsram_top/u_psram_sync/lock_cnt_14_s1 |
| Launch Clk | clk_d[R] |
| Latch Clk | clk_d[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_d | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 31 | clk_d_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK |
| 1.803 | 0.458 | tC2Q | RF | 5 | u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q |
| 2.283 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n47_s2/I1 |
| 3.382 | 1.099 | tINS | FF | 4 | u_apsram_top/u_psram_sync/n47_s2/F |
| 3.862 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n44_s3/I1 |
| 4.961 | 1.099 | tINS | FF | 6 | u_apsram_top/u_psram_sync/n44_s3/F |
| 5.441 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n39_s2/I1 |
| 6.540 | 1.099 | tINS | FF | 4 | u_apsram_top/u_psram_sync/n39_s2/F |
| 7.020 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n37_s1/I0 |
| 8.052 | 1.032 | tINS | FF | 1 | u_apsram_top/u_psram_sync/n37_s1/F |
| 8.532 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/lock_cnt_14_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_d | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 10.982 | 0.982 | tINS | RR | 31 | clk_d_ibuf/O |
| 11.345 | 0.363 | tNET | RR | 1 | u_apsram_top/u_psram_sync/lock_cnt_14_s1/CLK |
| 10.945 | -0.400 | tSu | 1 | u_apsram_top/u_psram_sync/lock_cnt_14_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 4
Path Summary:| Slack | 2.623 |
| Data Arrival Time | 8.322 |
| Data Required Time | 10.945 |
| From | u_apsram_top/u_psram_sync/lock_cnt_1_s3 |
| To | u_apsram_top/u_psram_sync/lock_cnt_15_s1 |
| Launch Clk | clk_d[R] |
| Latch Clk | clk_d[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_d | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 31 | clk_d_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK |
| 1.803 | 0.458 | tC2Q | RF | 5 | u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q |
| 2.283 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n47_s2/I1 |
| 3.382 | 1.099 | tINS | FF | 4 | u_apsram_top/u_psram_sync/n47_s2/F |
| 3.862 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n44_s3/I1 |
| 4.961 | 1.099 | tINS | FF | 6 | u_apsram_top/u_psram_sync/n44_s3/F |
| 5.441 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n39_s2/I1 |
| 6.540 | 1.099 | tINS | FF | 4 | u_apsram_top/u_psram_sync/n39_s2/F |
| 7.020 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n36_s1/I2 |
| 7.842 | 0.822 | tINS | FF | 1 | u_apsram_top/u_psram_sync/n36_s1/F |
| 8.322 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/lock_cnt_15_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_d | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 10.982 | 0.982 | tINS | RR | 31 | clk_d_ibuf/O |
| 11.345 | 0.363 | tNET | RR | 1 | u_apsram_top/u_psram_sync/lock_cnt_15_s1/CLK |
| 10.945 | -0.400 | tSu | 1 | u_apsram_top/u_psram_sync/lock_cnt_15_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 5
Path Summary:| Slack | 2.690 |
| Data Arrival Time | 8.255 |
| Data Required Time | 10.945 |
| From | u_apsram_top/u_psram_sync/cs_memsync_5_s0 |
| To | u_apsram_top/u_psram_sync/flag_0_s0 |
| Launch Clk | clk_d[R] |
| Latch Clk | clk_d[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_d | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 31 | clk_d_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | u_apsram_top/u_psram_sync/cs_memsync_5_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 8 | u_apsram_top/u_psram_sync/cs_memsync_5_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n326_s13/I1 |
| 3.382 | 1.099 | tINS | FF | 3 | u_apsram_top/u_psram_sync/n326_s13/F |
| 3.862 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n348_s13/I2 |
| 4.684 | 0.822 | tINS | FF | 3 | u_apsram_top/u_psram_sync/n348_s13/F |
| 5.164 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n359_s7/I1 |
| 6.263 | 1.099 | tINS | FF | 1 | u_apsram_top/u_psram_sync/n359_s7/F |
| 6.743 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/n359_s6/I0 |
| 7.775 | 1.032 | tINS | FF | 1 | u_apsram_top/u_psram_sync/n359_s6/F |
| 8.255 | 0.480 | tNET | FF | 1 | u_apsram_top/u_psram_sync/flag_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_d | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_d_ibuf/I |
| 10.982 | 0.982 | tINS | RR | 31 | clk_d_ibuf/O |
| 11.345 | 0.363 | tNET | RR | 1 | u_apsram_top/u_psram_sync/flag_0_s0/CLK |
| 10.945 | -0.400 | tSu | 1 | u_apsram_top/u_psram_sync/flag_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 4.052, 58.637%; route: 2.400, 34.731%; tC2Q: 0.458, 6.633% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |