Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\src\a.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\src\a.sdc
GOWIN version	V1.9.7.02Beta
Part Number	GW1NR-LV9QN88PC6/I5
Device	GW1NR-9C
Created Time	Wed Mar 10 15:19:16 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C
Hold Delay Model	Fast 1.26V 0C
Numbers of Paths Analyzed	2038
Numbers of Endpoints Analyzed	2017
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk_x2p	Base	7.143	139.997	0.000	3.571			psram_memory_interface_top/u_apsram_top/clk_x2p
clk	Base	41.667	24.000	0.000	20.834			clk
clk_x1	Base	14.286	69.999	0.000	7.143			clk_x1
clk_x2	Base	7.143	139.997	0.000	3.571			psram_memory_interface_top/u_apsram_top/clk_x2
clk_d	Base	28.571	35.001	0.000	14.286			clk_d
your_instance_name/rpll_inst/CLKOUT.default_gen_clk	Generated	6.250	159.999	0.000	3.125	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUT
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Generated	6.250	159.999	3.125	0.000	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTP
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Generated	18.750	53.333	0.000	9.375	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTD3
psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT.default_gen_clk	Generated	14.286	69.999	0.000	7.142	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2p/CLKOUT	clk_x2p	psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	24.000(MHz)	183.713(MHz)	4	TOP
2	clk_x1	69.999(MHz)	73.256(MHz)	4	TOP
3	clk_d	35.001(MHz)	107.956(MHz)	4	TOP
4	psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT.default_gen_clk	69.999(MHz)	305.415(MHz)	1	TOP

No timing paths to get frequency of clk_x2p!

No timing paths to get frequency of clk_x2!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk_x2p	Setup	0.000	0
clk_x2p	Hold	0.000	0
clk	Setup	0.000	0
clk	Hold	0.000	0
clk_x1	Setup	0.000	0
clk_x1	Hold	0.000	0
clk_x2	Setup	0.000	0
clk_x2	Hold	0.000	0
clk_d	Setup	0.000	0
clk_d	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0
psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT.default_gen_clk	Setup	0.000	0
psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.635	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_63_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	13.251
2	0.828	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/curr_state.CYC_DONE_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	13.058
3	0.966	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_58_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	12.920
4	1.281	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/curr_state.WRITE_BURST_s0/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	12.605
5	1.940	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_46_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	11.946
6	2.653	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/curr_state.READ_BURST_s0/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	11.233
7	2.781	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	11.105
8	3.187	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_44_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.699
9	3.187	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_45_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.699
10	3.187	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.WRITE_CA0_s0/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.699
11	3.191	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_43_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.695
12	3.258	u_test/check_data_58_s1/Q	u_test/error_d_s0/CE	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.985
13	3.491	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_LA_s0/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.395
14	3.491	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.WRITE_LA_s0/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.395
15	3.532	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_22_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.354
16	3.532	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_39_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.354
17	3.542	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_4_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.344
18	3.542	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_8_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.344
19	3.542	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_11_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.344
20	3.542	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_12_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.344
21	3.542	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_15_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.344
22	3.542	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_18_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.344
23	3.542	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_20_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.344
24	3.542	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_21_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.344
25	3.542	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_49_s1/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.344

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.556	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CE	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.571
2	0.557	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_done_0_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CE	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.572
3	0.708	button/cnt_0_s0/Q	button/cnt_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.708
4	0.708	u_test/check_data_33_s1/Q	u_test/check_data_33_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
5	0.708	u_test/check_data_40_s1/Q	u_test/check_data_40_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
6	0.708	u_test/check_data_52_s1/Q	u_test/check_data_52_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
7	0.708	u_test/curr_state.WRITE_WAITE_s0/Q	u_test/curr_state.WRITE_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
8	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/waite_cnt_0_s3/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/waite_cnt_0_s3/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
9	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_0_s3/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_0_s3/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
10	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
11	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
12	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_4_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_4_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
13	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_5_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_5_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
14	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_7_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_7_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
15	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_1_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_1_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
16	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
17	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_1_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_1_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
18	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
19	0.708	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_2_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_2_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
20	0.708	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_cnt_3_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_cnt_3_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
21	0.708	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.708
22	0.709	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/D	clk_d:[R]	clk_d:[R]	0.000	0.000	0.709
23	0.709	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/D	clk_d:[R]	clk_d:[R]	0.000	0.000	0.709
24	0.709	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/D	clk_d:[R]	clk_d:[R]	0.000	0.000	0.709
25	0.709	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0/D	clk_d:[R]	clk_d:[R]	0.000	0.000	0.709

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	5.819	7.069	1.250	Low Pulse Width	clk_x1	psram_memory_interface_top/u_apsram_top/rd_data_d_31_s0
2	5.819	7.069	1.250	Low Pulse Width	clk_x1	psram_memory_interface_top/u_apsram_top/rd_data_d_30_s0
3	5.819	7.069	1.250	Low Pulse Width	clk_x1	psram_memory_interface_top/u_apsram_top/rd_data_d_29_s0
4	5.819	7.069	1.250	Low Pulse Width	clk_x1	psram_memory_interface_top/u_apsram_top/rd_data_d_28_s0
5	5.819	7.069	1.250	Low Pulse Width	clk_x1	psram_memory_interface_top/u_apsram_top/rd_data_d_26_s0
6	5.819	7.069	1.250	Low Pulse Width	clk_x1	psram_memory_interface_top/u_apsram_top/rd_data_d_25_s0
7	5.819	7.069	1.250	Low Pulse Width	clk_x1	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_d_3_s0
8	5.819	7.069	1.250	Low Pulse Width	clk_x1	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_3_s1
9	5.819	7.069	1.250	Low Pulse Width	clk_x1	u_test/rd_data_d_14_s0
10	5.819	7.069	1.250	Low Pulse Width	clk_x1	u_test/rd_data_d_15_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.635
Data Arrival Time	13.493
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_63_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
12.394	4.928	tNET	FF	1	R21C28[2][B]	u_test/n1267_s1/I2
13.493	1.099	tINS	FF	1	R21C28[2][B]	u_test/n1267_s1/F
13.493	0.000	tNET	FF	1	R21C28[2][B]	u_test/check_data_63_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R21C28[2][B]	u_test/check_data_63_s1/CLK
14.128	-0.400	tSu		1	R21C28[2][B]	u_test/check_data_63_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 22.286%; route: 9.839, 74.256%; tC2Q: 0.458, 3.459%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path2

Path Summary:

Slack	0.828
Data Arrival Time	13.300
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/curr_state.CYC_DONE_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.469	2.114	tNET	FF	1	R16C20[3][A]	u_test/next_state.CMD_WAITE_s16/I1
7.530	1.061	tINS	FR	5	R16C20[3][A]	u_test/next_state.CMD_WAITE_s16/F
7.961	0.431	tNET	RR	1	R17C20[3][B]	u_test/next_state.WRITE_BURST_s17/I2
8.993	1.032	tINS	RF	2	R17C20[3][B]	u_test/next_state.WRITE_BURST_s17/F
10.771	1.778	tNET	FF	1	R17C21[3][B]	u_test/next_state.CYC_DONE_WAITE_s15/I2
11.397	0.626	tINS	FF	1	R17C21[3][B]	u_test/next_state.CYC_DONE_WAITE_s15/F
12.201	0.804	tNET	FF	1	R17C22[2][B]	u_test/next_state.CYC_DONE_WAITE_s14/I0
13.300	1.099	tINS	FF	1	R17C22[2][B]	u_test/next_state.CYC_DONE_WAITE_s14/F
13.300	0.000	tNET	FF	1	R17C22[2][B]	u_test/curr_state.CYC_DONE_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R17C22[2][B]	u_test/curr_state.CYC_DONE_WAITE_s0/CLK
14.128	-0.400	tSu		1	R17C22[2][B]	u_test/curr_state.CYC_DONE_WAITE_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 4.850, 37.142%; route: 7.750, 59.348%; tC2Q: 0.458, 3.510%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path3

Path Summary:

Slack	0.966
Data Arrival Time	13.162
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_58_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
12.063	4.597	tNET	FF	1	R21C28[1][A]	u_test/n1272_s1/I2
13.162	1.099	tINS	FF	1	R21C28[1][A]	u_test/n1272_s1/F
13.162	0.000	tNET	FF	1	R21C28[1][A]	u_test/check_data_58_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R21C28[1][A]	u_test/check_data_58_s1/CLK
14.128	-0.400	tSu		1	R21C28[1][A]	u_test/check_data_58_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 22.856%; route: 9.509, 73.596%; tC2Q: 0.458, 3.547%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path4

Path Summary:

Slack	1.281
Data Arrival Time	12.847
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/curr_state.WRITE_BURST_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.469	2.114	tNET	FF	1	R16C20[3][A]	u_test/next_state.CMD_WAITE_s16/I1
7.530	1.061	tINS	FR	5	R16C20[3][A]	u_test/next_state.CMD_WAITE_s16/F
7.961	0.431	tNET	RR	1	R17C20[3][B]	u_test/next_state.WRITE_BURST_s17/I2
8.993	1.032	tINS	RF	2	R17C20[3][B]	u_test/next_state.WRITE_BURST_s17/F
10.771	1.778	tNET	FF	1	R17C21[2][B]	u_test/next_state.WRITE_BURST_s14/I3
11.396	0.625	tINS	FR	1	R17C21[2][B]	u_test/next_state.WRITE_BURST_s14/F
11.815	0.419	tNET	RR	1	R16C21[1][A]	u_test/next_state.WRITE_BURST_s12/I3
12.847	1.032	tINS	RF	1	R16C21[1][A]	u_test/next_state.WRITE_BURST_s12/F
12.847	0.000	tNET	FF	1	R16C21[1][A]	u_test/curr_state.WRITE_BURST_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R16C21[1][A]	u_test/curr_state.WRITE_BURST_s0/CLK
14.128	-0.400	tSu		1	R16C21[1][A]	u_test/curr_state.WRITE_BURST_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 4.782, 37.938%; route: 7.364, 58.425%; tC2Q: 0.458, 3.636%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack	1.940
Data Arrival Time	12.188
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_46_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
11.089	3.623	tNET	FF	1	R20C26[2][A]	u_test/n1284_s1/I2
12.188	1.099	tINS	FF	1	R20C26[2][A]	u_test/n1284_s1/F
12.188	0.000	tNET	FF	1	R20C26[2][A]	u_test/check_data_46_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R20C26[2][A]	u_test/check_data_46_s1/CLK
14.128	-0.400	tSu		1	R20C26[2][A]	u_test/check_data_46_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 24.719%; route: 8.535, 71.444%; tC2Q: 0.458, 3.837%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack	2.653
Data Arrival Time	11.475
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/curr_state.READ_BURST_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.469	2.114	tNET	FF	1	R16C20[3][A]	u_test/next_state.CMD_WAITE_s16/I1
7.530	1.061	tINS	FR	5	R16C20[3][A]	u_test/next_state.CMD_WAITE_s16/F
7.961	0.431	tNET	RR	1	R17C20[2][B]	u_test/next_state.READ_BURST_s17/I3
8.993	1.032	tINS	RF	1	R17C20[2][B]	u_test/next_state.READ_BURST_s17/F
8.998	0.005	tNET	FF	1	R17C20[1][A]	u_test/next_state.READ_BURST_s18/I3
10.024	1.026	tINS	FR	1	R17C20[1][A]	u_test/next_state.READ_BURST_s18/F
10.443	0.419	tNET	RR	1	R16C20[1][A]	u_test/next_state.READ_BURST_s14/I0
11.475	1.032	tINS	RF	1	R16C20[1][A]	u_test/next_state.READ_BURST_s14/F
11.475	0.000	tNET	FF	1	R16C20[1][A]	u_test/curr_state.READ_BURST_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R16C20[1][A]	u_test/curr_state.READ_BURST_s0/CLK
14.128	-0.400	tSu		1	R16C20[1][A]	u_test/curr_state.READ_BURST_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 5.183, 46.140%; route: 5.592, 49.780%; tC2Q: 0.458, 4.080%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path7

Path Summary:

Slack	2.781
Data Arrival Time	11.347
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.333	2.633	tNET	FF	1	R16C32[3][A]	psram_memory_interface_top/u_apsram_top/cmd_en_d_s0/I2
4.365	1.032	tINS	FF	14	R16C32[3][A]	psram_memory_interface_top/u_apsram_top/cmd_en_d_s0/F
5.526	1.161	tNET	FF	1	R20C31[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s20/I0
6.558	1.032	tINS	FF	2	R20C31[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s20/F
7.703	1.145	tNET	FF	1	R20C37[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s18/I1
8.525	0.822	tINS	FF	9	R20C37[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s18/F
10.315	1.790	tNET	FF	1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.READ_CA0_s17/I2
11.347	1.032	tINS	FF	1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.READ_CA0_s17/F
11.347	0.000	tNET	FF	1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0/CLK
14.128	-0.400	tSu		1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.918, 35.282%; route: 6.728, 60.591%; tC2Q: 0.458, 4.127%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack	3.187
Data Arrival Time	10.941
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_44_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
10.119	2.653	tNET	FF	1	R20C15[1][A]	u_test/n1286_s1/I2
10.941	0.822	tINS	FF	1	R20C15[1][A]	u_test/n1286_s1/F
10.941	0.000	tNET	FF	1	R20C15[1][A]	u_test/check_data_44_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R20C15[1][A]	u_test/check_data_44_s1/CLK
14.128	-0.400	tSu		1	R20C15[1][A]	u_test/check_data_44_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.676, 25.011%; route: 7.565, 70.705%; tC2Q: 0.458, 4.284%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack	3.187
Data Arrival Time	10.941
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_45_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
10.119	2.653	tNET	FF	1	R20C15[0][B]	u_test/n1285_s1/I2
10.941	0.822	tINS	FF	1	R20C15[0][B]	u_test/n1285_s1/F
10.941	0.000	tNET	FF	1	R20C15[0][B]	u_test/check_data_45_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R20C15[0][B]	u_test/check_data_45_s1/CLK
14.128	-0.400	tSu		1	R20C15[0][B]	u_test/check_data_45_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.676, 25.011%; route: 7.565, 70.705%; tC2Q: 0.458, 4.284%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path10

Path Summary:

Slack	3.187
Data Arrival Time	10.941
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.WRITE_CA0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.333	2.633	tNET	FF	1	R16C32[3][A]	psram_memory_interface_top/u_apsram_top/cmd_en_d_s0/I2
4.365	1.032	tINS	FF	14	R16C32[3][A]	psram_memory_interface_top/u_apsram_top/cmd_en_d_s0/F
5.526	1.161	tNET	FF	1	R20C31[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s20/I0
6.558	1.032	tINS	FF	2	R20C31[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s20/F
7.703	1.145	tNET	FF	1	R20C37[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s18/I1
8.525	0.822	tINS	FF	9	R20C37[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s18/F
10.315	1.790	tNET	FF	1	R17C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.WRITE_CA0_s17/I2
10.941	0.626	tINS	FF	1	R17C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.WRITE_CA0_s17/F
10.941	0.000	tNET	FF	1	R17C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.WRITE_CA0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R17C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.WRITE_CA0_s0/CLK
14.128	-0.400	tSu		1	R17C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.WRITE_CA0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.512, 32.826%; route: 6.728, 62.890%; tC2Q: 0.458, 4.284%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack	3.191
Data Arrival Time	10.937
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_43_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
10.115	2.649	tNET	FF	1	R20C17[0][A]	u_test/n1287_s1/I0
10.937	0.822	tINS	FF	1	R20C17[0][A]	u_test/n1287_s1/F
10.937	0.000	tNET	FF	1	R20C17[0][A]	u_test/check_data_43_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R20C17[0][A]	u_test/check_data_43_s1/CLK
14.128	-0.400	tSu		1	R20C17[0][A]	u_test/check_data_43_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.676, 25.022%; route: 7.560, 70.692%; tC2Q: 0.458, 4.286%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack	3.258
Data Arrival Time	11.227
Data Required Time	14.485
From	u_test/check_data_58_s1
To	u_test/error_d_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R21C28[1][A]	u_test/check_data_58_s1/CLK
0.700	0.458	tC2Q	RF	6	R21C28[1][A]	u_test/check_data_58_s1/Q
3.129	2.428	tNET	FF	1	R18C15[3][B]	u_test/n1495_s23/I2
4.155	1.026	tINS	FR	1	R18C15[3][B]	u_test/n1495_s23/F
4.573	0.419	tNET	RR	1	R18C16[3][B]	u_test/n1495_s12/I1
5.672	1.099	tINS	RF	1	R18C16[3][B]	u_test/n1495_s12/F
7.126	1.453	tNET	FF	1	R17C26[1][B]	u_test/n1495_s3/I1
7.751	0.625	tINS	FR	1	R17C26[1][B]	u_test/n1495_s3/F
8.170	0.419	tNET	RR	1	R17C27[2][B]	u_test/n1495_s0/I2
9.196	1.026	tINS	RR	1	R17C27[2][B]	u_test/n1495_s0/F
11.227	2.031	tNET	RR	1	IOR24[A]	u_test/error_d_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	IOR24[A]	u_test/error_d_s0/CLK
14.485	-0.043	tSu		1	IOR24[A]	u_test/error_d_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.776, 34.374%; route: 6.751, 61.453%; tC2Q: 0.458, 4.172%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path13

Path Summary:

Slack	3.491
Data Arrival Time	10.637
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_LA_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.333	2.633	tNET	FF	1	R16C32[3][A]	psram_memory_interface_top/u_apsram_top/cmd_en_d_s0/I2
4.365	1.032	tINS	FF	14	R16C32[3][A]	psram_memory_interface_top/u_apsram_top/cmd_en_d_s0/F
5.526	1.161	tNET	FF	1	R20C31[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s20/I0
6.558	1.032	tINS	FF	2	R20C31[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s20/F
7.703	1.145	tNET	FF	1	R20C37[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s18/I1
8.525	0.822	tINS	FF	9	R20C37[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s18/F
10.011	1.486	tNET	FF	1	R21C31[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.READ_LA_s17/I0
10.637	0.626	tINS	FF	1	R21C31[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.READ_LA_s17/F
10.637	0.000	tNET	FF	1	R21C31[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_LA_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R21C31[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_LA_s0/CLK
14.128	-0.400	tSu		1	R21C31[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_LA_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.512, 33.785%; route: 6.425, 61.806%; tC2Q: 0.458, 4.409%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack	3.491
Data Arrival Time	10.637
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.WRITE_LA_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.333	2.633	tNET	FF	1	R16C32[3][A]	psram_memory_interface_top/u_apsram_top/cmd_en_d_s0/I2
4.365	1.032	tINS	FF	14	R16C32[3][A]	psram_memory_interface_top/u_apsram_top/cmd_en_d_s0/F
5.526	1.161	tNET	FF	1	R20C31[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s20/I0
6.558	1.032	tINS	FF	2	R20C31[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s20/F
7.703	1.145	tNET	FF	1	R20C37[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s18/I1
8.525	0.822	tINS	FF	9	R20C37[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.IDLE_s18/F
10.011	1.486	tNET	FF	1	R21C31[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.WRITE_LA_s17/I0
10.637	0.626	tINS	FF	1	R21C31[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.WRITE_LA_s17/F
10.637	0.000	tNET	FF	1	R21C31[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.WRITE_LA_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R21C31[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.WRITE_LA_s0/CLK
14.128	-0.400	tSu		1	R21C31[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.WRITE_LA_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.512, 33.785%; route: 6.425, 61.806%; tC2Q: 0.458, 4.409%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack	3.532
Data Arrival Time	10.596
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_22_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.497	2.031	tNET	FF	1	R15C15[1][A]	u_test/n1308_s1/I2
10.596	1.099	tINS	FF	1	R15C15[1][A]	u_test/n1308_s1/F
10.596	0.000	tNET	FF	1	R15C15[1][A]	u_test/check_data_22_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R15C15[1][A]	u_test/check_data_22_s1/CLK
14.128	-0.400	tSu		1	R15C15[1][A]	u_test/check_data_22_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.520%; route: 6.943, 67.054%; tC2Q: 0.458, 4.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack	3.532
Data Arrival Time	10.596
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_39_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.497	2.031	tNET	FF	1	R15C15[2][A]	u_test/n1291_s1/I2
10.596	1.099	tINS	FF	1	R15C15[2][A]	u_test/n1291_s1/F
10.596	0.000	tNET	FF	1	R15C15[2][A]	u_test/check_data_39_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R15C15[2][A]	u_test/check_data_39_s1/CLK
14.128	-0.400	tSu		1	R15C15[2][A]	u_test/check_data_39_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.520%; route: 6.943, 67.054%; tC2Q: 0.458, 4.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack	3.542
Data Arrival Time	10.586
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_4_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.487	2.022	tNET	FF	1	R16C16[1][A]	u_test/n1326_s1/I0
10.586	1.099	tINS	FF	1	R16C16[1][A]	u_test/n1326_s1/F
10.586	0.000	tNET	FF	1	R16C16[1][A]	u_test/check_data_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R16C16[1][A]	u_test/check_data_4_s1/CLK
14.128	-0.400	tSu		1	R16C16[1][A]	u_test/check_data_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.547%; route: 6.933, 67.022%; tC2Q: 0.458, 4.431%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack	3.542
Data Arrival Time	10.586
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_8_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.487	2.022	tNET	FF	1	R16C15[2][A]	u_test/n1322_s4/I0
10.586	1.099	tINS	FF	1	R16C15[2][A]	u_test/n1322_s4/F
10.586	0.000	tNET	FF	1	R16C15[2][A]	u_test/check_data_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R16C15[2][A]	u_test/check_data_8_s1/CLK
14.128	-0.400	tSu		1	R16C15[2][A]	u_test/check_data_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.547%; route: 6.933, 67.022%; tC2Q: 0.458, 4.431%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack	3.542
Data Arrival Time	10.586
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_11_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.487	2.022	tNET	FF	1	R16C16[2][B]	u_test/n1319_s1/I0
10.586	1.099	tINS	FF	1	R16C16[2][B]	u_test/n1319_s1/F
10.586	0.000	tNET	FF	1	R16C16[2][B]	u_test/check_data_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R16C16[2][B]	u_test/check_data_11_s1/CLK
14.128	-0.400	tSu		1	R16C16[2][B]	u_test/check_data_11_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.547%; route: 6.933, 67.022%; tC2Q: 0.458, 4.431%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack	3.542
Data Arrival Time	10.586
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_12_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.487	2.022	tNET	FF	1	R16C16[2][A]	u_test/n1318_s1/I2
10.586	1.099	tINS	FF	1	R16C16[2][A]	u_test/n1318_s1/F
10.586	0.000	tNET	FF	1	R16C16[2][A]	u_test/check_data_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R16C16[2][A]	u_test/check_data_12_s1/CLK
14.128	-0.400	tSu		1	R16C16[2][A]	u_test/check_data_12_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.547%; route: 6.933, 67.022%; tC2Q: 0.458, 4.431%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack	3.542
Data Arrival Time	10.586
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_15_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.487	2.022	tNET	FF	1	R16C15[1][A]	u_test/n1315_s1/I0
10.586	1.099	tINS	FF	1	R16C15[1][A]	u_test/n1315_s1/F
10.586	0.000	tNET	FF	1	R16C15[1][A]	u_test/check_data_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R16C15[1][A]	u_test/check_data_15_s1/CLK
14.128	-0.400	tSu		1	R16C15[1][A]	u_test/check_data_15_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.547%; route: 6.933, 67.022%; tC2Q: 0.458, 4.431%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack	3.542
Data Arrival Time	10.586
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_18_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.487	2.022	tNET	FF	1	R15C16[2][A]	u_test/n1312_s1/I0
10.586	1.099	tINS	FF	1	R15C16[2][A]	u_test/n1312_s1/F
10.586	0.000	tNET	FF	1	R15C16[2][A]	u_test/check_data_18_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R15C16[2][A]	u_test/check_data_18_s1/CLK
14.128	-0.400	tSu		1	R15C16[2][A]	u_test/check_data_18_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.547%; route: 6.933, 67.022%; tC2Q: 0.458, 4.431%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack	3.542
Data Arrival Time	10.586
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_20_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.487	2.022	tNET	FF	1	R15C16[2][B]	u_test/n1310_s1/I0
10.586	1.099	tINS	FF	1	R15C16[2][B]	u_test/n1310_s1/F
10.586	0.000	tNET	FF	1	R15C16[2][B]	u_test/check_data_20_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R15C16[2][B]	u_test/check_data_20_s1/CLK
14.128	-0.400	tSu		1	R15C16[2][B]	u_test/check_data_20_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.547%; route: 6.933, 67.022%; tC2Q: 0.458, 4.431%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack	3.542
Data Arrival Time	10.586
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_21_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.487	2.022	tNET	FF	1	R15C16[1][A]	u_test/n1309_s1/I2
10.586	1.099	tINS	FF	1	R15C16[1][A]	u_test/n1309_s1/F
10.586	0.000	tNET	FF	1	R15C16[1][A]	u_test/check_data_21_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R15C16[1][A]	u_test/check_data_21_s1/CLK
14.128	-0.400	tSu		1	R15C16[1][A]	u_test/check_data_21_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.547%; route: 6.933, 67.022%; tC2Q: 0.458, 4.431%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack	3.542
Data Arrival Time	10.586
Data Required Time	14.128
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_49_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	110	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.324	2.623	tNET	FF	1	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.356	1.032	tINS	FF	5	R15C33[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.644	2.288	tNET	FF	1	R17C19[0][A]	u_test/next_state.IDLE_s15/I0
7.466	0.822	tINS	FF	63	R17C19[0][A]	u_test/next_state.IDLE_s15/F
9.487	2.022	tNET	FF	1	R17C16[1][A]	u_test/n1281_s1/I2
10.586	1.099	tINS	FF	1	R17C16[1][A]	u_test/n1281_s1/F
10.586	0.000	tNET	FF	1	R17C16[1][A]	u_test/check_data_49_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.528	0.242	tNET	RR	1	R17C16[1][A]	u_test/check_data_49_s1/CLK
14.128	-0.400	tSu		1	R17C16[1][A]	u_test/check_data_49_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.547%; route: 6.933, 67.022%; tC2Q: 0.458, 4.431%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.556
Data Arrival Time	0.754
Data Required Time	0.198
From	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C36[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.516	0.333	tC2Q	RR	2	R13C36[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q
0.754	0.238	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.198	0.015	tHld		1	R13C36[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path2

Path Summary:

Slack	0.557
Data Arrival Time	0.755
Data Required Time	0.198
From	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_done_0_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_done_0_s0/CLK
0.516	0.333	tC2Q	RR	4	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_done_0_s0/Q
0.755	0.239	tNET	RR	1	R13C33[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C33[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.198	0.015	tHld		1	R13C33[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path3

Path Summary:

Slack	0.708
Data Arrival Time	2.570
Data Required Time	1.862
From	button/cnt_0_s0
To	button/cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R11C20[0][A]	button/cnt_0_s0/CLK
2.195	0.333	tC2Q	RR	3	R11C20[0][A]	button/cnt_0_s0/Q
2.198	0.002	tNET	RR	1	R11C20[0][A]	button/n35_s2/I
2.570	0.372	tINS	RF	1	R11C20[0][A]	button/n35_s2/O
2.570	0.000	tNET	FF	1	R11C20[0][A]	button/cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R11C20[0][A]	button/cnt_0_s0/CLK
1.862	0.000	tHld		1	R11C20[0][A]	button/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path4

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	u_test/check_data_33_s1
To	u_test/check_data_33_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R14C16[0][A]	u_test/check_data_33_s1/CLK
0.516	0.333	tC2Q	RR	5	R14C16[0][A]	u_test/check_data_33_s1/Q
0.519	0.002	tNET	RR	1	R14C16[0][A]	u_test/n1297_s1/I1
0.891	0.372	tINS	RF	1	R14C16[0][A]	u_test/n1297_s1/F
0.891	0.000	tNET	FF	1	R14C16[0][A]	u_test/check_data_33_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R14C16[0][A]	u_test/check_data_33_s1/CLK
0.183	0.000	tHld		1	R14C16[0][A]	u_test/check_data_33_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path5

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	u_test/check_data_40_s1
To	u_test/check_data_40_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R17C15[0][A]	u_test/check_data_40_s1/CLK
0.516	0.333	tC2Q	RR	4	R17C15[0][A]	u_test/check_data_40_s1/Q
0.519	0.002	tNET	RR	1	R17C15[0][A]	u_test/n1290_s1/I3
0.891	0.372	tINS	RF	1	R17C15[0][A]	u_test/n1290_s1/F
0.891	0.000	tNET	FF	1	R17C15[0][A]	u_test/check_data_40_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R17C15[0][A]	u_test/check_data_40_s1/CLK
0.183	0.000	tHld		1	R17C15[0][A]	u_test/check_data_40_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path6

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	u_test/check_data_52_s1
To	u_test/check_data_52_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R17C14[0][A]	u_test/check_data_52_s1/CLK
0.516	0.333	tC2Q	RR	3	R17C14[0][A]	u_test/check_data_52_s1/Q
0.519	0.002	tNET	RR	1	R17C14[0][A]	u_test/n1278_s1/I3
0.891	0.372	tINS	RF	1	R17C14[0][A]	u_test/n1278_s1/F
0.891	0.000	tNET	FF	1	R17C14[0][A]	u_test/check_data_52_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R17C14[0][A]	u_test/check_data_52_s1/CLK
0.183	0.000	tHld		1	R17C14[0][A]	u_test/check_data_52_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path7

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	u_test/curr_state.WRITE_WAITE_s0
To	u_test/curr_state.WRITE_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R16C23[0][A]	u_test/curr_state.WRITE_WAITE_s0/CLK
0.516	0.333	tC2Q	RR	2	R16C23[0][A]	u_test/curr_state.WRITE_WAITE_s0/Q
0.519	0.002	tNET	RR	1	R16C23[0][A]	u_test/next_state.WRITE_WAITE_s12/I3
0.891	0.372	tINS	RF	1	R16C23[0][A]	u_test/next_state.WRITE_WAITE_s12/F
0.891	0.000	tNET	FF	1	R16C23[0][A]	u_test/curr_state.WRITE_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R16C23[0][A]	u_test/curr_state.WRITE_WAITE_s0/CLK
0.183	0.000	tHld		1	R16C23[0][A]	u_test/curr_state.WRITE_WAITE_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path8

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/waite_cnt_0_s3
To	psram_memory_interface_top/u_apsram_top/u_psram_init/waite_cnt_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/waite_cnt_0_s3/CLK
0.516	0.333	tC2Q	RR	5	R12C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/waite_cnt_0_s3/Q
0.519	0.002	tNET	RR	1	R12C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n554_s4/I0
0.891	0.372	tINS	RF	1	R12C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n554_s4/F
0.891	0.000	tNET	FF	1	R12C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/waite_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/waite_cnt_0_s3/CLK
0.183	0.000	tHld		1	R12C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/waite_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path9

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_0_s3
To	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R9C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_0_s3/CLK
0.516	0.333	tC2Q	RR	6	R9C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_0_s3/Q
0.519	0.002	tNET	RR	1	R9C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n465_s3/I0
0.891	0.372	tINS	RF	1	R9C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n465_s3/F
0.891	0.000	tNET	FF	1	R9C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R9C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_0_s3/CLK
0.183	0.000	tHld		1	R9C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path10

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C37[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/CLK
0.516	0.333	tC2Q	RR	3	R15C37[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/Q
0.519	0.002	tNET	RR	1	R15C37[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1372_s3/I1
0.891	0.372	tINS	RF	1	R15C37[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1372_s3/F
0.891	0.000	tNET	FF	1	R15C37[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C37[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/CLK
0.183	0.000	tHld		1	R15C37[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path11

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C38[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/CLK
0.516	0.333	tC2Q	RR	3	R15C38[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/Q
0.519	0.002	tNET	RR	1	R15C38[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1369_s1/I3
0.891	0.372	tINS	RF	1	R15C38[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1369_s1/F
0.891	0.000	tNET	FF	1	R15C38[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C38[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/CLK
0.183	0.000	tHld		1	R15C38[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path12

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_4_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_4_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R14C39[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_4_s1/CLK
0.516	0.333	tC2Q	RR	2	R14C39[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_4_s1/Q
0.519	0.002	tNET	RR	1	R14C39[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1287_s1/I3
0.891	0.372	tINS	RF	1	R14C39[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1287_s1/F
0.891	0.000	tNET	FF	1	R14C39[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R14C39[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_4_s1/CLK
0.183	0.000	tHld		1	R14C39[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path13

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_5_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_5_s1/CLK
0.516	0.333	tC2Q	RR	5	R15C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_5_s1/Q
0.519	0.002	tNET	RR	1	R15C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1286_s1/I1
0.891	0.372	tINS	RF	1	R15C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1286_s1/F
0.891	0.000	tNET	FF	1	R15C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_5_s1/CLK
0.183	0.000	tHld		1	R15C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path14

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_7_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_7_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_7_s1/CLK
0.516	0.333	tC2Q	RR	3	R15C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_7_s1/Q
0.519	0.002	tNET	RR	1	R15C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1284_s1/I3
0.891	0.372	tINS	RF	1	R15C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1284_s1/F
0.891	0.000	tNET	FF	1	R15C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_7_s1/CLK
0.183	0.000	tHld		1	R15C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path15

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_1_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R9C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_1_s1/CLK
0.516	0.333	tC2Q	RR	5	R9C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_1_s1/Q
0.519	0.002	tNET	RR	1	R9C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n464_s1/I1
0.891	0.372	tINS	RF	1	R9C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n464_s1/F
0.891	0.000	tNET	FF	1	R9C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R9C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_1_s1/CLK
0.183	0.000	tHld		1	R9C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path16

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R9C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/CLK
0.516	0.333	tC2Q	RR	3	R9C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/Q
0.519	0.002	tNET	RR	1	R9C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n462_s1/I3
0.891	0.372	tINS	RF	1	R9C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n462_s1/F
0.891	0.000	tNET	FF	1	R9C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R9C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/CLK
0.183	0.000	tHld		1	R9C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path17

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_1_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_1_s0/CLK
0.516	0.333	tC2Q	RR	3	R15C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_1_s0/Q
0.519	0.002	tNET	RR	1	R15C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1454_s1/I1
0.891	0.372	tINS	RF	1	R15C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1454_s1/F
0.891	0.000	tNET	FF	1	R15C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_1_s0/CLK
0.183	0.000	tHld		1	R15C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path18

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/CLK
0.516	0.333	tC2Q	RR	2	R13C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/Q
0.519	0.002	tNET	RR	1	R13C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_WAITE_s27/I3
0.891	0.372	tINS	RF	1	R13C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_WAITE_s27/F
0.891	0.000	tNET	FF	1	R13C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/CLK
0.183	0.000	tHld		1	R13C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path19

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_2_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R17C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_2_s1/CLK
0.516	0.333	tC2Q	RR	4	R17C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_2_s1/Q
0.519	0.002	tNET	RR	1	R17C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n1031_s1/I2
0.891	0.372	tINS	RF	1	R17C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n1031_s1/F
0.891	0.000	tNET	FF	1	R17C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R17C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_2_s1/CLK
0.183	0.000	tHld		1	R17C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path20

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_cnt_3_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_cnt_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R21C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_cnt_3_s1/CLK
0.516	0.333	tC2Q	RR	3	R21C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_cnt_3_s1/Q
0.519	0.002	tNET	RR	1	R21C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n423_s1/I3
0.891	0.372	tINS	RF	1	R21C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n423_s1/F
0.891	0.000	tNET	FF	1	R21C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R21C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_cnt_3_s1/CLK
0.183	0.000	tHld		1	R21C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path21

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0/CLK
0.516	0.333	tC2Q	RR	4	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0/Q
0.519	0.002	tNET	RR	1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.READ_CA0_s17/I3
0.891	0.372	tINS	RF	1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n_state.READ_CA0_s17/F
0.891	0.000	tNET	FF	1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	690	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0/CLK
0.183	0.000	tHld		1	R17C30[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.READ_CA0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path22

Path Summary:

Slack	0.709
Data Arrival Time	0.893
Data Required Time	0.185
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3
Launch Clk	clk_d:[R]
Latch Clk	clk_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
0.185	0.185	tNET	RR	1	R11C23[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK
0.518	0.333	tC2Q	RR	5	R11C23[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q
0.521	0.004	tNET	RR	1	R11C23[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n50_s4/I2
0.893	0.372	tINS	RF	1	R11C23[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n50_s4/F
0.893	0.000	tNET	FF	1	R11C23[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
0.185	0.185	tNET	RR	1	R11C23[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK
0.185	0.000	tHld		1	R11C23[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path23

Path Summary:

Slack	0.709
Data Arrival Time	0.893
Data Required Time	0.185
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1
Launch Clk	clk_d:[R]
Latch Clk	clk_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
0.185	0.185	tNET	RR	1	R11C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/CLK
0.518	0.333	tC2Q	RR	5	R11C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/Q
0.521	0.004	tNET	RR	1	R11C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n43_s1/I2
0.893	0.372	tINS	RF	1	R11C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n43_s1/F
0.893	0.000	tNET	FF	1	R11C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
0.185	0.185	tNET	RR	1	R11C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/CLK
0.185	0.000	tHld		1	R11C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path24

Path Summary:

Slack	0.709
Data Arrival Time	0.893
Data Required Time	0.185
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1
Launch Clk	clk_d:[R]
Latch Clk	clk_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
0.185	0.185	tNET	RR	1	R12C25[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/CLK
0.518	0.333	tC2Q	RR	3	R12C25[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/Q
0.521	0.004	tNET	RR	1	R12C25[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n40_s1/I2
0.893	0.372	tINS	RF	1	R12C25[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n40_s1/F
0.893	0.000	tNET	FF	1	R12C25[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
0.185	0.185	tNET	RR	1	R12C25[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/CLK
0.185	0.000	tHld		1	R12C25[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path25

Path Summary:

Slack	0.709
Data Arrival Time	0.893
Data Required Time	0.185
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0
Launch Clk	clk_d:[R]
Latch Clk	clk_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
0.185	0.185	tNET	RR	1	R16C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0/CLK
0.518	0.333	tC2Q	RR	6	R16C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0/Q
0.521	0.004	tNET	RR	1	R16C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n387_s3/I0
0.893	0.372	tINS	RF	1	R16C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n387_s3/F
0.893	0.000	tNET	FF	1	R16C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
0.185	0.185	tNET	RR	1	R16C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0/CLK
0.185	0.000	tHld		1	R16C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	5.819
Actual Width:	7.069
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	psram_memory_interface_top/u_apsram_top/rd_data_d_31_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.400	0.257	tNET	FF	psram_memory_interface_top/u_apsram_top/rd_data_d_31_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.469	0.183	tNET	RR	psram_memory_interface_top/u_apsram_top/rd_data_d_31_s0/CLK

MPW2

MPW Summary:

Slack:	5.819
Actual Width:	7.069
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	psram_memory_interface_top/u_apsram_top/rd_data_d_30_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.400	0.257	tNET	FF	psram_memory_interface_top/u_apsram_top/rd_data_d_30_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.469	0.183	tNET	RR	psram_memory_interface_top/u_apsram_top/rd_data_d_30_s0/CLK

MPW3

MPW Summary:

Slack:	5.819
Actual Width:	7.069
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	psram_memory_interface_top/u_apsram_top/rd_data_d_29_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.400	0.257	tNET	FF	psram_memory_interface_top/u_apsram_top/rd_data_d_29_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.469	0.183	tNET	RR	psram_memory_interface_top/u_apsram_top/rd_data_d_29_s0/CLK

MPW4

MPW Summary:

Slack:	5.819
Actual Width:	7.069
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	psram_memory_interface_top/u_apsram_top/rd_data_d_28_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.400	0.257	tNET	FF	psram_memory_interface_top/u_apsram_top/rd_data_d_28_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.469	0.183	tNET	RR	psram_memory_interface_top/u_apsram_top/rd_data_d_28_s0/CLK

MPW5

MPW Summary:

Slack:	5.819
Actual Width:	7.069
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	psram_memory_interface_top/u_apsram_top/rd_data_d_26_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.400	0.257	tNET	FF	psram_memory_interface_top/u_apsram_top/rd_data_d_26_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.469	0.183	tNET	RR	psram_memory_interface_top/u_apsram_top/rd_data_d_26_s0/CLK

MPW6

MPW Summary:

Slack:	5.819
Actual Width:	7.069
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	psram_memory_interface_top/u_apsram_top/rd_data_d_25_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.400	0.257	tNET	FF	psram_memory_interface_top/u_apsram_top/rd_data_d_25_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.469	0.183	tNET	RR	psram_memory_interface_top/u_apsram_top/rd_data_d_25_s0/CLK

MPW7

MPW Summary:

Slack:	5.819
Actual Width:	7.069
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_d_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.400	0.257	tNET	FF	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_d_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.469	0.183	tNET	RR	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_d_3_s0/CLK

MPW8

MPW Summary:

Slack:	5.819
Actual Width:	7.069
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_3_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.400	0.257	tNET	FF	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_3_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.469	0.183	tNET	RR	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ss_3_s1/CLK

MPW9

MPW Summary:

Slack:	5.819
Actual Width:	7.069
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_test/rd_data_d_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.400	0.257	tNET	FF	u_test/rd_data_d_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.469	0.183	tNET	RR	u_test/rd_data_d_14_s0/CLK

MPW10

MPW Summary:

Slack:	5.819
Actual Width:	7.069
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_test/rd_data_d_15_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.400	0.257	tNET	FF	u_test/rd_data_d_15_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.469	0.183	tNET	RR	u_test/rd_data_d_15_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
690	clk_x1	0.635	0.257
110	init_calib_d	0.635	4.745
90	curr_state.WRITE_BURST	4.515	2.794
69	rd_data_valid_d	3.659	3.447
63	next_state.IDLE_19	0.635	4.928
57	wr_data_31_11	5.498	2.821
42	n1615_8	4.145	2.483
39	curr_state.CYC_DONE	5.439	1.678
36	n2175_8	4.145	1.860
36	config_done_Z	8.084	2.441

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R16C20	63.89%
R15C19	54.17%
R13C29	52.78%
R16C19	52.78%
R17C22	52.78%
R12C29	51.39%
R28C33	48.61%
R13C19	47.22%
R16C32	45.83%
R12C28	45.83%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk_x2p -period 7.143 -waveform {0 3.571} [get_nets {psram_memory_interface_top/u_apsram_top/clk_x2p}]
TC_CLOCK	Actived	create_clock -name clk -period 41.667 -waveform {0 20.834} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name clk_x1 -period 14.286 -waveform {0 7.143} [get_nets {clk_x1}]
TC_CLOCK	Actived	create_clock -name clk_x2 -period 7.143 -waveform {0 3.571} [get_nets {psram_memory_interface_top/u_apsram_top/clk_x2}]
TC_CLOCK	Actived	create_clock -name clk_d -period 28.571 -waveform {0 14.286} [get_nets {clk_d}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_x2p}] -to [get_clocks {clk clk_x1 clk_x2 clk_d}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {clk_x1 clk_x2 clk_d}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_x1}] -to [get_clocks {clk_x2 clk_d}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_x2}] -to [get_clocks {clk_d}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_d}] -to [get_clocks {clk_x2}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_d}] -to [get_clocks {clk_x2p}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_d}] -to [get_clocks {clk}]