| Report Title |
Gowin Power Analysis Report |
| Design File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\src\a.cst |
| Timing Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\src\a.sdc |
| GOWIN Version |
V1.9.7.02Beta |
| Part Number |
GW1NR-LV9QN88PC6/I5 |
| Device |
GW1NR-9C |
| Created Time |
Wed Mar 10 15:19:16 2021
|
| Legal Announcement |
Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
40.607 |
| Quiescent Power (mW) |
3.309 |
| Dynamic Power (mW) |
37.298 |
| Psram Power (mW) |
86.000 |
| Junction Temperature |
25.425 |
| Theta JA |
10.500 |
| Max Allowed Ambient Temperature |
84.575 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.200 |
30.311 |
2.311 |
39.147 |
| VCCX |
2.500 |
0.216 |
0.125 |
0.853 |
| VCCO12 |
1.200 |
0.002 |
0.003 |
0.006 |
| VCCO18 |
1.800 |
0.213 |
0.122 |
0.602 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
3.962 |
NA |
8.329 |
| IO |
1.900
| 0.686
| 15.404
|
| BSRAM |
3.058
| NA |
NA |
| PLL |
3.720
| NA |
NA |
| DLL |
8.601
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
Routing Dynamic Power(mW) |
| syn_top |
36.059 |
19.341(19.341) |
16.718(16.680) |
| syn_top/button/ |
0.197 |
0.107(0.000) |
0.090(0.000) |
| syn_top/psram_memory_interface_top/ |
22.894 |
13.556(13.556) |
9.338(9.338) |
| syn_top/psram_memory_interface_top/u_apsram_top/ |
22.894 |
13.556(4.679) |
9.338(8.203) |
| syn_top/psram_memory_interface_top/u_apsram_top/u_psram_init/ |
4.647 |
0.876(0.000) |
3.771(0.000) |
| syn_top/psram_memory_interface_top/u_apsram_top/u_psram_sync/ |
0.485 |
0.078(0.000) |
0.407(0.000) |
| syn_top/psram_memory_interface_top/u_apsram_top/u_psram_wd/ |
7.749 |
3.725(3.725) |
4.024(4.024) |
| syn_top/psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
7.749 |
3.725(3.203) |
4.024(0.740) |
| syn_top/psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/ |
3.943 |
3.203(0.000) |
0.740(0.000) |
| syn_top/u_test/ |
8.997 |
1.958(0.000) |
7.039(0.000) |
| syn_top/your_instance_name/ |
3.934 |
3.720(0.000) |
0.213(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| clk |
24.000 |
3.960 |
| clk_x1 |
69.999 |
22.780 |
| clk_d |
35.001 |
0.516 |
| NO CLOCK DOMAIN |
0.000 |
0.000 |
| psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT.default_gen_clk |
69.999 |
0.035 |
| your_instance_name/rpll_inst/CLKOUT.default_gen_clk |
159.999 |
0.096 |
| your_instance_name/rpll_inst/CLKOUTP.default_gen_clk |
159.999 |
0.096 |
| clk_x2 |
0.000 |
8.601 |