Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\UHS_PSRAM_1\data\PSRAM_32_TOP.v
C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\UHS_PSRAM_1\data\apsram_32_code.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW1NR-LV9MG100PAC7/I6
Device GW1NR-9C
Created Time Tue Mar 09 17:15:20 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module UHS_PSRAM_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 48.207MB
Running netlist conversion:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 48.207MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.137s, Peak memory usage = 48.207MB
    Optimizing Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.158s, Peak memory usage = 48.207MB
    Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.204s, Peak memory usage = 48.207MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 48.207MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 48.207MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 48.207MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 48.207MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.218s, Peak memory usage = 48.207MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 48.207MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 48.207MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 62.746MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.298s, Peak memory usage = 62.746MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 62.746MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 62.746MB

Resource

Resource Usage Summary

I/O Port 315
Emedded Port 52
I/O Buf 362
    IBUF 182
    OBUF 136
    TBUF 4
    IOBUF 36
    ELVDS_OBUF 4
Register 1005
    DFF 1
    DFFP 7
    DFFPE 12
    DFFC 592
    DFFCE 393
LUT 1793
    LUT2 609
    LUT3 554
    LUT4 630
ALU 64
    ALU 64
SSRAM 36
    RAM16S4 36
INV 29
    INV 29
IOLOGIC 120
    IDES4 32
    OSER4 48
    IODELAY 40
CLOCK 3
    DLL 1
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Logic 2102(1822 LUTs, 64 ALUs, 36 SSRAMs) / 8640 24%
Register 1005 / 6900 15%
  --Register as Latch 0 / 6900 0%
  --Register as FF 1005 / 6900 15%
BSRAM 0 / 26 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
u_apsram_top/clkdiv/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 memory_clk_ibuf/I memory_clk u_apsram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 176.3(MHz) 5 TOP
2 u_apsram_top/clkdiv/CLKOUT.default_gen_clk 50.0(MHz) 287.3(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.175
Data Arrival Time 1.692
Data Required Time 5.867
From u_apsram_top/u_psram_sync/cs_memsync_4_s0
To u_apsram_top/u_dqce_clk_x2
Launch Clk clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
0.997 0.269 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_4_s0/CLK
1.336 0.340 tC2Q RF 8 u_apsram_top/u_psram_sync/cs_memsync_4_s0/Q
1.692 0.356 tNET FF 1 u_apsram_top/u_dqce_clk_x2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.729 0.729 tINS FF 1 memory_clk_ibuf/O
6.085 0.356 tNET FF 3 u_apsram_top/u_dqce_clk_x2/CLKIN
6.055 -0.030 tUnc u_apsram_top/u_dqce_clk_x2
5.867 -0.188 tSu 1 u_apsram_top/u_dqce_clk_x2
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845%
Required Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%

Path 2

Path Summary:
Slack 4.328
Data Arrival Time 6.372
Data Required Time 10.700
From u_apsram_top/u_psram_sync/lock_cnt_1_s3
To u_apsram_top/u_psram_sync/lock_cnt_13_s3
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
0.997 0.269 tNET RR 1 u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK
1.336 0.340 tC2Q RF 5 u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q
1.692 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n47_s2/I1
2.506 0.814 tINS FF 6 u_apsram_top/u_psram_sync/n47_s2/F
2.862 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n42_s2/I1
3.676 0.814 tINS FF 3 u_apsram_top/u_psram_sync/n42_s2/F
4.032 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n38_s2/I1
4.846 0.814 tINS FF 3 u_apsram_top/u_psram_sync/n38_s2/F
5.202 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n38_s5/I1
6.016 0.814 tINS FF 1 u_apsram_top/u_psram_sync/n38_s5/F
6.372 0.356 tNET FF 1 u_apsram_top/u_psram_sync/lock_cnt_13_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.728 0.728 tINS RR 31 clk_ibuf/O
10.997 0.269 tNET RR 1 u_apsram_top/u_psram_sync/lock_cnt_13_s3/CLK
10.700 -0.296 tSu 1 u_apsram_top/u_psram_sync/lock_cnt_13_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.257, 60.598%; route: 1.778, 33.084%; tC2Q: 0.340, 6.318%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 3

Path Summary:
Slack 4.328
Data Arrival Time 6.372
Data Required Time 10.700
From u_apsram_top/u_psram_sync/lock_cnt_1_s3
To u_apsram_top/u_psram_sync/lock_cnt_14_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
0.997 0.269 tNET RR 1 u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK
1.336 0.340 tC2Q RF 5 u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q
1.692 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n47_s2/I1
2.506 0.814 tINS FF 6 u_apsram_top/u_psram_sync/n47_s2/F
2.862 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n42_s2/I1
3.676 0.814 tINS FF 3 u_apsram_top/u_psram_sync/n42_s2/F
4.032 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n38_s2/I1
4.846 0.814 tINS FF 3 u_apsram_top/u_psram_sync/n38_s2/F
5.202 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n37_s1/I1
6.016 0.814 tINS FF 1 u_apsram_top/u_psram_sync/n37_s1/F
6.372 0.356 tNET FF 1 u_apsram_top/u_psram_sync/lock_cnt_14_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.728 0.728 tINS RR 31 clk_ibuf/O
10.997 0.269 tNET RR 1 u_apsram_top/u_psram_sync/lock_cnt_14_s1/CLK
10.700 -0.296 tSu 1 u_apsram_top/u_psram_sync/lock_cnt_14_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.257, 60.598%; route: 1.778, 33.084%; tC2Q: 0.340, 6.318%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 4

Path Summary:
Slack 4.378
Data Arrival Time 6.322
Data Required Time 10.700
From u_apsram_top/u_psram_sync/cs_memsync_4_s0
To u_apsram_top/u_psram_sync/flag_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
0.997 0.269 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_4_s0/CLK
1.336 0.340 tC2Q RF 8 u_apsram_top/u_psram_sync/cs_memsync_4_s0/Q
1.692 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n359_s10/I1
2.506 0.814 tINS FF 1 u_apsram_top/u_psram_sync/n359_s10/F
2.862 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n359_s8/I1
3.676 0.814 tINS FF 2 u_apsram_top/u_psram_sync/n359_s8/F
4.032 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n348_s6/I1
4.846 0.814 tINS FF 1 u_apsram_top/u_psram_sync/n348_s6/F
5.202 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n348_s5/I0
5.967 0.765 tINS FF 1 u_apsram_top/u_psram_sync/n348_s5/F
6.322 0.356 tNET FF 1 u_apsram_top/u_psram_sync/flag_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.728 0.728 tINS RR 31 clk_ibuf/O
10.997 0.269 tNET RR 1 u_apsram_top/u_psram_sync/flag_1_s0/CLK
10.700 -0.296 tSu 1 u_apsram_top/u_psram_sync/flag_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.208, 60.231%; route: 1.778, 33.392%; tC2Q: 0.340, 6.377%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 5

Path Summary:
Slack 4.679
Data Arrival Time 6.022
Data Required Time 10.700
From u_apsram_top/u_psram_sync/lock_cnt_1_s3
To u_apsram_top/u_psram_sync/lock_cnt_15_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
0.997 0.269 tNET RR 1 u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK
1.336 0.340 tC2Q RF 5 u_apsram_top/u_psram_sync/lock_cnt_1_s3/Q
1.692 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n47_s2/I1
2.506 0.814 tINS FF 6 u_apsram_top/u_psram_sync/n47_s2/F
2.862 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n42_s2/I1
3.676 0.814 tINS FF 3 u_apsram_top/u_psram_sync/n42_s2/F
4.032 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n38_s2/I1
4.846 0.814 tINS FF 3 u_apsram_top/u_psram_sync/n38_s2/F
5.202 0.356 tNET FF 1 u_apsram_top/u_psram_sync/n36_s1/I3
5.666 0.464 tINS FF 1 u_apsram_top/u_psram_sync/n36_s1/F
6.022 0.356 tNET FF 1 u_apsram_top/u_psram_sync/lock_cnt_15_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.728 0.728 tINS RR 31 clk_ibuf/O
10.997 0.269 tNET RR 1 u_apsram_top/u_psram_sync/lock_cnt_15_s1/CLK
10.700 -0.296 tSu 1 u_apsram_top/u_psram_sync/lock_cnt_15_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 2.907, 57.850%; route: 1.778, 35.391%; tC2Q: 0.340, 6.759%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%