@W: MT453 |clock period is too long for clock apsram_init|read_calibration[0]_VALUE_derived_clock[0], changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns. 
@W: MT453 |clock period is too long for clock apsram_init|read_calibration[1]_VALUE_derived_clock[1], changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns. 
@W: MT246 :"d:\gowin_refdesign\apsram32m_refdesign\project\fpga_project\src\apsram_core.v":2100:8:2100:13|Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"d:\gowin_refdesign\apsram32m_refdesign\project\fpga_project\src\apsram_core.v":2094:6:2094:19|Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock apsram_top|clk_out_inferred_clock with period 4.74ns. Please declare a user-defined clock on net u_apsram_top.clk_outz.
@W: MT420 |Found inferred clock psram_memory_interface_top|clk_d with period 3.77ns. Please declare a user-defined clock on port clk_d.
@W: MT420 |Found inferred clock apsram_top|clk_x2_inferred_clock with period 6.67ns. Please declare a user-defined clock on net u_apsram_top.clk_x2.
@W: MT420 |Found inferred clock apsram_top|clk_x2p_inferred_clock with period 6.67ns. Please declare a user-defined clock on net u_apsram_top.clk_x2p.
