| Report Title |
Gowin Power Analysis Report |
| Design File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_1ch_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_1ch_Refdesign\project\fpga_project\src\a.cst |
| Timing Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_1ch_Refdesign\project\fpga_project\src\fpga_project.sdc |
| GOWIN Version |
V1.9.7.02Beta |
| Part Number |
GW1NR-LV9MG100PAC7/I6 |
| Device |
GW1NR-9C |
| Created Time |
Tue Mar 09 17:16:04 2021
|
| Legal Announcement |
Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
67.989 |
| Quiescent Power (mW) |
4.907 |
| Dynamic Power (mW) |
63.082 |
| Psram Power (mW) |
172.000 |
| Junction Temperature |
25.709 |
| Theta JA |
10.500 |
| Max Allowed Ambient Temperature |
84.291 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.200 |
49.422 |
2.606 |
62.434 |
| VCCX |
2.500 |
0.880 |
0.415 |
3.238 |
| VCCO18 |
1.800 |
0.876 |
0.411 |
2.317 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
7.773 |
NA |
8.655 |
| IO |
7.222
| 2.278
| 17.571
|
| PLL |
3.720
| NA |
NA |
| DLL |
8.601
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
Routing Dynamic Power(mW) |
| syn_top |
58.153 |
20.095(20.095) |
38.059(38.029) |
| syn_top/u_psram_memory_interface_top/ |
41.545 |
13.781(13.781) |
27.765(27.765) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/ |
41.545 |
13.781(4.422) |
27.765(24.303) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_init/ |
11.897 |
2.243(0.000) |
9.654(0.000) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_sync/ |
0.608 |
0.091(0.000) |
0.517(0.000) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_wd/ |
16.220 |
2.088(1.888) |
14.132(13.706) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
6.490 |
0.709(0.000) |
5.781(0.000) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/ |
3.068 |
0.403(0.000) |
2.664(0.000) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/ |
2.939 |
0.387(0.000) |
2.553(0.000) |
| syn_top/u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/ |
3.097 |
0.389(0.000) |
2.708(0.000) |
| syn_top/u_test/ |
12.737 |
2.594(0.000) |
10.144(0.000) |
| syn_top/your_instance_name/ |
3.841 |
3.720(0.000) |
0.120(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| clk_x1 |
69.999 |
44.744 |
| your_instance_name/rpll_inst/CLKOUTD.default_gen_clk |
40.000 |
0.645 |
| NO CLOCK DOMAIN |
0.000 |
0.000 |
| clk_x2 |
139.997 |
8.903 |
| clk |
50.000 |
3.751 |
| your_instance_name/rpll_inst/CLKOUT.default_gen_clk |
160.000 |
0.096 |