Project Settings Project Name fpga_project Device Name rev_1: GOWIN-GW2A : GW2A_18 Implementation Name rev_1 Top Module [auto] Pipelining 1 Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 Clock Conversion 1 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 10 1 0 - 00m:03s - 2021/1/19 16:45:56 (premap) Complete 6 2 0 0m:02s 0m:02s 239MB 2021/1/19 16:46:00 (fpga_mapper) Complete 11 8 0 0m:06s 0m:06s 259MB 2021/1/19 16:46:08 Multi-srs Generator Complete 2021/1/19 16:45:57 Area Summary I/O ports (io_port) 126 Non I/O Register bits (non_io_reg) 422 (2%) I/O Register bits (total_io_reg) 0 Ultra Rams 0 Block Rams (v_ram) 1 (46) Block Multipliers (dsp_used) 0 (24) LUTs (total_luts) 636 (3%) Timing Summary Clock Name Req Freq Est Freq Slack _~apsram_init_psram_memory_interface_top_|read_calibration[0]_VALUE_derived_clock[0] 0.1 MHz NA NA _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock 211.1 MHz 179.4 MHz -0.836 _~apsram_top_psram_memory_interface_top_|clk_x2_inferred_clock 150.0 MHz NA NA _~apsram_wd_psram_memory_interface_top_|step_derived_clock[0] 0.1 MHz NA NA psram_memory_interface_top|clk 265.5 MHz 225.7 MHz -0.665 System 1627.9 MHz 1383.7 MHz -0.108 Optimizations Summary Combined Clock Conversion 3 / 2