#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020 #install: D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro #OS: Windows 8 6.2 #Hostname: JN-IP-SHANGYAN # Tue Jan 19 16:45:53 2021 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\PSRAM_TOP.v" (library work) @I:"D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\PSRAM_TOP.v":"D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\apsram_define.v" (library work) @I:"D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\PSRAM_TOP.v":"D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\apsram_local_define.v" (library work) @I:"D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\PSRAM_TOP.v":"D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\apsram_param.v" (library work) @I:"D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\PSRAM_TOP.v":"D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\apsram_local_param.v" (library work) @I::"D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\apsram_core.v" (library work) @N:CG346 : apsram_core.v(160) | Read full_case directive. @N:CG347 : apsram_core.v(160) | Read a parallel_case directive. @W:CG286 : apsram_core.v(160) | Case statement has both a full_case directive and a default clause -- ignoring full_case directive. Verilog syntax check successful! File D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\src\apsram_core_ming.v changed - recompiling Selecting top level module psram_memory_interface_top Running optimization stage 1 on \~fifo_sc.psram_memory_interface_top ....... Running optimization stage 1 on OSER4 ....... Running optimization stage 1 on IDES4 ....... Running optimization stage 1 on \~apsram_lane.psram_memory_interface_top ....... Running optimization stage 1 on IODELAY ....... Running optimization stage 1 on IOBUF ....... Running optimization stage 1 on OBUF ....... Running optimization stage 1 on \~apsram_wd.psram_memory_interface_top ....... Running optimization stage 1 on \~apsram_init.psram_memory_interface_top ....... Running optimization stage 1 on \~apsram_sync.psram_memory_interface_top ....... Running optimization stage 1 on DLL ....... Running optimization stage 1 on DHCEN ....... Running optimization stage 1 on CLKDIV ....... Running optimization stage 1 on \~apsram_top.psram_memory_interface_top ....... @N:CG364 : PSRAM_TOP.v(5) | Synthesizing module psram_memory_interface_top in library work. Running optimization stage 1 on psram_memory_interface_top ....... Running optimization stage 2 on psram_memory_interface_top ....... Running optimization stage 2 on \~apsram_top.psram_memory_interface_top ....... Running optimization stage 2 on CLKDIV ....... Running optimization stage 2 on DHCEN ....... Running optimization stage 2 on DLL ....... Running optimization stage 2 on \~apsram_sync.psram_memory_interface_top ....... Extracted state machine for register flag State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on \~apsram_init.psram_memory_interface_top ....... Extracted state machine for register c_state State machine has 19 reachable states with original encodings of: 0000000000000000001 0000000000000000010 0000000000000000100 0000000000000001000 0000000000000010000 0000000000000100000 0000000000001000000 0000000000010000000 0000000000100000000 0000000001000000000 0000000010000000000 0000000100000000000 0000001000000000000 0000010000000000000 0000100000000000000 0001000000000000000 0010000000000000000 0100000000000000000 1000000000000000000 Running optimization stage 2 on OBUF ....... Running optimization stage 2 on IOBUF ....... Running optimization stage 2 on IODELAY ....... Running optimization stage 2 on \~apsram_lane.psram_memory_interface_top ....... Extracted state machine for register c_state State machine has 11 reachable states with original encodings of: 00000000001 00000000010 00000000100 00000001000 00000010000 00000100000 00001000000 00010000000 00100000000 01000000000 10000000000 Running optimization stage 2 on IDES4 ....... Running optimization stage 2 on OSER4 ....... Running optimization stage 2 on \~fifo_sc.psram_memory_interface_top ....... Running optimization stage 2 on \~apsram_wd.psram_memory_interface_top ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 109MB peak: 117MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jan 19 16:45:55 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @N:NF107 : psram_top.v(5) | Selected library: work cell: psram_memory_interface_top view verilog as top level @N:NF107 : psram_top.v(5) | Selected library: work cell: psram_memory_interface_top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jan 19 16:45:56 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: fpga_project_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 33MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime Process completed successfully. # Tue Jan 19 16:45:56 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode File D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\impl\synthesize\rev_1\synwork\fpga_project_comp.srs changed - recompiling @N:NF107 : psram_top.v(5) | Selected library: work cell: psram_memory_interface_top view verilog as top level @N:NF107 : psram_top.v(5) | Selected library: work cell: psram_memory_interface_top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jan 19 16:45:57 2021 ###########################################################] # Tue Jan 19 16:45:58 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 125MB) @A:MF827 : | No constraint file specified. Linked File: fpga_project_scck.rpt See clock summary report "D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\impl\synthesize\rev_1\fpga_project_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 136MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB) Encoding state machine c_state[10:0] (in view: work.\\\~apsram_lane\.psram_memory_interface_top\ (verilog)) original code -> new code 00000000001 -> 00000000001 00000000010 -> 00000000010 00000000100 -> 00000000100 00000001000 -> 00000001000 00000010000 -> 00000010000 00000100000 -> 00000100000 00001000000 -> 00001000000 00010000000 -> 00010000000 00100000000 -> 00100000000 01000000000 -> 01000000000 10000000000 -> 10000000000 Encoding state machine c_state[18:0] (in view: work.\\\~apsram_init\.psram_memory_interface_top\ (verilog)) original code -> new code 0000000000000000001 -> 0000000000000000001 0000000000000000010 -> 0000000000000000010 0000000000000000100 -> 0000000000000000100 0000000000000001000 -> 0000000000000001000 0000000000000010000 -> 0000000000000010000 0000000000000100000 -> 0000000000000100000 0000000000001000000 -> 0000000000001000000 0000000000010000000 -> 0000000000010000000 0000000000100000000 -> 0000000000100000000 0000000001000000000 -> 0000000001000000000 0000000010000000000 -> 0000000010000000000 0000000100000000000 -> 0000000100000000000 0000001000000000000 -> 0000001000000000000 0000010000000000000 -> 0000010000000000000 0000100000000000000 -> 0000100000000000000 0001000000000000000 -> 0001000000000000000 0010000000000000000 -> 0010000000000000000 0100000000000000000 -> 0100000000000000000 1000000000000000000 -> 1000000000000000000 Encoding state machine flag[2:0] (in view: work.\\\~apsram_sync\.psram_memory_interface_top\ (verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 236MB peak: 236MB) @N:MF578 : | Incompatible asynchronous control logic preventing generated clock conversion. Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 236MB peak: 236MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 236MB peak: 236MB) @W:BN117 : psram_top.v(57) | Instance u_apsram_top of partition view:work.\\\~apsram_top\.psram_memory_interface_top\ (verilog) has no references to its outputs; instance not removed. @W:BN117 : psram_top.v(57) | Instance u_apsram_top of partition view:work.\\\~apsram_top\.psram_memory_interface_top\ (verilog) has no references to its outputs; instance not removed. Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 236MB peak: 237MB) Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 237MB peak: 237MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - System 150.0 MHz 6.667 system system_clkgroup 0 0 - _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock 184.0 MHz 5.434 inferred Autoconstr_clkgroup_0 516 1 . _~apsram_init_psram_memory_interface_top_|read_calibration[0]_VALUE_derived_clock[0] 184.0 MHz 5.434 derived (from _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock) Autoconstr_clkgroup_0 8 1 . _~apsram_wd_psram_memory_interface_top_|step_derived_clock[0] 184.0 MHz 5.434 derived (from _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock) Autoconstr_clkgroup_0 1 0 - psram_memory_interface_top|clk 275.0 MHz 3.636 inferred Autoconstr_clkgroup_1 31 0 - _~apsram_top_psram_memory_interface_top_|clk_x2_inferred_clock 150.0 MHz 6.667 inferred Autoconstr_clkgroup_2 19 =================================================================================================================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System 0 - - - - _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock 516 u_apsram_top.clkdiv.CLKOUT(CLKDIV) u_apsram_top.rd_data_valid_d.C u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[6\]\.u_ides4.PCLK - _~apsram_init_psram_memory_interface_top_|read_calibration[0]_VALUE_derived_clock[0] 8 u_apsram_top.u_psram_init.read_calibration\[0\]\.VALUE[0].Q[0](dffre) u_apsram_top.u_psram_wd.dq_iodelay_gen0\[0\]\.genblk1\[4\]\.iodelay.VALUE - - _~apsram_wd_psram_memory_interface_top_|step_derived_clock[0] 1 u_apsram_top.u_psram_wd.step[8:0].Q[0](dffr) u_apsram_top.u_psram_wd.ck_delay\[0\]\.iodelay.VALUE - - psram_memory_interface_top|clk 31 clk(port) u_apsram_top.u_psram_sync.dll_rst.C - - _~apsram_top_psram_memory_interface_top_|clk_x2_inferred_clock 19 u_apsram_top.u_dqce_clk_x2.CLKOUT(DHCEN) u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.mask_oser4.FCLK - - ==================================================================================================================================================================================================================================================================================================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 3 non-gated/non-generated clock tree(s) driving 523 clock pin(s) of sequential element(s) 2 gated/generated clock tree(s) driving 9 clock pin(s) of sequential element(s) 0 instances converted, 9 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 clk port 31 ENCRYPTED ClockId_0_1 ENCRYPTED CLKDIV 473 ENCRYPTED ClockId_0_2 ENCRYPTED DHCEN 19 ENCRYPTED ======================================================================================= ============================================================= Gated/Generated Clocks ============================================================= Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation -------------------------------------------------------------------------------------------------------------------------------------------------- ClockId_0_3 ENCRYPTED dffre 8 ENCRYPTED Derived clock on input (not legal for GCC) ClockId_0_5 ENCRYPTED dffr 1 ENCRYPTED Derived clock on input (not legal for GCC) ================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\impl\synthesize\rev_1\fpga_project.sap. Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 237MB peak: 237MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 238MB peak: 238MB) Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 239MB peak: 239MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 239MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Tue Jan 19 16:46:00 2021 ###########################################################] # Tue Jan 19 16:46:01 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\Gowin_V1.9.7.01Beta_46384_20201120\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 125MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 137MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 137MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 137MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 229MB peak: 229MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 233MB peak: 233MB) Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 237MB peak: 237MB) Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 240MB peak: 240MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 241MB peak: 241MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB) Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 243MB) Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 255MB peak: 255MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:03s -2.72ns 693 / 419 2 0h:00m:03s -2.72ns 691 / 419 3 0h:00m:03s -2.68ns 691 / 419 4 0h:00m:03s -2.68ns 691 / 419 Timing driven replication report Added 3 Registers via timing driven replication Added 0 LUTs via timing driven replication 5 0h:00m:03s -1.60ns 711 / 422 6 0h:00m:03s -1.90ns 711 / 422 7 0h:00m:03s -1.60ns 711 / 422 8 0h:00m:03s -1.82ns 711 / 422 9 0h:00m:03s -1.68ns 711 / 422 10 0h:00m:03s -1.53ns 707 / 422 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 257MB peak: 257MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @W:MT453 : | clock period is too long for clock _~apsram_wd_psram_memory_interface_top_|step_derived_clock[0], changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns. @W:MT453 : | clock period is too long for clock _~apsram_init_psram_memory_interface_top_|read_calibration[0]_VALUE_derived_clock[0], changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns. Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 258MB peak: 258MB) Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 181MB peak: 258MB) Writing Analyst data base D:\GOWIN_refdesign\apsram256M_ref\project\fpga_project\impl\synthesize\rev_1\synwork\fpga_project_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 258MB peak: 258MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 259MB peak: 259MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 259MB peak: 259MB) Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 255MB peak: 259MB) @W:MT246 : apsram_core.v(583) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : apsram_core.v(571) | Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : apsram_core.v(559) | Blackbox DLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock with period 4.74ns. Please declare a user-defined clock on net u_apsram_top.clk_outz. @W:MT420 : | Found inferred clock psram_memory_interface_top|clk with period 3.77ns. Please declare a user-defined clock on port clk. @W:MT420 : | Found inferred clock _~apsram_top_psram_memory_interface_top_|clk_x2_inferred_clock with period 6.67ns. Please declare a user-defined clock on net u_apsram_top.clk_x2. @N:MT615 : | Found clock _~apsram_wd_psram_memory_interface_top_|step_derived_clock[0] with period 20000.00ns @N:MT615 : | Found clock _~apsram_init_psram_memory_interface_top_|read_calibration[0]_VALUE_derived_clock[0] with period 20000.00ns ##### START OF TIMING REPORT #####[ # Timing report written on Tue Jan 19 16:46:07 2021 # Top view: psram_memory_interface_top Requested Frequency: 0.1 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.836 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- _~apsram_init_psram_memory_interface_top_|read_calibration[0]_VALUE_derived_clock[0] 0.1 MHz NA 20000.000 NA NA derived (from _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock) Autoconstr_clkgroup_0 _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock 211.1 MHz 179.4 MHz 4.737 5.573 -0.836 inferred Autoconstr_clkgroup_0 _~apsram_top_psram_memory_interface_top_|clk_x2_inferred_clock 150.0 MHz NA 6.667 NA NA inferred Autoconstr_clkgroup_2 _~apsram_wd_psram_memory_interface_top_|step_derived_clock[0] 0.1 MHz NA 20000.000 NA NA derived (from _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock) Autoconstr_clkgroup_0 psram_memory_interface_top|clk 265.5 MHz 225.7 MHz 3.766 4.431 -0.665 inferred Autoconstr_clkgroup_1 System 1627.9 MHz 1383.7 MHz 0.614 0.723 -0.108 system system_clkgroup ====================================================================================================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 0.614 -0.108 | No paths - | No paths - | No paths - System _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock | 4.737 1.141 | No paths - | No paths - | No paths - System psram_memory_interface_top|clk | 3.766 2.507 | No paths - | No paths - | No paths - _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock | 4.737 -0.836 | No paths - | No paths - | No paths - _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock _~apsram_top_psram_memory_interface_top_|clk_x2_inferred_clock | Diff grp - | No paths - | No paths - | No paths - psram_memory_interface_top|clk System | 3.766 1.695 | No paths - | No paths - | No paths - psram_memory_interface_top|clk _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock | Diff grp - | No paths - | No paths - | No paths - psram_memory_interface_top|clk psram_memory_interface_top|clk | 3.766 -0.665 | No paths - | No paths - | No paths - ========================================================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[0] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE Q burst_cnt[0] 0.267 -0.836 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[1] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE Q burst_cnt[1] 0.267 -0.797 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[2] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE Q burst_cnt[2] 0.267 -0.759 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[3] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE Q burst_cnt[3] 0.267 -0.720 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[4] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE Q burst_cnt[4] 0.267 -0.682 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[5] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE Q burst_cnt[5] 0.267 -0.563 u_apsram_top.u_psram_init.read_calibration\[0\]\.check_cnt[1] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE Q check_cnt[1] 0.267 -0.490 u_apsram_top.u_psram_init.read_calibration\[0\]\.check_cnt[0] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE Q check_cnt[0] 0.267 -0.467 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[6] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE Q burst_cnt[6] 0.267 -0.463 u_apsram_top.u_psram_init.read_calibration\[0\]\.check_cnt[4] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE Q check_cnt[4] 0.267 -0.371 =================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdw_done _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE CE g0_0 4.670 -0.836 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdr_done _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE CE g0 4.670 -0.756 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdr_done _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE D cmdr_done6 4.670 -0.630 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdw_done _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE D cmdw_done5 4.670 -0.630 u_apsram_top.u_psram_init.read_calibration\[0\]\.id_reg[0] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE D id_reg_4[0] 4.670 -0.490 u_apsram_top.u_psram_init.read_calibration\[0\]\.id_reg[1] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE D id_reg_4[1] 4.670 -0.490 u_apsram_top.u_psram_init.read_calibration\[0\]\.id_reg[2] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE D id_reg_4[2] 4.670 -0.490 u_apsram_top.u_psram_init.read_calibration\[0\]\.id_reg[3] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE D id_reg_4[3] 4.670 -0.490 u_apsram_top.u_psram_init.read_calibration\[0\]\.id_reg[4] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE D id_reg_4[4] 4.670 -0.490 u_apsram_top.u_psram_init.read_calibration\[0\]\.id_reg[5] _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock DFFCE D id_reg_4[5] 4.670 -0.490 ================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.737 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.670 - Propagation time: 5.506 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.836 Number of logic level(s): 9 Starting point: u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[0] / Q Ending point: u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdw_done / CE The start point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK The end point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[0] DFFCE Q Out 0.267 0.267 r - burst_cnt[0] Net - - 0.589 - 2 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_0_0 ALU I1 In - 0.856 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_0_0 ALU COUT Out 0.627 1.483 r - un1_burst_cnt_1_a_4_cry_0 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_1_0 ALU CIN In - 1.483 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_1_0 ALU COUT Out 0.038 1.521 r - un1_burst_cnt_1_a_4_cry_1 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_2_0 ALU CIN In - 1.521 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_2_0 ALU COUT Out 0.038 1.560 r - un1_burst_cnt_1_a_4_cry_2 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_3_0 ALU CIN In - 1.560 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_3_0 ALU COUT Out 0.038 1.598 r - un1_burst_cnt_1_a_4_cry_3 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_4_0 ALU CIN In - 1.598 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_4_0 ALU COUT Out 0.038 1.637 r - un1_burst_cnt_1_a_4_cry_4 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_5_0 ALU CIN In - 1.637 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_5_0 ALU SUM Out 0.517 2.154 f - un1_burst_cnt_1_a_4[5] Net - - 0.589 - 3 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5_RNO LUT2 I1 In - 2.742 f - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5_RNO LUT2 F Out 0.627 3.369 r - g0_0_5_RNO Net - - 0.441 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5 LUT4 I1 In - 3.811 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5 LUT4 F Out 0.627 4.438 r - g0_0_1_1 Net - - 0.441 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0 LUT4 I1 In - 4.879 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0 LUT4 F Out 0.627 5.506 r - g0_0 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdw_done DFFCE CE In - 5.506 r - ==================================================================================================================================================== Total path delay (propagation time + setup) of 5.573 is 3.513(63.0%) logic and 2.060(37.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.737 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.670 - Propagation time: 5.467 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.797 Number of logic level(s): 8 Starting point: u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[1] / Q Ending point: u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdw_done / CE The start point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK The end point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[1] DFFCE Q Out 0.267 0.267 r - burst_cnt[1] Net - - 0.589 - 2 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_1_0 ALU I1 In - 0.856 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_1_0 ALU COUT Out 0.627 1.483 r - un1_burst_cnt_1_a_4_cry_1 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_2_0 ALU CIN In - 1.483 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_2_0 ALU COUT Out 0.038 1.521 r - un1_burst_cnt_1_a_4_cry_2 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_3_0 ALU CIN In - 1.521 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_3_0 ALU COUT Out 0.038 1.560 r - un1_burst_cnt_1_a_4_cry_3 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_4_0 ALU CIN In - 1.560 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_4_0 ALU COUT Out 0.038 1.598 r - un1_burst_cnt_1_a_4_cry_4 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_5_0 ALU CIN In - 1.598 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_5_0 ALU SUM Out 0.517 2.115 f - un1_burst_cnt_1_a_4[5] Net - - 0.589 - 3 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5_RNO LUT2 I1 In - 2.704 f - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5_RNO LUT2 F Out 0.627 3.331 r - g0_0_5_RNO Net - - 0.441 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5 LUT4 I1 In - 3.772 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5 LUT4 F Out 0.627 4.399 r - g0_0_1_1 Net - - 0.441 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0 LUT4 I1 In - 4.840 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0 LUT4 F Out 0.627 5.467 r - g0_0 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdw_done DFFCE CE In - 5.467 r - ==================================================================================================================================================== Total path delay (propagation time + setup) of 5.534 is 3.475(62.8%) logic and 2.060(37.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.737 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.670 - Propagation time: 5.429 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.759 Number of logic level(s): 7 Starting point: u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[2] / Q Ending point: u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdw_done / CE The start point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK The end point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[2] DFFCE Q Out 0.267 0.267 r - burst_cnt[2] Net - - 0.589 - 2 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_2_0 ALU I1 In - 0.856 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_2_0 ALU COUT Out 0.627 1.483 r - un1_burst_cnt_1_a_4_cry_2 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_3_0 ALU CIN In - 1.483 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_3_0 ALU COUT Out 0.038 1.521 r - un1_burst_cnt_1_a_4_cry_3 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_4_0 ALU CIN In - 1.521 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_4_0 ALU COUT Out 0.038 1.560 r - un1_burst_cnt_1_a_4_cry_4 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_5_0 ALU CIN In - 1.560 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_5_0 ALU SUM Out 0.517 2.077 f - un1_burst_cnt_1_a_4[5] Net - - 0.589 - 3 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5_RNO LUT2 I1 In - 2.665 f - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5_RNO LUT2 F Out 0.627 3.292 r - g0_0_5_RNO Net - - 0.441 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5 LUT4 I1 In - 3.734 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5 LUT4 F Out 0.627 4.361 r - g0_0_1_1 Net - - 0.441 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0 LUT4 I1 In - 4.802 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0 LUT4 F Out 0.627 5.429 r - g0_0 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdw_done DFFCE CE In - 5.429 r - ==================================================================================================================================================== Total path delay (propagation time + setup) of 5.496 is 3.436(62.5%) logic and 2.060(37.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.737 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.670 - Propagation time: 5.426 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.756 Number of logic level(s): 10 Starting point: u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[0] / Q Ending point: u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdr_done / CE The start point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK The end point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[0] DFFCE Q Out 0.267 0.267 r - burst_cnt[0] Net - - 0.589 - 2 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_0_0 ALU I1 In - 0.856 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_0_0 ALU COUT Out 0.627 1.483 r - un1_burst_cnt_1_a_4_cry_0 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_1_0 ALU CIN In - 1.483 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_1_0 ALU COUT Out 0.038 1.521 r - un1_burst_cnt_1_a_4_cry_1 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_2_0 ALU CIN In - 1.521 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_2_0 ALU COUT Out 0.038 1.560 r - un1_burst_cnt_1_a_4_cry_2 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_3_0 ALU CIN In - 1.560 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_3_0 ALU COUT Out 0.038 1.598 r - un1_burst_cnt_1_a_4_cry_3 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_4_0 ALU CIN In - 1.598 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_4_0 ALU COUT Out 0.038 1.637 r - un1_burst_cnt_1_a_4_cry_4 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_5_0 ALU CIN In - 1.637 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_5_0 ALU COUT Out 0.038 1.675 r - un1_burst_cnt_1_a_4_cry_5 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_6_0 ALU CIN In - 1.675 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_6_0 ALU SUM Out 0.517 2.192 f - un1_burst_cnt_1_a_4[6] Net - - 0.589 - 4 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_7_N_3L3 LUT4 I2 In - 2.781 f - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_7_N_3L3 LUT4 F Out 0.508 3.289 r - g0_0_5_1 Net - - 0.441 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_7 LUT4 I1 In - 3.730 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_7 LUT4 F Out 0.627 4.357 r - g0_0_7 Net - - 0.441 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0 LUT4 I1 In - 4.799 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0 LUT4 F Out 0.627 5.426 r - g0 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdr_done DFFCE CE In - 5.426 r - ==================================================================================================================================================== Total path delay (propagation time + setup) of 5.493 is 3.433(62.5%) logic and 2.060(37.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.737 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.670 - Propagation time: 5.390 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.720 Number of logic level(s): 6 Starting point: u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[3] / Q Ending point: u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdw_done / CE The start point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK The end point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.burst_cnt[3] DFFCE Q Out 0.267 0.267 r - burst_cnt[3] Net - - 0.589 - 2 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_3_0 ALU I1 In - 0.856 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_3_0 ALU COUT Out 0.627 1.483 r - un1_burst_cnt_1_a_4_cry_3 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_4_0 ALU CIN In - 1.483 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_4_0 ALU COUT Out 0.038 1.521 r - un1_burst_cnt_1_a_4_cry_4 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_5_0 ALU CIN In - 1.521 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.un1_burst_cnt_1_a_4_cry_5_0 ALU SUM Out 0.517 2.038 f - un1_burst_cnt_1_a_4[5] Net - - 0.589 - 3 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5_RNO LUT2 I1 In - 2.627 f - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5_RNO LUT2 F Out 0.627 3.254 r - g0_0_5_RNO Net - - 0.441 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5 LUT4 I1 In - 3.695 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0_5 LUT4 F Out 0.627 4.322 r - g0_0_1_1 Net - - 0.441 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0 LUT4 I1 In - 4.763 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.g0_0 LUT4 F Out 0.627 5.390 r - g0_0 Net - - 0.000 - 1 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.cmdw_done DFFCE CE In - 5.390 r - ==================================================================================================================================================== Total path delay (propagation time + setup) of 5.457 is 3.398(62.3%) logic and 2.060(37.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: psram_memory_interface_top|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_sync.lock_syn[1] psram_memory_interface_top|clk DFFC Q lock_cnt 0.267 -0.665 u_apsram_top.u_psram_sync.lock_cnt[0] psram_memory_interface_top|clk DFFCE Q lock_cnt[0] 0.267 -0.621 u_apsram_top.u_psram_sync.lock_cnt[1] psram_memory_interface_top|clk DFFCE Q lock_cnt[1] 0.267 -0.582 u_apsram_top.u_psram_sync.lock_cnt[2] psram_memory_interface_top|clk DFFCE Q lock_cnt[2] 0.267 -0.544 u_apsram_top.u_psram_sync.lock_cnt[3] psram_memory_interface_top|clk DFFCE Q lock_cnt[3] 0.267 -0.505 u_apsram_top.u_psram_sync.lock_cnt[4] psram_memory_interface_top|clk DFFCE Q lock_cnt[4] 0.267 -0.467 u_apsram_top.u_psram_sync.lock_cnt[5] psram_memory_interface_top|clk DFFCE Q lock_cnt[5] 0.267 -0.428 u_apsram_top.u_psram_sync.lock_cnt[6] psram_memory_interface_top|clk DFFCE Q lock_cnt[6] 0.267 -0.390 u_apsram_top.u_psram_sync.lock_cnt[7] psram_memory_interface_top|clk DFFCE Q lock_cnt[7] 0.267 -0.351 u_apsram_top.u_psram_sync.lock_cnt[8] psram_memory_interface_top|clk DFFCE Q lock_cnt[8] 0.267 -0.313 ================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_sync.lock_cnt[15] psram_memory_interface_top|clk DFFCE D lock_cnt_s[15] 3.699 -0.665 u_apsram_top.u_psram_sync.lock_cnt[14] psram_memory_interface_top|clk DFFCE D lock_cnt_s[14] 3.699 -0.626 u_apsram_top.u_psram_sync.lock_cnt[13] psram_memory_interface_top|clk DFFCE D lock_cnt_s[13] 3.699 -0.588 u_apsram_top.u_psram_sync.lock_cnt[12] psram_memory_interface_top|clk DFFCE D lock_cnt_s[12] 3.699 -0.549 u_apsram_top.u_psram_sync.lock_cnt[11] psram_memory_interface_top|clk DFFCE D lock_cnt_s[11] 3.699 -0.511 u_apsram_top.u_psram_sync.lock_cnt[10] psram_memory_interface_top|clk DFFCE D lock_cnt_s[10] 3.699 -0.472 u_apsram_top.u_psram_sync.lock_cnt[9] psram_memory_interface_top|clk DFFCE D lock_cnt_s[9] 3.699 -0.434 u_apsram_top.u_psram_sync.lock_cnt[8] psram_memory_interface_top|clk DFFCE D lock_cnt_s[8] 3.699 -0.395 u_apsram_top.u_psram_sync.lock_cnt[7] psram_memory_interface_top|clk DFFCE D lock_cnt_s[7] 3.699 -0.357 u_apsram_top.u_psram_sync.lock_cnt[6] psram_memory_interface_top|clk DFFCE D lock_cnt_s[6] 3.699 -0.318 ====================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 3.766 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.699 - Propagation time: 4.364 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.665 Number of logic level(s): 17 Starting point: u_apsram_top.u_psram_sync.lock_syn[1] / Q Ending point: u_apsram_top.u_psram_sync.lock_cnt[15] / D The start point is clocked by psram_memory_interface_top|clk [rising] (rise=0.000 fall=1.883 period=3.766) on pin CLK The end point is clocked by psram_memory_interface_top|clk [rising] (rise=0.000 fall=1.883 period=3.766) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_sync.lock_syn[1] DFFC Q Out 0.267 0.267 r - lock_cnt Net - - 0.656 - 18 u_apsram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 I0 In - 0.923 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 F Out 0.604 1.527 r - lock_cnt_cry_0_RNO[0] Net - - 0.589 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[0] ALU I0 In - 2.115 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[0] ALU COUT Out 0.604 2.719 r - lock_cnt_cry[0] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[1] ALU CIN In - 2.719 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[1] ALU COUT Out 0.038 2.758 r - lock_cnt_cry[1] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[2] ALU CIN In - 2.758 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[2] ALU COUT Out 0.038 2.796 r - lock_cnt_cry[2] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[3] ALU CIN In - 2.796 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[3] ALU COUT Out 0.038 2.835 r - lock_cnt_cry[3] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[4] ALU CIN In - 2.835 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[4] ALU COUT Out 0.038 2.873 r - lock_cnt_cry[4] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[5] ALU CIN In - 2.873 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[5] ALU COUT Out 0.038 2.912 r - lock_cnt_cry[5] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[6] ALU CIN In - 2.912 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[6] ALU COUT Out 0.038 2.950 r - lock_cnt_cry[6] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[7] ALU CIN In - 2.950 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[7] ALU COUT Out 0.038 2.989 r - lock_cnt_cry[7] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[8] ALU CIN In - 2.989 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[8] ALU COUT Out 0.038 3.027 r - lock_cnt_cry[8] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[9] ALU CIN In - 3.027 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[9] ALU COUT Out 0.038 3.066 r - lock_cnt_cry[9] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[10] ALU CIN In - 3.066 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[10] ALU COUT Out 0.038 3.104 r - lock_cnt_cry[10] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[11] ALU CIN In - 3.104 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[11] ALU COUT Out 0.038 3.143 r - lock_cnt_cry[11] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[12] ALU CIN In - 3.143 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[12] ALU COUT Out 0.038 3.181 r - lock_cnt_cry[12] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[13] ALU CIN In - 3.181 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[13] ALU COUT Out 0.038 3.220 r - lock_cnt_cry[13] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[14] ALU CIN In - 3.220 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[14] ALU COUT Out 0.038 3.258 r - lock_cnt_cry[14] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_s_0[15] ALU CIN In - 3.258 r - u_apsram_top.u_psram_sync.lock_cnt_s_0[15] ALU SUM Out 0.517 3.775 f - lock_cnt_s[15] Net - - 0.589 - 1 u_apsram_top.u_psram_sync.lock_cnt[15] DFFCE D In - 4.364 f - =============================================================================================================== Total path delay (propagation time + setup) of 4.431 is 2.598(58.6%) logic and 1.833(41.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 3.766 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.699 - Propagation time: 4.325 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.626 Number of logic level(s): 16 Starting point: u_apsram_top.u_psram_sync.lock_syn[1] / Q Ending point: u_apsram_top.u_psram_sync.lock_cnt[15] / D The start point is clocked by psram_memory_interface_top|clk [rising] (rise=0.000 fall=1.883 period=3.766) on pin CLK The end point is clocked by psram_memory_interface_top|clk [rising] (rise=0.000 fall=1.883 period=3.766) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_sync.lock_syn[1] DFFC Q Out 0.267 0.267 r - lock_cnt Net - - 0.656 - 18 u_apsram_top.u_psram_sync.lock_cnt_cry_0_RNO[1] LUT2 I0 In - 0.923 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0_RNO[1] LUT2 F Out 0.604 1.527 r - lock_cnt_cry_0_RNO[1] Net - - 0.589 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[1] ALU I0 In - 2.115 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[1] ALU COUT Out 0.604 2.719 r - lock_cnt_cry[1] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[2] ALU CIN In - 2.719 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[2] ALU COUT Out 0.038 2.758 r - lock_cnt_cry[2] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[3] ALU CIN In - 2.758 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[3] ALU COUT Out 0.038 2.796 r - lock_cnt_cry[3] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[4] ALU CIN In - 2.796 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[4] ALU COUT Out 0.038 2.835 r - lock_cnt_cry[4] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[5] ALU CIN In - 2.835 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[5] ALU COUT Out 0.038 2.873 r - lock_cnt_cry[5] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[6] ALU CIN In - 2.873 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[6] ALU COUT Out 0.038 2.912 r - lock_cnt_cry[6] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[7] ALU CIN In - 2.912 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[7] ALU COUT Out 0.038 2.950 r - lock_cnt_cry[7] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[8] ALU CIN In - 2.950 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[8] ALU COUT Out 0.038 2.989 r - lock_cnt_cry[8] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[9] ALU CIN In - 2.989 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[9] ALU COUT Out 0.038 3.027 r - lock_cnt_cry[9] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[10] ALU CIN In - 3.027 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[10] ALU COUT Out 0.038 3.066 r - lock_cnt_cry[10] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[11] ALU CIN In - 3.066 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[11] ALU COUT Out 0.038 3.104 r - lock_cnt_cry[11] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[12] ALU CIN In - 3.104 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[12] ALU COUT Out 0.038 3.143 r - lock_cnt_cry[12] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[13] ALU CIN In - 3.143 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[13] ALU COUT Out 0.038 3.181 r - lock_cnt_cry[13] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[14] ALU CIN In - 3.181 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[14] ALU COUT Out 0.038 3.220 r - lock_cnt_cry[14] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_s_0[15] ALU CIN In - 3.220 r - u_apsram_top.u_psram_sync.lock_cnt_s_0[15] ALU SUM Out 0.517 3.737 f - lock_cnt_s[15] Net - - 0.589 - 1 u_apsram_top.u_psram_sync.lock_cnt[15] DFFCE D In - 4.325 f - =============================================================================================================== Total path delay (propagation time + setup) of 4.392 is 2.560(58.3%) logic and 1.833(41.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 3.766 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.699 - Propagation time: 4.325 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.626 Number of logic level(s): 16 Starting point: u_apsram_top.u_psram_sync.lock_syn[1] / Q Ending point: u_apsram_top.u_psram_sync.lock_cnt[14] / D The start point is clocked by psram_memory_interface_top|clk [rising] (rise=0.000 fall=1.883 period=3.766) on pin CLK The end point is clocked by psram_memory_interface_top|clk [rising] (rise=0.000 fall=1.883 period=3.766) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_sync.lock_syn[1] DFFC Q Out 0.267 0.267 r - lock_cnt Net - - 0.656 - 18 u_apsram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 I0 In - 0.923 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 F Out 0.604 1.527 r - lock_cnt_cry_0_RNO[0] Net - - 0.589 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[0] ALU I0 In - 2.115 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[0] ALU COUT Out 0.604 2.719 r - lock_cnt_cry[0] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[1] ALU CIN In - 2.719 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[1] ALU COUT Out 0.038 2.758 r - lock_cnt_cry[1] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[2] ALU CIN In - 2.758 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[2] ALU COUT Out 0.038 2.796 r - lock_cnt_cry[2] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[3] ALU CIN In - 2.796 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[3] ALU COUT Out 0.038 2.835 r - lock_cnt_cry[3] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[4] ALU CIN In - 2.835 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[4] ALU COUT Out 0.038 2.873 r - lock_cnt_cry[4] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[5] ALU CIN In - 2.873 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[5] ALU COUT Out 0.038 2.912 r - lock_cnt_cry[5] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[6] ALU CIN In - 2.912 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[6] ALU COUT Out 0.038 2.950 r - lock_cnt_cry[6] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[7] ALU CIN In - 2.950 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[7] ALU COUT Out 0.038 2.989 r - lock_cnt_cry[7] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[8] ALU CIN In - 2.989 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[8] ALU COUT Out 0.038 3.027 r - lock_cnt_cry[8] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[9] ALU CIN In - 3.027 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[9] ALU COUT Out 0.038 3.066 r - lock_cnt_cry[9] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[10] ALU CIN In - 3.066 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[10] ALU COUT Out 0.038 3.104 r - lock_cnt_cry[10] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[11] ALU CIN In - 3.104 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[11] ALU COUT Out 0.038 3.143 r - lock_cnt_cry[11] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[12] ALU CIN In - 3.143 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[12] ALU COUT Out 0.038 3.181 r - lock_cnt_cry[12] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[13] ALU CIN In - 3.181 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[13] ALU COUT Out 0.038 3.220 r - lock_cnt_cry[13] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[14] ALU CIN In - 3.220 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[14] ALU SUM Out 0.517 3.737 f - lock_cnt_s[14] Net - - 0.589 - 1 u_apsram_top.u_psram_sync.lock_cnt[14] DFFCE D In - 4.325 f - =============================================================================================================== Total path delay (propagation time + setup) of 4.392 is 2.560(58.3%) logic and 1.833(41.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 3.766 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.699 - Propagation time: 4.320 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.621 Number of logic level(s): 17 Starting point: u_apsram_top.u_psram_sync.lock_cnt[0] / Q Ending point: u_apsram_top.u_psram_sync.lock_cnt[15] / D The start point is clocked by psram_memory_interface_top|clk [rising] (rise=0.000 fall=1.883 period=3.766) on pin CLK The end point is clocked by psram_memory_interface_top|clk [rising] (rise=0.000 fall=1.883 period=3.766) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_sync.lock_cnt[0] DFFCE Q Out 0.267 0.267 r - lock_cnt[0] Net - - 0.589 - 2 u_apsram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 I1 In - 0.856 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 F Out 0.627 1.483 r - lock_cnt_cry_0_RNO[0] Net - - 0.589 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[0] ALU I0 In - 2.071 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[0] ALU COUT Out 0.604 2.675 r - lock_cnt_cry[0] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[1] ALU CIN In - 2.675 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[1] ALU COUT Out 0.038 2.714 r - lock_cnt_cry[1] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[2] ALU CIN In - 2.714 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[2] ALU COUT Out 0.038 2.752 r - lock_cnt_cry[2] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[3] ALU CIN In - 2.752 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[3] ALU COUT Out 0.038 2.791 r - lock_cnt_cry[3] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[4] ALU CIN In - 2.791 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[4] ALU COUT Out 0.038 2.829 r - lock_cnt_cry[4] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[5] ALU CIN In - 2.829 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[5] ALU COUT Out 0.038 2.868 r - lock_cnt_cry[5] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[6] ALU CIN In - 2.868 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[6] ALU COUT Out 0.038 2.906 r - lock_cnt_cry[6] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[7] ALU CIN In - 2.906 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[7] ALU COUT Out 0.038 2.945 r - lock_cnt_cry[7] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[8] ALU CIN In - 2.945 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[8] ALU COUT Out 0.038 2.983 r - lock_cnt_cry[8] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[9] ALU CIN In - 2.983 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[9] ALU COUT Out 0.038 3.022 r - lock_cnt_cry[9] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[10] ALU CIN In - 3.022 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[10] ALU COUT Out 0.038 3.060 r - lock_cnt_cry[10] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[11] ALU CIN In - 3.060 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[11] ALU COUT Out 0.038 3.099 r - lock_cnt_cry[11] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[12] ALU CIN In - 3.099 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[12] ALU COUT Out 0.038 3.137 r - lock_cnt_cry[12] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[13] ALU CIN In - 3.137 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[13] ALU COUT Out 0.038 3.176 r - lock_cnt_cry[13] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[14] ALU CIN In - 3.176 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[14] ALU COUT Out 0.038 3.214 r - lock_cnt_cry[14] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_s_0[15] ALU CIN In - 3.214 r - u_apsram_top.u_psram_sync.lock_cnt_s_0[15] ALU SUM Out 0.517 3.731 f - lock_cnt_s[15] Net - - 0.589 - 1 u_apsram_top.u_psram_sync.lock_cnt[15] DFFCE D In - 4.320 f - =============================================================================================================== Total path delay (propagation time + setup) of 4.387 is 2.621(59.8%) logic and 1.766(40.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 3.766 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.699 - Propagation time: 4.287 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.588 Number of logic level(s): 15 Starting point: u_apsram_top.u_psram_sync.lock_syn[1] / Q Ending point: u_apsram_top.u_psram_sync.lock_cnt[15] / D The start point is clocked by psram_memory_interface_top|clk [rising] (rise=0.000 fall=1.883 period=3.766) on pin CLK The end point is clocked by psram_memory_interface_top|clk [rising] (rise=0.000 fall=1.883 period=3.766) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- u_apsram_top.u_psram_sync.lock_syn[1] DFFC Q Out 0.267 0.267 r - lock_cnt Net - - 0.656 - 18 u_apsram_top.u_psram_sync.lock_cnt_cry_0_RNO[2] LUT2 I0 In - 0.923 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0_RNO[2] LUT2 F Out 0.604 1.527 r - lock_cnt_cry_0_RNO[2] Net - - 0.589 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[2] ALU I0 In - 2.115 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[2] ALU COUT Out 0.604 2.719 r - lock_cnt_cry[2] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[3] ALU CIN In - 2.719 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[3] ALU COUT Out 0.038 2.758 r - lock_cnt_cry[3] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[4] ALU CIN In - 2.758 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[4] ALU COUT Out 0.038 2.796 r - lock_cnt_cry[4] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[5] ALU CIN In - 2.796 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[5] ALU COUT Out 0.038 2.835 r - lock_cnt_cry[5] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[6] ALU CIN In - 2.835 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[6] ALU COUT Out 0.038 2.873 r - lock_cnt_cry[6] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[7] ALU CIN In - 2.873 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[7] ALU COUT Out 0.038 2.912 r - lock_cnt_cry[7] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[8] ALU CIN In - 2.912 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[8] ALU COUT Out 0.038 2.950 r - lock_cnt_cry[8] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[9] ALU CIN In - 2.950 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[9] ALU COUT Out 0.038 2.989 r - lock_cnt_cry[9] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[10] ALU CIN In - 2.989 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[10] ALU COUT Out 0.038 3.027 r - lock_cnt_cry[10] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[11] ALU CIN In - 3.027 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[11] ALU COUT Out 0.038 3.066 r - lock_cnt_cry[11] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[12] ALU CIN In - 3.066 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[12] ALU COUT Out 0.038 3.104 r - lock_cnt_cry[12] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[13] ALU CIN In - 3.104 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[13] ALU COUT Out 0.038 3.143 r - lock_cnt_cry[13] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_cry_0[14] ALU CIN In - 3.143 r - u_apsram_top.u_psram_sync.lock_cnt_cry_0[14] ALU COUT Out 0.038 3.181 r - lock_cnt_cry[14] Net - - 0.000 - 1 u_apsram_top.u_psram_sync.lock_cnt_s_0[15] ALU CIN In - 3.181 r - u_apsram_top.u_psram_sync.lock_cnt_s_0[15] ALU SUM Out 0.517 3.698 f - lock_cnt_s[15] Net - - 0.589 - 1 u_apsram_top.u_psram_sync.lock_cnt[15] DFFCE D In - 4.287 f - =============================================================================================================== Total path delay (propagation time + setup) of 4.354 is 2.521(57.9%) logic and 1.833(42.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------ u_apsram_top.u_dqce_clk_x2 System DHCEN CLKOUT clk_x2_i 0.000 -0.108 u_apsram_top.clkdiv System CLKDIV CLKOUT clk_out 0.000 1.141 u_apsram_top.u_dll System DLL STEP[0] dll_step[0] 0.000 1.795 u_apsram_top.u_dll System DLL STEP[1] dll_step[1] 0.000 1.833 u_apsram_top.u_dll System DLL STEP[2] dll_step[2] 0.000 1.872 u_apsram_top.u_dll System DLL STEP[3] dll_step[3] 0.000 1.910 u_apsram_top.u_dll System DLL STEP[4] dll_step[4] 0.000 1.949 u_apsram_top.u_dll System DLL STEP[5] dll_step[5] 0.000 1.987 u_apsram_top.u_dll System DLL STEP[6] dll_step[6] 0.000 2.026 u_apsram_top.u_dll System DLL STEP[7] dll_step[7] 0.000 2.064 ====================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------- u_apsram_top.clkdiv System CLKDIV HCLKIN clk_x2_i 0.614 -0.108 u_apsram_top.u_dll System DLL CLKIN clk_x2_i 0.614 -0.108 u_apsram_top.rd_data_d[0] System DFFC D rd_data_d_3[0] 4.670 1.141 u_apsram_top.rd_data_d[1] System DFFC D rd_data_d_3[1] 4.670 1.141 u_apsram_top.rd_data_d[2] System DFFC D rd_data_d_3[2] 4.670 1.141 u_apsram_top.rd_data_d[3] System DFFC D rd_data_d_3[3] 4.670 1.141 u_apsram_top.rd_data_d[4] System DFFC D rd_data_d_3[4] 4.670 1.141 u_apsram_top.rd_data_d[5] System DFFC D rd_data_d_3[5] 4.670 1.141 u_apsram_top.rd_data_d[6] System DFFC D rd_data_d_3[6] 4.670 1.141 u_apsram_top.rd_data_d[7] System DFFC D rd_data_d_3[7] 4.670 1.141 ======================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.614 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.614 - Propagation time: 0.723 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.108 Number of logic level(s): 0 Starting point: u_apsram_top.u_dqce_clk_x2 / CLKOUT Ending point: u_apsram_top.clkdiv / HCLKIN The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- u_apsram_top.u_dqce_clk_x2 DHCEN CLKOUT Out 0.000 0.000 r - clk_x2_i Net - - 0.723 - 21 u_apsram_top.clkdiv CLKDIV HCLKIN In - 0.723 r - ============================================================================================= Total path delay (propagation time + setup) of 0.723 is 0.000(0.0%) logic and 0.723(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 0.614 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.614 - Propagation time: 0.723 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.108 Number of logic level(s): 0 Starting point: u_apsram_top.u_dqce_clk_x2 / CLKOUT Ending point: u_apsram_top.u_dll / CLKIN The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- u_apsram_top.u_dqce_clk_x2 DHCEN CLKOUT Out 0.000 0.000 r - clk_x2_i Net - - 0.723 - 21 u_apsram_top.u_dll DLL CLKIN In - 0.723 r - ============================================================================================ Total path delay (propagation time + setup) of 0.723 is 0.000(0.0%) logic and 0.723(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.737 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.670 - Propagation time: 3.529 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 1.141 Number of logic level(s): 2 Starting point: u_apsram_top.clkdiv / CLKOUT Ending point: u_apsram_top.rd_data_d[0] / D The start point is clocked by System [rising] The end point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.clkdiv CLKDIV CLKOUT Out 0.000 0.000 r - clk_out Net - - 2.155 - 413 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[0\]\.u_ides4 IDES4 PCLK In - 2.155 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[0\]\.u_ides4 IDES4 Q3 Out 0.181 2.336 r - rd_data_d0[0] Net - - 0.589 - 1 u_apsram_top.rd_data_d_3[0] LUT2 I0 In - 2.925 r - u_apsram_top.rd_data_d_3[0] LUT2 F Out 0.604 3.529 r - rd_data_d_3[0] Net - - 0.000 - 1 u_apsram_top.rd_data_d[0] DFFC D In - 3.529 r - ===================================================================================================================================================== Total path delay (propagation time + setup) of 3.596 is 0.852(23.7%) logic and 2.743(76.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.737 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.670 - Propagation time: 3.529 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 1.141 Number of logic level(s): 2 Starting point: u_apsram_top.clkdiv / CLKOUT Ending point: u_apsram_top.rd_data_d[6] / D The start point is clocked by System [rising] The end point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.clkdiv CLKDIV CLKOUT Out 0.000 0.000 r - clk_out Net - - 2.155 - 413 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[6\]\.u_ides4 IDES4 PCLK In - 2.155 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[6\]\.u_ides4 IDES4 Q3 Out 0.181 2.336 r - rd_data_d0[6] Net - - 0.589 - 1 u_apsram_top.rd_data_d_3[6] LUT2 I0 In - 2.925 r - u_apsram_top.rd_data_d_3[6] LUT2 F Out 0.604 3.529 r - rd_data_d_3[6] Net - - 0.000 - 1 u_apsram_top.rd_data_d[6] DFFC D In - 3.529 r - ===================================================================================================================================================== Total path delay (propagation time + setup) of 3.596 is 0.852(23.7%) logic and 2.743(76.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.737 - Setup time: 0.067 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.670 - Propagation time: 3.529 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 1.141 Number of logic level(s): 2 Starting point: u_apsram_top.clkdiv / CLKOUT Ending point: u_apsram_top.rd_data_d[1] / D The start point is clocked by System [rising] The end point is clocked by _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.369 period=4.737) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------- u_apsram_top.clkdiv CLKDIV CLKOUT Out 0.000 0.000 r - clk_out Net - - 2.155 - 413 u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[1\]\.u_ides4 IDES4 PCLK In - 2.155 r - u_apsram_top.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[1\]\.u_ides4 IDES4 Q3 Out 0.181 2.336 r - rd_data_d0[1] Net - - 0.589 - 1 u_apsram_top.rd_data_d_3[1] LUT2 I0 In - 2.925 r - u_apsram_top.rd_data_d_3[1] LUT2 F Out 0.604 3.529 r - rd_data_d_3[1] Net - - 0.000 - 1 u_apsram_top.rd_data_d[1] DFFC D In - 3.529 r - ===================================================================================================================================================== Total path delay (propagation time + setup) of 3.596 is 0.852(23.7%) logic and 2.743(76.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 256MB peak: 259MB) Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 256MB peak: 259MB) --------------------------------------- Resource Usage Report for psram_memory_interface_top Mapping to part: gw2a_18pbga484-7 Cell usage: ALU 114 uses CLKDIV 1 use DFFC 217 uses DFFCE 197 uses DFFP 7 uses DFFPE 1 use DHCEN 1 use DLL 1 use GSR 1 use IDES4 8 uses INV 9 uses IODELAY 9 uses MUX2_LUT5 1 use OSER4 11 uses SDPX9B 1 use LUT2 211 uses LUT3 138 uses LUT4 287 uses I/O ports: 126 I/O primitives: 125 IBUF 78 uses IOBUF 9 uses OBUF 38 uses I/O Register bits: 0 Register bits not including I/Os: 422 of 15552 (2%) RAM/ROM usage summary Block Rams : 1 of 46 (2%) Total load per clock: _~apsram_top_psram_memory_interface_top_|clk_out_inferred_clock: 412 psram_memory_interface_top|clk: 31 _~apsram_top_psram_memory_interface_top_|clk_x2_inferred_clock: 19 _~apsram_wd_psram_memory_interface_top_|step_derived_clock[0]: 1 _~apsram_init_psram_memory_interface_top_|read_calibration[0]_VALUE_derived_clock[0]: 8 @S |Mapping Summary: Total LUTs: 636 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 90MB peak: 259MB) Process took 0h:00m:07s realtime, 0h:00m:06s cputime # Tue Jan 19 16:46:08 2021 ###########################################################]