| Report Title |
Gowin Power Analysis Report |
| Design File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\a.cst |
| Timing Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\fpga_project.sdc |
| GOWIN Version |
V1.9.7.02Beta |
| Part Number |
GW1NR-LV9QN88PC6/I5 |
| Device |
GW1NR-9C |
| Created Time |
Tue Mar 09 17:34:20 2021
|
| Legal Announcement |
Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
44.873 |
| Quiescent Power (mW) |
3.310 |
| Dynamic Power (mW) |
41.563 |
| Psram Power (mW) |
86.000 |
| Junction Temperature |
25.470 |
| Theta JA |
10.500 |
| Max Allowed Ambient Temperature |
84.530 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.200 |
33.830 |
2.312 |
43.370 |
| VCCX |
2.500 |
0.226 |
0.125 |
0.879 |
| VCCO12 |
1.200 |
0.005 |
0.003 |
0.009 |
| VCCO18 |
1.800 |
0.220 |
0.122 |
0.614 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
3.826 |
NA |
7.496 |
| IO |
1.947
| 0.686
| 15.289
|
| BSRAM |
2.621
| NA |
NA |
| PLL |
11.157
| NA |
NA |
| DLL |
7.373
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
Routing Dynamic Power(mW) |
| syn_top |
40.280 |
24.977(24.976) |
15.303(15.211) |
| syn_top/button/ |
0.501 |
0.268(0.000) |
0.234(0.000) |
| syn_top/psram_memory_interface_top/ |
20.734 |
11.873(11.873) |
8.861(8.861) |
| syn_top/psram_memory_interface_top/u_apsram_top/ |
20.734 |
11.873(4.262) |
8.861(7.686) |
| syn_top/psram_memory_interface_top/u_apsram_top/u_psram_init/ |
4.117 |
0.764(0.000) |
3.353(0.000) |
| syn_top/psram_memory_interface_top/u_apsram_top/u_psram_sync/ |
0.928 |
0.142(0.000) |
0.786(0.000) |
| syn_top/psram_memory_interface_top/u_apsram_top/u_psram_wd/ |
6.903 |
3.356(3.193) |
3.546(3.414) |
| syn_top/psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
6.607 |
3.193(2.746) |
3.414(0.581) |
| syn_top/psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/ |
3.327 |
2.746(0.000) |
0.581(0.000) |
| syn_top/u_test/ |
7.722 |
1.678(0.000) |
6.044(0.000) |
| syn_top/your_instance_name/ |
11.229 |
11.157(0.000) |
0.072(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| clk |
59.999 |
12.706 |
| clk_x1 |
59.999 |
19.905 |
| NO CLOCK DOMAIN |
0.000 |
0.000 |
| clk_x2 |
120.005 |
7.692 |