Pin Messages

Report Title Gowin Pin Report
Design File E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\a.cst
Timing Constraints File E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\fpga_project.sdc
GOWIN Version V1.9.7.02Beta
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9C
Created Time Tue Mar 09 17:34:20 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Pin Details

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor BankVccio
clk 63/1 N in IOR5[A] LVCMOS18 NA UP NA NONE NA NA NA OFF NA 1.8
rst_n 85/3 Y in IOT8[B] LVCMOS18 NA UP NA NONE NA NA NA OFF NA 1.2
O_apsram_ck 26/2 N out IOB8[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
O_apsram_cs_n 28/2 N out IOB11[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
error 49/1 Y out IOR24[A] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
init_calib 50/1 Y out IOR22[B] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
led[0] 51/1 Y out IOR17[B] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
led[1] 52/1 Y out IOR17[A] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
IO_apsram_dqsm 37/2 N io IOB31[A] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
IO_apsram_dq[0] 41/2 N io IOB41[A] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
IO_apsram_dq[1] 47/2 N io IOB43[B] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
IO_apsram_dq[2] 35/2 N io IOB29[A] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
IO_apsram_dq[3] 39/2 N io IOB33[A] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
IO_apsram_dq[4] 38/2 N io IOB31[B] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
IO_apsram_dq[5] 40/2 N io IOB33[B] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
IO_apsram_dq[6] 42/2 N io IOB41[B] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
IO_apsram_dq[7] 48/1 N io IOR24[B] LVCMOS18 8 UP NA NONE OFF FAST NA OFF NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor Bank Vccio
3/3 - in IOT2[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
88/3 - in IOT5[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
87/3 - in IOT6[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
86/3 - in IOT8[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
85/3 rst_n in IOT8[B] LVCMOS18 NA UP NA NONE NA NA NA OFF NA 1.2
84/3 - in IOT10[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
83/3 - in IOT10[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
82/3 - in IOT11[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
81/3 - in IOT11[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
80/3 - in IOT12[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
79/3 - in IOT12[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
77/1 - in IOT37[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
76/1 - in IOT37[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
75/1 - in IOT38[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
74/1 - in IOT38[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
73/1 - in IOT39[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
72/1 - in IOT39[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
71/1 - in IOT41[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
70/1 - in IOT41[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
69/1 - in IOT42[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
68/1 - in IOT42[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
17/2 - in IOB2[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
18/2 - in IOB2[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
19/2 - in IOB4[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
20/2 - in IOB4[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
25/2 - in IOB8[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
26/2 O_apsram_ck out IOB8[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
27/2 - in IOB11[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
28/2 O_apsram_cs_n out IOB11[B] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.8
29/2 - in IOB13[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
30/2 - in IOB13[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
31/2 - in IOB15[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
32/2 - in IOB15[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
33/2 - in IOB23[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
34/2 - in IOB23[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
35/2 IO_apsram_dq[2] io IOB29[A] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
36/2 - in IOB29[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
37/2 IO_apsram_dqsm io IOB31[A] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
38/2 IO_apsram_dq[4] io IOB31[B] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
39/2 IO_apsram_dq[3] io IOB33[A] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
40/2 IO_apsram_dq[5] io IOB33[B] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
41/2 IO_apsram_dq[0] io IOB41[A] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
42/2 IO_apsram_dq[6] io IOB41[B] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
47/2 IO_apsram_dq[1] io IOB43[B] LVCMOS18 8 UP NA NONE OFF FAST NA NA NA 1.8
4/3 - in IOL5[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
5/3 - in IOL11[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
6/3 - in IOL11[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
7/3 - in IOL12[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
8/3 - out IOL13[A] LVCMOS18 8 UP NA NA OFF FAST NA NA NA 1.2
9/3 - in IOL13[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
10/3 - in IOL15[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
11/3 - in IOL16[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
13/3 - in IOL21[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
14/3 - in IOL22[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
15/3 - in IOL25[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
16/3 - in IOL26[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
63/1 clk in IOR5[A] LVCMOS18 NA UP NA NONE NA NA NA OFF NA 1.8
62/1 - in IOR11[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
61/1 - in IOR11[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
60/1 - in IOR12[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
59/1 - in IOR12[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
57/1 - in IOR13[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
56/1 - in IOR14[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
55/1 - in IOR14[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
54/1 - in IOR15[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
53/1 - in IOR15[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.8
52/1 led[1] out IOR17[A] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
51/1 led[0] out IOR17[B] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
50/1 init_calib out IOR22[B] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
49/1 error out IOR24[A] LVCMOS18 8 UP NA NA OFF FAST NA OFF NA 1.8
48/1 IO_apsram_dq[7] io IOR24[B] LVCMOS18 8 UP NA NONE OFF FAST NA OFF NA 1.8