Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\UHS_PSRAM_2\data\5a\PSRAM_64_TOP.v
D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\UHS_PSRAM_2\data\5a\apsram_64_code.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10.01 (64-bit)
Part Number GW5AR-LV25UG256PC2/I1
Device GW5AR-25
Device Version A
Created Time Thu Aug 8 18:53:58 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module UHS_PSRAM_Memory_Interface_V2_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.781s, Elapsed time = 0h 0m 0.792s, Peak memory usage = 106.945MB
Running netlist conversion:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 106.945MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.215s, Peak memory usage = 106.945MB
    Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.168s, Peak memory usage = 106.945MB
    Optimizing Phase 2: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.585s, Peak memory usage = 106.945MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.226s, Peak memory usage = 106.945MB
    Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 106.945MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 106.945MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 106.945MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.265s, Peak memory usage = 106.945MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 106.945MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 106.945MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 128.332MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.275s, Peak memory usage = 128.332MB
Generate output files:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.259s, Peak memory usage = 128.332MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 128.332MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 323
Embedded Port 28
I/O Buf 344
    IBUF 183
    OBUF 139
    TBUF 2
    IOBUF 16
    ELVDS_OBUF 2
    ELVDS_IOBUF 2
Register 1972
    DFFRE 257
    DFFPE 9
    DFFCE 1706
LUT 1853
    LUT2 605
    LUT3 642
    LUT4 606
ALU 62
    ALU 62
INV 36
    INV 36
IOLOGIC 44
    IDES8_MEM 16
    OSER8 4
    OSER8_MEM 20
    IODELAY 4
BSRAM 8
    SDPB 4
    SDPX9B 4
CLOCK 5
    CLKDIV 1
    DQS 2
    DDRDLL 1
    DHCE 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1951(1889 LUT, 62 ALU) / 23040 9%
Register 1972 / 23640 9%
  --Register as Latch 0 / 23640 0%
  --Register as FF 1972 / 23640 9%
BSRAM 8 / 56 15%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
2 clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
3 u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 memory_clk_ibuf/I memory_clk u_apm64_top/clk_x4_div/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 memory_clk 100.000(MHz) 1394.294(MHz) 1 TOP
2 clk 100.000(MHz) 283.046(MHz) 5 TOP
3 u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk 25.000(MHz) 1522.075(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.072
Data Arrival Time 1.196
Data Required Time 5.268
From u_apm64_top/u_apsram_init/hold_s0
To u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
Launch Clk u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
0.290 0.290 tCL RR 2000 u_apm64_top/clk_x4_div/CLKOUT
0.590 0.300 tNET RR 1 u_apm64_top/u_apsram_init/hold_s0/CLK
0.896 0.306 tC2Q RR 2 u_apm64_top/u_apsram_init/hold_s0/Q
1.196 0.300 tNET RR 1 u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.000 0.000 tINS FF 1 memory_clk_ibuf/O
5.280 0.280 tNET FF 3 u_apm64_top/u_dqce_clk_x4/CLKIN
5.440 0.160 tINS FF 44 u_apm64_top/u_dqce_clk_x4/CLKOUT
5.720 0.280 tNET FF 1 u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
5.685 -0.035 tUnc u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
5.268 -0.417 tSu 1 u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
Path Statistics:
Clock Skew: 0.130
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.300, 49.505%; tC2Q: 0.306, 50.495%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 4.072
Data Arrival Time 1.196
Data Required Time 5.268
From u_apm64_top/u_apsram_init/hold_s0
To u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs
Launch Clk u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
0.290 0.290 tCL RR 2000 u_apm64_top/clk_x4_div/CLKOUT
0.590 0.300 tNET RR 1 u_apm64_top/u_apsram_init/hold_s0/CLK
0.896 0.306 tC2Q RR 2 u_apm64_top/u_apsram_init/hold_s0/Q
1.196 0.300 tNET RR 1 u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.000 0.000 tINS FF 1 memory_clk_ibuf/O
5.280 0.280 tNET FF 3 u_apm64_top/u_dqce_clk_x4/CLKIN
5.440 0.160 tINS FF 44 u_apm64_top/u_dqce_clk_x4/CLKOUT
5.720 0.280 tNET FF 1 u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs/FCLK
5.685 -0.035 tUnc u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs
5.268 -0.417 tSu 1 u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs
Path Statistics:
Clock Skew: 0.130
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.300, 49.505%; tC2Q: 0.306, 50.495%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 4.182
Data Arrival Time 0.906
Data Required Time 5.088
From u_apm64_top/u_apsram_sync/cs_memsync_4_s0
To u_apm64_top/u_dqce_clk_x4
Launch Clk clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.300 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/cs_memsync_4_s0/CLK
0.606 0.306 tC2Q RR 7 u_apm64_top/u_apsram_sync/cs_memsync_4_s0/Q
0.906 0.300 tNET RR 1 u_apm64_top/u_dqce_clk_x4/CEN
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.000 0.000 tINS FF 1 memory_clk_ibuf/O
5.280 0.280 tNET FF 3 u_apm64_top/u_dqce_clk_x4/CLKIN
5.245 -0.035 tUnc u_apm64_top/u_dqce_clk_x4
5.088 -0.157 tSu 1 u_apm64_top/u_dqce_clk_x4
Path Statistics:
Clock Skew: -0.020
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.300, 49.505%; tC2Q: 0.306, 50.495%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 6.467
Data Arrival Time 3.782
Data Required Time 10.249
From u_apm64_top/u_apsram_sync/cs_memsync_3_s0
To u_apm64_top/u_apsram_sync/flag_0_s4
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.300 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/cs_memsync_3_s0/CLK
0.606 0.306 tC2Q RR 9 u_apm64_top/u_apsram_sync/cs_memsync_3_s0/Q
0.906 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/ns_memsync_1_s13/I0
1.327 0.421 tINS RR 5 u_apm64_top/u_apsram_sync/ns_memsync_1_s13/F
1.627 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/flag_d_0_s15/I0
2.048 0.421 tINS RR 2 u_apm64_top/u_apsram_sync/flag_d_0_s15/F
2.348 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/flag_d_0_s12/I1
2.761 0.413 tINS RR 1 u_apm64_top/u_apsram_sync/flag_d_0_s12/F
3.061 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/flag_d_0_s14/I0
3.482 0.421 tINS RR 1 u_apm64_top/u_apsram_sync/flag_d_0_s14/F
3.782 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/flag_0_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 31 clk_ibuf/O
10.300 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/flag_0_s4/CLK
10.249 -0.051 tSu 1 u_apm64_top/u_apsram_sync/flag_0_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.676, 48.133%; route: 1.500, 43.079%; tC2Q: 0.306, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 6.467
Data Arrival Time 3.782
Data Required Time 10.249
From u_apm64_top/u_apsram_sync/lock_cnt_0_s3
To u_apm64_top/u_apsram_sync/lock_cnt_12_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.300 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/lock_cnt_0_s3/CLK
0.606 0.306 tC2Q RR 6 u_apm64_top/u_apsram_sync/lock_cnt_0_s3/Q
0.906 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/n50_s2/I0
1.327 0.421 tINS RR 4 u_apm64_top/u_apsram_sync/n50_s2/F
1.627 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/n47_s3/I1
2.040 0.413 tINS RR 5 u_apm64_top/u_apsram_sync/n47_s3/F
2.340 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/n44_s9/I0
2.761 0.421 tINS RR 3 u_apm64_top/u_apsram_sync/n44_s9/F
3.061 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/n42_s1/I0
3.482 0.421 tINS RR 1 u_apm64_top/u_apsram_sync/n42_s1/F
3.782 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/lock_cnt_12_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 31 clk_ibuf/O
10.300 0.300 tNET RR 1 u_apm64_top/u_apsram_sync/lock_cnt_12_s1/CLK
10.249 -0.051 tSu 1 u_apm64_top/u_apsram_sync/lock_cnt_12_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.676, 48.133%; route: 1.500, 43.079%; tC2Q: 0.306, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%