Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\src\gowin_pll\gowin_pll.v E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\src\key_debounce.v E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\src\test.v E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\src\top.v E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\src\uhs_psram_memory_interface_v2\uhs_psram_memory_interface_v2.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.10.01 (64-bit) |
| Part Number | GW5AR-LV25UG256PC2/I1 |
| Device | GW5AR-25 |
| Device Version | A |
| Created Time | Thu Aug 8 18:54:06 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.72s, Peak memory usage = 239.156MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 239.156MB Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 239.156MB Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 239.156MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 239.156MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 239.156MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 239.156MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 239.156MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 239.156MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 239.156MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 239.156MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.316s, Peak memory usage = 256.609MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 256.609MB Generate output files: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.252s, Peak memory usage = 256.609MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 256.609MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 4 |
| Embedded Port | 28 |
| I/O Buf | 28 |
| IBUF | 2 |
| OBUF | 4 |
| TBUF | 2 |
| IOBUF | 16 |
| ELVDS_OBUF | 2 |
| ELVDS_IOBUF | 2 |
| Register | 2343 |
| DFFRE | 278 |
| DFFPE | 10 |
| DFFCE | 2055 |
| LUT | 1964 |
| LUT2 | 610 |
| LUT3 | 709 |
| LUT4 | 645 |
| ALU | 235 |
| ALU | 235 |
| INV | 38 |
| INV | 38 |
| IOLOGIC | 44 |
| IDES8_MEM | 16 |
| OSER8 | 4 |
| OSER8_MEM | 20 |
| IODELAY | 4 |
| BSRAM | 8 |
| SDPB | 4 |
| SDPX9B | 4 |
| CLOCK | 6 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
| DHCE | 1 |
| PLLA | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2237(2002 LUT, 235 ALU) / 23040 | 10% |
| Register | 2343 / 23640 | 10% |
| --Register as Latch | 0 / 23640 | 0% |
| --Register as FF | 2343 / 23640 | 10% |
| BSRAM | 8 / 56 | 15% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 2.500 | 400.0 | 0.000 | 1.250 | clk_ibuf/I | clk | u_Gowin_PLL/PLLA_inst/CLKOUT0 |
| 3 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | u_Gowin_PLL/PLLA_inst/CLKOUT0 | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 283.046(MHz) | 5 | TOP |
| 2 | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | 400.000(MHz) | 1394.296(MHz) | 1 | TOP |
| 3 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk | 100.000(MHz) | 1522.071(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.213 |
| Data Arrival Time | 10.291 |
| Data Required Time | 10.504 |
| From | inst_apm64_top/u_apm64_top/u_apm64_dll |
| To | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[1].RMOVE_PAR_7_s0 |
| Launch Clk | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 7.744 | 0.244 | tCL | RR | 1 | u_Gowin_PLL/PLLA_inst/CLKOUT0 |
| 8.044 | 0.300 | tNET | RR | 3 | inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN |
| 8.201 | 0.157 | tINS | RR | 44 | inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT |
| 8.501 | 0.300 | tNET | RR | 8 | inst_apm64_top/u_apm64_top/u_apm64_dll/CLKIN |
| 8.851 | 0.350 | tINS | RR | 3 | inst_apm64_top/u_apm64_top/u_apm64_dll/STEP[1] |
| 9.151 | 0.300 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/I0 |
| 9.596 | 0.445 | tINS | RF | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/COUT |
| 9.596 | 0.000 | tNET | FF | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/CIN |
| 9.636 | 0.040 | tINS | FR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/COUT |
| 9.636 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/CIN |
| 9.676 | 0.040 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/COUT |
| 9.676 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/CIN |
| 9.716 | 0.040 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/COUT |
| 9.716 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/CIN |
| 9.756 | 0.040 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/COUT |
| 9.756 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n9_s/CIN |
| 9.796 | 0.040 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n9_s/COUT |
| 9.796 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n8_s/CIN |
| 9.991 | 0.195 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n8_s/SUM |
| 10.291 | 0.300 | tNET | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[1].RMOVE_PAR_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk | |||
| 10.290 | 0.290 | tCL | RR | 2321 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT |
| 10.590 | 0.300 | tNET | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[1].RMOVE_PAR_7_s0/CLK |
| 10.555 | -0.035 | tUnc | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[1].RMOVE_PAR_7_s0 | ||
| 10.504 | -0.051 | tSu | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[1].RMOVE_PAR_7_s0 |
| Clock Skew: | -0.111 |
| Setup Relationship: | 2.500 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.157, 34.338%; route: 0.300, 65.662% |
| Arrival Data Path Delay: | cell: 1.190, 56.937%; route: 0.600, 28.709%; tC2Q: 0.300, 14.354% |
| Required Clock Path Delay: | cell: 0.157, 34.338%; route: 0.300, 65.662% |
Path 2
Path Summary:| Slack | 0.253 |
| Data Arrival Time | 10.251 |
| Data Required Time | 10.504 |
| From | inst_apm64_top/u_apm64_top/u_apm64_dll |
| To | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_6_s0 |
| Launch Clk | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 7.744 | 0.244 | tCL | RR | 1 | u_Gowin_PLL/PLLA_inst/CLKOUT0 |
| 8.044 | 0.300 | tNET | RR | 3 | inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN |
| 8.201 | 0.157 | tINS | RR | 44 | inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT |
| 8.501 | 0.300 | tNET | RR | 8 | inst_apm64_top/u_apm64_top/u_apm64_dll/CLKIN |
| 8.851 | 0.350 | tINS | RR | 3 | inst_apm64_top/u_apm64_top/u_apm64_dll/STEP[1] |
| 9.151 | 0.300 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/I0 |
| 9.596 | 0.445 | tINS | RF | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/COUT |
| 9.596 | 0.000 | tNET | FF | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/CIN |
| 9.636 | 0.040 | tINS | FR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/COUT |
| 9.636 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/CIN |
| 9.676 | 0.040 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/COUT |
| 9.676 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/CIN |
| 9.716 | 0.040 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/COUT |
| 9.716 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/CIN |
| 9.756 | 0.040 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/COUT |
| 9.756 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n9_s/CIN |
| 9.951 | 0.195 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n9_s/SUM |
| 10.251 | 0.300 | tNET | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_6_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk | |||
| 10.290 | 0.290 | tCL | RR | 2321 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT |
| 10.590 | 0.300 | tNET | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_6_s0/CLK |
| 10.555 | -0.035 | tUnc | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_6_s0 | ||
| 10.504 | -0.051 | tSu | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_6_s0 |
| Clock Skew: | -0.111 |
| Setup Relationship: | 2.500 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.157, 34.338%; route: 0.300, 65.662% |
| Arrival Data Path Delay: | cell: 1.150, 56.097%; route: 0.600, 29.269%; tC2Q: 0.300, 14.634% |
| Required Clock Path Delay: | cell: 0.157, 34.338%; route: 0.300, 65.662% |
Path 3
Path Summary:| Slack | 0.293 |
| Data Arrival Time | 10.211 |
| Data Required Time | 10.504 |
| From | inst_apm64_top/u_apm64_top/u_apm64_dll |
| To | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_5_s0 |
| Launch Clk | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 7.744 | 0.244 | tCL | RR | 1 | u_Gowin_PLL/PLLA_inst/CLKOUT0 |
| 8.044 | 0.300 | tNET | RR | 3 | inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN |
| 8.201 | 0.157 | tINS | RR | 44 | inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT |
| 8.501 | 0.300 | tNET | RR | 8 | inst_apm64_top/u_apm64_top/u_apm64_dll/CLKIN |
| 8.851 | 0.350 | tINS | RR | 3 | inst_apm64_top/u_apm64_top/u_apm64_dll/STEP[1] |
| 9.151 | 0.300 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/I0 |
| 9.596 | 0.445 | tINS | RF | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/COUT |
| 9.596 | 0.000 | tNET | FF | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/CIN |
| 9.636 | 0.040 | tINS | FR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/COUT |
| 9.636 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/CIN |
| 9.676 | 0.040 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/COUT |
| 9.676 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/CIN |
| 9.716 | 0.040 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/COUT |
| 9.716 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/CIN |
| 9.911 | 0.195 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/SUM |
| 10.211 | 0.300 | tNET | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk | |||
| 10.290 | 0.290 | tCL | RR | 2321 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT |
| 10.590 | 0.300 | tNET | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_5_s0/CLK |
| 10.555 | -0.035 | tUnc | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_5_s0 | ||
| 10.504 | -0.051 | tSu | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_5_s0 |
| Clock Skew: | -0.111 |
| Setup Relationship: | 2.500 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.157, 34.338%; route: 0.300, 65.662% |
| Arrival Data Path Delay: | cell: 1.110, 55.223%; route: 0.600, 29.851%; tC2Q: 0.300, 14.926% |
| Required Clock Path Delay: | cell: 0.157, 34.338%; route: 0.300, 65.662% |
Path 4
Path Summary:| Slack | 0.333 |
| Data Arrival Time | 10.171 |
| Data Required Time | 10.504 |
| From | inst_apm64_top/u_apm64_top/u_apm64_dll |
| To | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_4_s0 |
| Launch Clk | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 7.744 | 0.244 | tCL | RR | 1 | u_Gowin_PLL/PLLA_inst/CLKOUT0 |
| 8.044 | 0.300 | tNET | RR | 3 | inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN |
| 8.201 | 0.157 | tINS | RR | 44 | inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT |
| 8.501 | 0.300 | tNET | RR | 8 | inst_apm64_top/u_apm64_top/u_apm64_dll/CLKIN |
| 8.851 | 0.350 | tINS | RR | 3 | inst_apm64_top/u_apm64_top/u_apm64_dll/STEP[1] |
| 9.151 | 0.300 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/I0 |
| 9.596 | 0.445 | tINS | RF | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/COUT |
| 9.596 | 0.000 | tNET | FF | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/CIN |
| 9.636 | 0.040 | tINS | FR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/COUT |
| 9.636 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/CIN |
| 9.676 | 0.040 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/COUT |
| 9.676 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/CIN |
| 9.871 | 0.195 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/SUM |
| 10.171 | 0.300 | tNET | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk | |||
| 10.290 | 0.290 | tCL | RR | 2321 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT |
| 10.590 | 0.300 | tNET | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_4_s0/CLK |
| 10.555 | -0.035 | tUnc | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_4_s0 | ||
| 10.504 | -0.051 | tSu | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_4_s0 |
| Clock Skew: | -0.111 |
| Setup Relationship: | 2.500 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.157, 34.338%; route: 0.300, 65.662% |
| Arrival Data Path Delay: | cell: 1.070, 54.314%; route: 0.600, 30.457%; tC2Q: 0.300, 15.229% |
| Required Clock Path Delay: | cell: 0.157, 34.338%; route: 0.300, 65.662% |
Path 5
Path Summary:| Slack | 0.373 |
| Data Arrival Time | 10.131 |
| Data Required Time | 10.504 |
| From | inst_apm64_top/u_apm64_top/u_apm64_dll |
| To | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_3_s0 |
| Launch Clk | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 7.744 | 0.244 | tCL | RR | 1 | u_Gowin_PLL/PLLA_inst/CLKOUT0 |
| 8.044 | 0.300 | tNET | RR | 3 | inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN |
| 8.201 | 0.157 | tINS | RR | 44 | inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT |
| 8.501 | 0.300 | tNET | RR | 8 | inst_apm64_top/u_apm64_top/u_apm64_dll/CLKIN |
| 8.851 | 0.350 | tINS | RR | 3 | inst_apm64_top/u_apm64_top/u_apm64_dll/STEP[1] |
| 9.151 | 0.300 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/I0 |
| 9.596 | 0.445 | tINS | RF | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/COUT |
| 9.596 | 0.000 | tNET | FF | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/CIN |
| 9.636 | 0.040 | tINS | FR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/COUT |
| 9.636 | 0.000 | tNET | RR | 2 | inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/CIN |
| 9.831 | 0.195 | tINS | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/SUM |
| 10.131 | 0.300 | tNET | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk | |||
| 10.290 | 0.290 | tCL | RR | 2321 | inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT |
| 10.590 | 0.300 | tNET | RR | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_3_s0/CLK |
| 10.555 | -0.035 | tUnc | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_3_s0 | ||
| 10.504 | -0.051 | tSu | 1 | inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_3_s0 |
| Clock Skew: | -0.111 |
| Setup Relationship: | 2.500 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.157, 34.338%; route: 0.300, 65.662% |
| Arrival Data Path Delay: | cell: 1.030, 53.367%; route: 0.600, 31.089%; tC2Q: 0.300, 15.544% |
| Required Clock Path Delay: | cell: 0.157, 34.338%; route: 0.300, 65.662% |