Attention:
	1. if you reconfig the ip parameters,which reload the ddr_memory_interface.ipc and re-generator. 
	   please attention bits width of the top.v, tb.v, apsram_test.v file. for example, in the tb.v:
	   	O_ck, IO_dqsm, IO_dq......

	   int the ddr3_syn_top.v file:
	   O_apsram_ck, IO_apsram_dqsm, IO_apsram_dq, O_apsram_cs_n, error, init_calib......

	2. for simulation, please in the../../project/fpga_project/src/apsram_param.v file,open below:
	   `define SIM
	   for board test, please in the../../project/fpga_project/src/apsram_param.v file,close below:
	   `define SIM

1.Run Command
    method 1: do cmd.do , in the Transcript windows of the Modesim Tool

2.Files Introduction

    prim_sim.v                  :
                                simulation library
    cmd.do                      :
                                modesim  do(command) file
    compile.f                   :
                                modesim compile design file

