Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\datasheet\PROJECT\3_04\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\src\apsram_test.v D:\datasheet\PROJECT\3_04\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\src\button.v D:\datasheet\PROJECT\3_04\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\src\gowin_rpll\gowin_rpll.v D:\datasheet\PROJECT\3_04\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\src\top.v D:\datasheet\PROJECT\3_04\apsram_reference_design\apsram_256_double_Refdesign\project\fpga_project\src\uhs_psram_memory_interface_v2\uhs_psram_memory_interface_v2.v |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
| Part Number | GW1NR-LV9QN88PC6/I5 |
| Device | GW1NR-9C |
| Created Time | Wed Mar 10 09:15:54 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | syn_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.292s, Peak memory usage = 258.746MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 258.746MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 258.746MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 258.746MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 258.746MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 258.746MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 258.746MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 258.746MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 258.746MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 258.746MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 258.746MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 258.746MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 258.746MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 258.746MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 258.746MB |
Resource
Resource Usage Summary
| I/O Port | 17 |
| I/O Buf | 17 |
| IBUF | 2 |
| OBUF | 6 |
| IOBUF | 9 |
| Register | 728 |
| DFF | 3 |
| DFFE | 1 |
| DFFR | 20 |
| DFFP | 8 |
| DFFPE | 3 |
| DFFC | 314 |
| DFFCE | 379 |
| LUT | 1132 |
| LUT2 | 284 |
| LUT3 | 270 |
| LUT4 | 578 |
| ALU | 113 |
| ALU | 113 |
| INV | 10 |
| INV | 10 |
| IOLOGIC | 27 |
| IDES4 | 8 |
| OSER4 | 11 |
| IODELAY | 8 |
| BSRAM | 1 |
| SDPX9B | 1 |
| CLOCK | 6 |
| DLL | 1 |
| CLKDIV | 2 |
| DHCEN | 2 |
| rPLL | 1 |
Resource Utilization Summary
| Logic | 1255(1142 LUTs, 113 ALUs) / 8640 | 15% |
| Register | 728 / 6693 | 11% |
| --Register as Latch | 0 / 6693 | 0% |
| --Register as FF | 728 / 6693 | 11% |
| BSRAM | 1 / 26 | 4% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 41.667 | 24.0 | 0.000 | 20.833 | clk_ibuf/I | ||
| your_instance_name/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.250 | 160.0 | 0.000 | 3.125 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUT |
| your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.250 | 160.0 | 3.125 | 0.000 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTP |
| your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | Generated | 25.000 | 40.0 | 0.000 | 12.500 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD |
| your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 18.750 | 53.3 | 0.000 | 9.375 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD3 |
| psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | your_instance_name/rpll_inst/CLKOUT | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT.default_gen_clk | Generated | 12.500 | 80.0 | 3.125 | 9.375 | your_instance_name/rpll_inst/CLKOUTP | your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 24.0(MHz) | 180.9(MHz) | 4 | TOP |
| 2 | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | 40.0(MHz) | 130.6(MHz) | 5 | TOP |
| 3 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | 80.0(MHz) | 116.1(MHz) | 6 | TOP |
| 4 | psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT.default_gen_clk | 80.0(MHz) | 747.2(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.757 |
| Data Arrival Time | 1.665 |
| Data Required Time | 3.421 |
| From | psram_memory_interface_top/u_apsram_top/u_psram_init/Tvcs_done_s0 |
| To | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/Tvcs_done_d_0_s0 |
| Launch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 0.363 | 0.363 | tCL | RR | 690 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 0.727 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_init/Tvcs_done_s0/CLK |
| 1.185 | 0.458 | tC2Q | RF | 4 | psram_memory_interface_top/u_apsram_top/u_psram_init/Tvcs_done_s0/Q |
| 1.665 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/Tvcs_done_d_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 3.125 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT.default_gen_clk | |||
| 3.489 | 0.363 | tCL | RR | 3 | psram_memory_interface_top/u_apsram_top/clkdivp/CLKOUT |
| 3.852 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/Tvcs_done_d_0_s0/CLK |
| 3.822 | -0.030 | tUnc | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/Tvcs_done_d_0_s0 | ||
| 3.422 | -0.400 | tSu | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/Tvcs_done_d_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 3.125 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.480, 51.155%; tC2Q: 0.458, 48.845% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 2
Path Summary:| Slack | 2.078 |
| Data Arrival Time | 3.001 |
| Data Required Time | 5.079 |
| From | psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0 |
| To | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F] |
| Latch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | |||
| 1.700 | 1.700 | tCL | RR | 31 | your_instance_name/rpll_inst/CLKOUTD |
| 2.063 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/CLK |
| 2.521 | 0.458 | tC2Q | RF | 9 | psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/Q |
| 3.001 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 3.125 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 4.883 | 1.758 | tCL | FF | 1 | your_instance_name/rpll_inst/CLKOUT |
| 5.363 | 0.480 | tNET | FF | 3 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 5.333 | -0.030 | tUnc | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2 | ||
| 5.079 | -0.254 | tSu | 1 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2 |
| Clock Skew: | 0.175 |
| Setup Relationship: | 3.125 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.480, 51.155%; tC2Q: 0.458, 48.845% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.480, 100.000% |
Path 3
Path Summary:| Slack | 3.888 |
| Data Arrival Time | 8.939 |
| Data Required Time | 12.827 |
| From | psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s0 |
| To | u_test/curr_state.CYC_DONE_WAITE_s0 |
| Launch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 0.363 | 0.363 | tCL | RR | 690 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 0.727 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s0/CLK |
| 1.185 | 0.458 | tC2Q | RF | 4 | psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s0/Q |
| 1.665 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I1 |
| 2.764 | 1.099 | tINS | FF | 5 | psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F |
| 3.244 | 0.480 | tNET | FF | 1 | u_test/next_state.CMD_WAITE_s16/I1 |
| 4.343 | 1.099 | tINS | FF | 5 | u_test/next_state.CMD_WAITE_s16/F |
| 4.823 | 0.480 | tNET | FF | 1 | u_test/next_state.WRITE_BURST_s17/I2 |
| 5.645 | 0.822 | tINS | FF | 2 | u_test/next_state.WRITE_BURST_s17/F |
| 6.125 | 0.480 | tNET | FF | 1 | u_test/next_state.CYC_DONE_WAITE_s15/I2 |
| 6.947 | 0.822 | tINS | FF | 1 | u_test/next_state.CYC_DONE_WAITE_s15/F |
| 7.427 | 0.480 | tNET | FF | 1 | u_test/next_state.CYC_DONE_WAITE_s14/I0 |
| 8.459 | 1.032 | tINS | FF | 1 | u_test/next_state.CYC_DONE_WAITE_s14/F |
| 8.939 | 0.480 | tNET | FF | 1 | u_test/curr_state.CYC_DONE_WAITE_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.864 | 0.363 | tCL | RR | 690 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.227 | 0.363 | tNET | RR | 1 | u_test/curr_state.CYC_DONE_WAITE_s0/CLK |
| 12.827 | -0.400 | tSu | 1 | u_test/curr_state.CYC_DONE_WAITE_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
| Arrival Data Path Delay: | cell: 4.874, 59.350%; route: 2.880, 35.069%; tC2Q: 0.458, 5.581% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 4
Path Summary:| Slack | 3.888 |
| Data Arrival Time | 8.939 |
| Data Required Time | 12.827 |
| From | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0 |
| To | u_test/curr_state.READ_WAITE_s0 |
| Launch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 0.363 | 0.363 | tCL | RR | 690 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 0.727 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0/CLK |
| 1.185 | 0.458 | tC2Q | RF | 24 | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0/Q |
| 1.665 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/I1 |
| 2.764 | 1.099 | tINS | FF | 9 | psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/F |
| 3.244 | 0.480 | tNET | FF | 1 | u_test/next_state.CYC_DONE_s17/I0 |
| 4.276 | 1.032 | tINS | FF | 2 | u_test/next_state.CYC_DONE_s17/F |
| 4.756 | 0.480 | tNET | FF | 1 | u_test/next_state.READ_BURST_s16/I2 |
| 5.578 | 0.822 | tINS | FF | 2 | u_test/next_state.READ_BURST_s16/F |
| 6.058 | 0.480 | tNET | FF | 1 | u_test/next_state.CMD_WAITE_s15/I2 |
| 6.880 | 0.822 | tINS | FF | 2 | u_test/next_state.CMD_WAITE_s15/F |
| 7.360 | 0.480 | tNET | FF | 1 | u_test/next_state.READ_WAITE_s12/I1 |
| 8.459 | 1.099 | tINS | FF | 1 | u_test/next_state.READ_WAITE_s12/F |
| 8.939 | 0.480 | tNET | FF | 1 | u_test/curr_state.READ_WAITE_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.864 | 0.363 | tCL | RR | 690 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.227 | 0.363 | tNET | RR | 1 | u_test/curr_state.READ_WAITE_s0/CLK |
| 12.827 | -0.400 | tSu | 1 | u_test/curr_state.READ_WAITE_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
| Arrival Data Path Delay: | cell: 4.874, 59.350%; route: 2.880, 35.069%; tC2Q: 0.458, 5.581% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 5
Path Summary:| Slack | 3.888 |
| Data Arrival Time | 8.939 |
| Data Required Time | 12.827 |
| From | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0 |
| To | u_test/curr_state.CMD_WAITE_s0 |
| Launch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 0.363 | 0.363 | tCL | RR | 690 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 0.727 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0/CLK |
| 1.185 | 0.458 | tC2Q | RF | 24 | psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0/Q |
| 1.665 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/I1 |
| 2.764 | 1.099 | tINS | FF | 9 | psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/F |
| 3.244 | 0.480 | tNET | FF | 1 | u_test/next_state.CYC_DONE_s17/I0 |
| 4.276 | 1.032 | tINS | FF | 2 | u_test/next_state.CYC_DONE_s17/F |
| 4.756 | 0.480 | tNET | FF | 1 | u_test/next_state.READ_BURST_s16/I2 |
| 5.578 | 0.822 | tINS | FF | 2 | u_test/next_state.READ_BURST_s16/F |
| 6.058 | 0.480 | tNET | FF | 1 | u_test/next_state.CMD_WAITE_s15/I2 |
| 6.880 | 0.822 | tINS | FF | 2 | u_test/next_state.CMD_WAITE_s15/F |
| 7.360 | 0.480 | tNET | FF | 1 | u_test/next_state.CMD_WAITE_s13/I1 |
| 8.459 | 1.099 | tINS | FF | 1 | u_test/next_state.CMD_WAITE_s13/F |
| 8.939 | 0.480 | tNET | FF | 1 | u_test/curr_state.CMD_WAITE_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.864 | 0.363 | tCL | RR | 690 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.227 | 0.363 | tNET | RR | 1 | u_test/curr_state.CMD_WAITE_s0/CLK |
| 12.827 | -0.400 | tSu | 1 | u_test/curr_state.CMD_WAITE_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
| Arrival Data Path Delay: | cell: 4.874, 59.350%; route: 2.880, 35.069%; tC2Q: 0.458, 5.581% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |