Project Settings Project Name fpga_project Device Name rev_1: GOWIN-GW2A : GW2A_18 Implementation Name rev_1 Top Module [auto] Pipelining 1 Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 Clock Conversion 1 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 10 1 0 - 00m:01s - 2021/2/8 10:16:20 (premap) Complete 6 2 0 0m:02s 0m:02s 240MB 2021/2/8 10:16:25 (fpga_mapper) Complete 13 8 0 0m:07s 0m:08s 268MB 2021/2/8 10:16:33 Multi-srs Generator Complete 00m:01s 2021/2/8 10:16:22 Area Summary I/O ports (io_port) 206 Non I/O Register bits (non_io_reg) 723 (4%) I/O Register bits (total_io_reg) 0 Ultra Rams 0 Block Rams (v_ram) 0 (46) Block Multipliers (dsp_used) 0 (24) LUTs (total_luts) 965 (4%) Timing Summary Clock Name Req Freq Est Freq Slack apsram_init|read_calibration[0]_VALUE_derived_clock[0] 0.1 MHz NA NA apsram_init|read_calibration[1]_VALUE_derived_clock[1] 0.1 MHz NA NA apsram_top|clk_out_inferred_clock 211.1 MHz 179.4 MHz -0.836 apsram_top|clk_x2_inferred_clock 150.0 MHz NA NA apsram_top|clk_x2p_inferred_clock 150.0 MHz NA NA psram_memory_interface_top|clk_d 265.5 MHz 225.7 MHz -0.665 System 1489.6 MHz 1266.1 MHz -0.118 Optimizations Summary Combined Clock Conversion 4 / 2