@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG346 :"D:\GOWIN_refdesign\apsram32M_refdesign\project\fpga_project\src\apsram_core.v":1656:34:1656:42|Read full_case directive.
@N: CG347 :"D:\GOWIN_refdesign\apsram32M_refdesign\project\fpga_project\src\apsram_core.v":1656:44:1656:56|Read a parallel_case directive.
@N: CG364 :"D:\GOWIN_refdesign\apsram32M_refdesign\project\fpga_project\src\APSRAM_TOP.v":5:8:5:33|Synthesizing module psram_memory_interface_top in library work.
@N|Running in 64-bit mode
@N: NF107 :"d:\gowin_refdesign\apsram32m_refdesign\project\fpga_project\src\apsram_top.v":5:8:5:33|Selected library: work cell: psram_memory_interface_top view verilog as top level
@N: NF107 :"d:\gowin_refdesign\apsram32m_refdesign\project\fpga_project\src\apsram_top.v":5:8:5:33|Selected library: work cell: psram_memory_interface_top view verilog as top level

