Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_1ch_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_1ch_Refdesign\project\fpga_project\src\a.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_1ch_Refdesign\project\fpga_project\src\fpga_project.sdc
GOWIN version	V1.9.7.02Beta
Part Number	GW1NR-LV9MG100PAC7/I6
Device	GW1NR-9C
Created Time	Tue Mar 09 17:16:05 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C
Hold Delay Model	Fast 1.26V 0C
Numbers of Paths Analyzed	5564
Numbers of Endpoints Analyzed	4502
Numbers of Falling Endpoints	1
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	20.000	50.000	0.000	10.000			clk
clk_x1	Base	14.286	69.999	0.000	7.143			clk_x1
clk_x2	Base	7.143	139.997	0.000	3.571			u_psram_memory_interface_top/u_apsram_top/clk_x2
your_instance_name/rpll_inst/CLKOUT.default_gen_clk	Generated	6.250	160.000	0.000	3.125	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUT
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Generated	6.250	160.000	1.563	4.688	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTP
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk	Generated	25.000	40.000	0.000	12.500	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTD
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Generated	18.750	53.333	0.000	9.375	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk_x1	69.999(MHz)	169.978(MHz)	4	TOP
2	your_instance_name/rpll_inst/CLKOUTD.default_gen_clk	40.000(MHz)	139.090(MHz)	4	TOP

No timing paths to get frequency of clk!

No timing paths to get frequency of clk_x2!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
clk_x1	Setup	0.000	0
clk_x1	Hold	0.000	0
clk_x2	Setup	0.000	0
clk_x2	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.170	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1/D	clk_x2:[R]	clk_x1:[R]	7.143	-0.181	6.827
2	0.544	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0/CE	clk_x2:[R]	clk_x1:[R]	7.143	-0.181	6.718
3	0.544	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0/CE	clk_x2:[R]	clk_x1:[R]	7.143	-0.181	6.718
4	0.544	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0/CE	clk_x2:[R]	clk_x1:[R]	7.143	-0.181	6.718
5	0.544	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0/CE	clk_x2:[R]	clk_x1:[R]	7.143	-0.181	6.718
6	1.148	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_5_s0/CE	clk_x2:[R]	clk_x1:[R]	7.143	-0.181	6.114
7	1.148	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_6_s0/CE	clk_x2:[R]	clk_x1:[R]	7.143	-0.181	6.114
8	1.148	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_7_s0/CE	clk_x2:[R]	clk_x1:[R]	7.143	-0.181	6.114
9	1.148	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_8_s0/CE	clk_x2:[R]	clk_x1:[R]	7.143	-0.181	6.114
10	1.829	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CE	your_instance_name/rpll_inst/CLKOUTD.default_gen_clk:[R]	your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[F]	3.125	0.138	0.941
11	3.085	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/curr_state.CMD_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.905
12	3.313	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[2].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.722
13	3.313	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[1].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.722
14	3.428	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[0].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.607
15	3.549	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[5].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.486
16	3.549	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[4].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.486
17	3.550	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[4].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.485
18	3.554	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[3].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.481
19	3.675	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.360
20	3.677	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[6].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.358
21	3.677	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[5].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.358
22	3.798	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[7].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.237
23	3.916	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[6].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.119
24	3.935	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/curr_state.WRITE_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	14.286	0.000	10.055
25	4.030	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[0].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	7.143	0.078	3.005

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.412	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CE	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.423
2	0.524	u_test/cyc_cnt_1_s3/Q	u_test/cyc_cnt_1_s3/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
3	0.524	u_test/WR_CNT_7_s3/Q	u_test/WR_CNT_7_s3/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
4	0.524	u_test/check_data_29_s1/Q	u_test/check_data_29_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
5	0.524	u_test/wr_data_add_72_s1/Q	u_test/wr_data_add_72_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
6	0.524	u_test/wr_data_add_90_s1/Q	u_test/wr_data_add_90_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
7	0.524	u_test/wr_data_add_121_s1/Q	u_test/wr_data_add_121_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
8	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
9	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_2_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_2_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
10	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
11	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
12	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_6_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_6_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
13	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_5_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_5_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
14	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
15	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_12_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_12_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
16	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_14_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_14_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
17	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].add_cnt_1_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].add_cnt_1_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
18	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
19	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
20	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
21	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
22	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/LA_cnt_2_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/LA_cnt_2_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
23	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_6_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_6_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
24	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_8_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_8_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524
25	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/LA_cnt_1_s3/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/LA_cnt_1_s3/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_127_s0
2	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_111_s0
3	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_103_s0
4	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_99_s0
5	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_97_s0
6	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_96_s0
7	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/rd_data_d_32_s0
8	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dq_25_s0
9	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/dqstx1_s0
10	6.159	7.085	0.926	Low Pulse Width	clk_x1	u_test/addr_12_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.170
Data Arrival Time	13.970
Data Required Time	14.140
From	u_psram_memory_interface_top/u_apsram_top/u_dll
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1
Launch Clk	clk_x2:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	8	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN
7.666	0.420	tINS	RF	1	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0]
10.186	2.520	tNET	FF	2	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1
10.593	0.408	tINS	FR	1	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT
10.593	0.000	tNET	RR	2	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN
10.635	0.042	tINS	RF	1	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT
10.635	0.000	tNET	FF	2	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN
10.678	0.042	tINS	FF	1	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT
10.678	0.000	tNET	FF	2	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN
10.720	0.042	tINS	FF	1	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT
10.720	0.000	tNET	FF	2	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN
10.762	0.042	tINS	FF	1	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT
10.762	0.000	tNET	FF	2	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN
10.804	0.042	tINS	FF	1	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT
10.804	0.000	tNET	FF	2	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN
10.847	0.042	tINS	FF	1	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT
10.847	0.000	tNET	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN
10.889	0.042	tINS	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT
13.361	2.472	tNET	FF	1	R12C14[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n761_s3/I1
13.970	0.609	tINS	FF	1	R12C14[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n761_s3/F
13.970	0.000	tNET	FF	1	R12C14[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R12C14[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1/CLK
14.437	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1
14.140	-0.296	tSu		1	R12C14[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1

Path Statistics:

Clock Skew	0.181
Setup Relationship	7.143
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.732, 25.367%; route: 4.992, 73.125%; tC2Q: 0.103, 1.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path2

Path Summary:

Slack	0.544
Data Arrival Time	13.861
Data Required Time	14.405
From	u_psram_memory_interface_top/u_apsram_top/u_dll
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0
Launch Clk	clk_x2:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	8	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN
7.666	0.420	tINS	RF	1	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0]
10.186	2.520	tNET	FF	2	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1
10.593	0.408	tINS	FR	1	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT
10.593	0.000	tNET	RR	2	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN
10.635	0.042	tINS	RF	1	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT
10.635	0.000	tNET	FF	2	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN
10.678	0.042	tINS	FF	1	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT
10.678	0.000	tNET	FF	2	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN
10.720	0.042	tINS	FF	1	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT
10.720	0.000	tNET	FF	2	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN
10.762	0.042	tINS	FF	1	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT
10.762	0.000	tNET	FF	2	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN
10.804	0.042	tINS	FF	1	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT
10.804	0.000	tNET	FF	2	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN
10.847	0.042	tINS	FF	1	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT
10.847	0.000	tNET	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN
10.889	0.042	tINS	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT
12.265	1.376	tNET	FF	1	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0
12.728	0.463	tINS	FR	8	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F
13.861	1.132	tNET	RR	1	R13C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0/CLK
14.437	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0
14.405	-0.032	tSu		1	R13C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0

Path Statistics:

Clock Skew	0.181
Setup Relationship	7.143
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.586, 23.609%; route: 5.029, 74.859%; tC2Q: 0.103, 1.533%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path3

Path Summary:

Slack	0.544
Data Arrival Time	13.861
Data Required Time	14.405
From	u_psram_memory_interface_top/u_apsram_top/u_dll
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0
Launch Clk	clk_x2:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	8	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN
7.666	0.420	tINS	RF	1	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0]
10.186	2.520	tNET	FF	2	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1
10.593	0.408	tINS	FR	1	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT
10.593	0.000	tNET	RR	2	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN
10.635	0.042	tINS	RF	1	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT
10.635	0.000	tNET	FF	2	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN
10.678	0.042	tINS	FF	1	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT
10.678	0.000	tNET	FF	2	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN
10.720	0.042	tINS	FF	1	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT
10.720	0.000	tNET	FF	2	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN
10.762	0.042	tINS	FF	1	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT
10.762	0.000	tNET	FF	2	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN
10.804	0.042	tINS	FF	1	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT
10.804	0.000	tNET	FF	2	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN
10.847	0.042	tINS	FF	1	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT
10.847	0.000	tNET	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN
10.889	0.042	tINS	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT
12.265	1.376	tNET	FF	1	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0
12.728	0.463	tINS	FR	8	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F
13.861	1.132	tNET	RR	1	R13C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0/CLK
14.437	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0
14.405	-0.032	tSu		1	R13C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0

Path Statistics:

Clock Skew	0.181
Setup Relationship	7.143
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.586, 23.609%; route: 5.029, 74.859%; tC2Q: 0.103, 1.533%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path4

Path Summary:

Slack	0.544
Data Arrival Time	13.861
Data Required Time	14.405
From	u_psram_memory_interface_top/u_apsram_top/u_dll
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0
Launch Clk	clk_x2:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	8	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN
7.666	0.420	tINS	RF	1	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0]
10.186	2.520	tNET	FF	2	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1
10.593	0.408	tINS	FR	1	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT
10.593	0.000	tNET	RR	2	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN
10.635	0.042	tINS	RF	1	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT
10.635	0.000	tNET	FF	2	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN
10.678	0.042	tINS	FF	1	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT
10.678	0.000	tNET	FF	2	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN
10.720	0.042	tINS	FF	1	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT
10.720	0.000	tNET	FF	2	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN
10.762	0.042	tINS	FF	1	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT
10.762	0.000	tNET	FF	2	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN
10.804	0.042	tINS	FF	1	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT
10.804	0.000	tNET	FF	2	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN
10.847	0.042	tINS	FF	1	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT
10.847	0.000	tNET	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN
10.889	0.042	tINS	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT
12.265	1.376	tNET	FF	1	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0
12.728	0.463	tINS	FR	8	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F
13.861	1.132	tNET	RR	1	R13C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0/CLK
14.437	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0
14.405	-0.032	tSu		1	R13C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0

Path Statistics:

Clock Skew	0.181
Setup Relationship	7.143
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.586, 23.609%; route: 5.029, 74.859%; tC2Q: 0.103, 1.533%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path5

Path Summary:

Slack	0.544
Data Arrival Time	13.861
Data Required Time	14.405
From	u_psram_memory_interface_top/u_apsram_top/u_dll
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0
Launch Clk	clk_x2:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	8	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN
7.666	0.420	tINS	RF	1	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0]
10.186	2.520	tNET	FF	2	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1
10.593	0.408	tINS	FR	1	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT
10.593	0.000	tNET	RR	2	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN
10.635	0.042	tINS	RF	1	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT
10.635	0.000	tNET	FF	2	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN
10.678	0.042	tINS	FF	1	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT
10.678	0.000	tNET	FF	2	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN
10.720	0.042	tINS	FF	1	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT
10.720	0.000	tNET	FF	2	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN
10.762	0.042	tINS	FF	1	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT
10.762	0.000	tNET	FF	2	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN
10.804	0.042	tINS	FF	1	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT
10.804	0.000	tNET	FF	2	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN
10.847	0.042	tINS	FF	1	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT
10.847	0.000	tNET	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN
10.889	0.042	tINS	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT
12.265	1.376	tNET	FF	1	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0
12.728	0.463	tINS	FR	8	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F
13.861	1.132	tNET	RR	1	R13C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0/CLK
14.437	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0
14.405	-0.032	tSu		1	R13C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0

Path Statistics:

Clock Skew	0.181
Setup Relationship	7.143
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.586, 23.609%; route: 5.029, 74.859%; tC2Q: 0.103, 1.533%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path6

Path Summary:

Slack	1.148
Data Arrival Time	13.257
Data Required Time	14.405
From	u_psram_memory_interface_top/u_apsram_top/u_dll
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_5_s0
Launch Clk	clk_x2:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	8	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN
7.666	0.420	tINS	RF	1	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0]
10.186	2.520	tNET	FF	2	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1
10.593	0.408	tINS	FR	1	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT
10.593	0.000	tNET	RR	2	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN
10.635	0.042	tINS	RF	1	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT
10.635	0.000	tNET	FF	2	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN
10.678	0.042	tINS	FF	1	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT
10.678	0.000	tNET	FF	2	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN
10.720	0.042	tINS	FF	1	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT
10.720	0.000	tNET	FF	2	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN
10.762	0.042	tINS	FF	1	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT
10.762	0.000	tNET	FF	2	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN
10.804	0.042	tINS	FF	1	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT
10.804	0.000	tNET	FF	2	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN
10.847	0.042	tINS	FF	1	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT
10.847	0.000	tNET	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN
10.889	0.042	tINS	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT
12.265	1.376	tNET	FF	1	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0
12.728	0.463	tINS	FR	8	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F
13.257	0.528	tNET	RR	1	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_5_s0/CLK
14.437	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_5_s0
14.405	-0.032	tSu		1	R13C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_5_s0

Path Statistics:

Clock Skew	0.181
Setup Relationship	7.143
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.586, 25.941%; route: 4.425, 72.375%; tC2Q: 0.103, 1.684%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path7

Path Summary:

Slack	1.148
Data Arrival Time	13.257
Data Required Time	14.405
From	u_psram_memory_interface_top/u_apsram_top/u_dll
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_6_s0
Launch Clk	clk_x2:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	8	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN
7.666	0.420	tINS	RF	1	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0]
10.186	2.520	tNET	FF	2	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1
10.593	0.408	tINS	FR	1	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT
10.593	0.000	tNET	RR	2	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN
10.635	0.042	tINS	RF	1	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT
10.635	0.000	tNET	FF	2	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN
10.678	0.042	tINS	FF	1	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT
10.678	0.000	tNET	FF	2	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN
10.720	0.042	tINS	FF	1	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT
10.720	0.000	tNET	FF	2	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN
10.762	0.042	tINS	FF	1	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT
10.762	0.000	tNET	FF	2	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN
10.804	0.042	tINS	FF	1	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT
10.804	0.000	tNET	FF	2	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN
10.847	0.042	tINS	FF	1	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT
10.847	0.000	tNET	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN
10.889	0.042	tINS	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT
12.265	1.376	tNET	FF	1	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0
12.728	0.463	tINS	FR	8	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F
13.257	0.528	tNET	RR	1	R13C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_6_s0/CLK
14.437	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_6_s0
14.405	-0.032	tSu		1	R13C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_6_s0

Path Statistics:

Clock Skew	0.181
Setup Relationship	7.143
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.586, 25.941%; route: 4.425, 72.375%; tC2Q: 0.103, 1.684%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path8

Path Summary:

Slack	1.148
Data Arrival Time	13.257
Data Required Time	14.405
From	u_psram_memory_interface_top/u_apsram_top/u_dll
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_7_s0
Launch Clk	clk_x2:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	8	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN
7.666	0.420	tINS	RF	1	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0]
10.186	2.520	tNET	FF	2	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1
10.593	0.408	tINS	FR	1	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT
10.593	0.000	tNET	RR	2	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN
10.635	0.042	tINS	RF	1	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT
10.635	0.000	tNET	FF	2	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN
10.678	0.042	tINS	FF	1	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT
10.678	0.000	tNET	FF	2	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN
10.720	0.042	tINS	FF	1	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT
10.720	0.000	tNET	FF	2	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN
10.762	0.042	tINS	FF	1	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT
10.762	0.000	tNET	FF	2	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN
10.804	0.042	tINS	FF	1	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT
10.804	0.000	tNET	FF	2	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN
10.847	0.042	tINS	FF	1	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT
10.847	0.000	tNET	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN
10.889	0.042	tINS	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT
12.265	1.376	tNET	FF	1	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0
12.728	0.463	tINS	FR	8	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F
13.257	0.528	tNET	RR	1	R13C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_7_s0/CLK
14.437	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_7_s0
14.405	-0.032	tSu		1	R13C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_7_s0

Path Statistics:

Clock Skew	0.181
Setup Relationship	7.143
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.586, 25.941%; route: 4.425, 72.375%; tC2Q: 0.103, 1.684%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path9

Path Summary:

Slack	1.148
Data Arrival Time	13.257
Data Required Time	14.405
From	u_psram_memory_interface_top/u_apsram_top/u_dll
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_8_s0
Launch Clk	clk_x2:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	8	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN
7.666	0.420	tINS	RF	1	DLL_TL	u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0]
10.186	2.520	tNET	FF	2	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1
10.593	0.408	tINS	FR	1	R16C26[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT
10.593	0.000	tNET	RR	2	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN
10.635	0.042	tINS	RF	1	R16C26[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT
10.635	0.000	tNET	FF	2	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN
10.678	0.042	tINS	FF	1	R16C26[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT
10.678	0.000	tNET	FF	2	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN
10.720	0.042	tINS	FF	1	R16C26[2][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT
10.720	0.000	tNET	FF	2	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN
10.762	0.042	tINS	FF	1	R16C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT
10.762	0.000	tNET	FF	2	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN
10.804	0.042	tINS	FF	1	R16C27[0][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT
10.804	0.000	tNET	FF	2	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN
10.847	0.042	tINS	FF	1	R16C27[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT
10.847	0.000	tNET	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN
10.889	0.042	tINS	FF	2	R16C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT
12.265	1.376	tNET	FF	1	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0
12.728	0.463	tINS	FR	8	R13C26[3][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F
13.257	0.528	tNET	RR	1	R13C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_8_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R13C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_8_s0/CLK
14.437	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_8_s0
14.405	-0.032	tSu		1	R13C27[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_8_s0

Path Statistics:

Clock Skew	0.181
Setup Relationship	7.143
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.586, 25.941%; route: 4.425, 72.375%; tC2Q: 0.103, 1.684%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path10

Path Summary:

Slack	1.829
Data Arrival Time	2.309
Data Required Time	4.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0
To	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2
Launch Clk	your_instance_name/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk	your_instance_name/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/rpll_inst/CLKOUTD.default_gen_clk
1.187	1.187	tCL	RR	31	PLL_R	your_instance_name/rpll_inst/CLKOUTD
1.368	0.181	tNET	RR	1	R18C46[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/CLK
1.708	0.340	tC2Q	RF	8	R18C46[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/Q
2.309	0.601	tNET	FF	1	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.125	3.125					active clock edge time
3.125	0.000					your_instance_name/rpll_inst/CLKOUT.default_gen_clk
4.355	1.230	tCL	FF	1	PLL_R	your_instance_name/rpll_inst/CLKOUT
4.355	0.000	tNET	FF	3	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN
4.325	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2
4.137	-0.188	tSu		1	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2

Path Statistics:

Clock Skew	-0.138
Setup Relationship	3.125
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.601, 63.896%; tC2Q: 0.340, 36.104%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack	3.085
Data Arrival Time	11.086
Data Required Time	14.170
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/curr_state.CMD_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R18C7[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	227	R18C7[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.200	2.680	tNET	FF	1	R17C27[3][B]	u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/I0
4.015	0.814	tINS	FF	9	R17C27[3][B]	u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/F
5.337	1.322	tNET	FF	1	R18C38[0][A]	u_test/next_state.IDLE_s16/I0
6.151	0.814	tINS	FF	2	R18C38[0][A]	u_test/next_state.IDLE_s16/F
6.159	0.008	tNET	FF	1	R18C38[2][B]	u_test/next_state.CYC_DONE_s14/I2
6.623	0.464	tINS	FF	3	R18C38[2][B]	u_test/next_state.CYC_DONE_s14/F
7.586	0.963	tNET	FF	1	R21C40[2][A]	u_test/next_state.CMD_WAITE_s12/I3
8.400	0.814	tINS	FF	2	R21C40[2][A]	u_test/next_state.CMD_WAITE_s12/F
10.321	1.921	tNET	FF	1	R21C19[0][A]	u_test/next_state.CMD_WAITE_s11/I0
11.086	0.765	tINS	FF	1	R21C19[0][A]	u_test/next_state.CMD_WAITE_s11/F
11.086	0.000	tNET	FF	1	R21C19[0][A]	u_test/curr_state.CMD_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R21C19[0][A]	u_test/curr_state.CMD_WAITE_s0/CLK
14.170	-0.296	tSu		1	R21C19[0][A]	u_test/curr_state.CMD_WAITE_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.672, 33.670%; route: 6.894, 63.216%; tC2Q: 0.340, 3.114%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path12

Path Summary:

Slack	3.313
Data Arrival Time	3.902
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[2].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/CLK
0.520	0.340	tC2Q	RF	12	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q
3.902	3.382	tNET	FF	1	IOR26[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[2].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR26[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[2].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[2].u_ides4
7.216	0.000	tSu		1	IOR26[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.382, 90.875%; tC2Q: 0.340, 9.125%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path13

Path Summary:

Slack	3.313
Data Arrival Time	3.902
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[1].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/CLK
0.520	0.340	tC2Q	RF	12	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q
3.902	3.382	tNET	FF	1	IOR26[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[1].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR26[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[1].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[1].u_ides4
7.216	0.000	tSu		1	IOR26[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[1].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.382, 90.875%; tC2Q: 0.340, 9.125%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path14

Path Summary:

Slack	3.428
Data Arrival Time	3.788
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[0].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/CLK
0.520	0.340	tC2Q	RF	12	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q
3.788	3.268	tNET	FF	1	IOR27[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[0].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR27[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[0].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[0].u_ides4
7.216	0.000	tSu		1	IOR27[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[0].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.268, 90.585%; tC2Q: 0.340, 9.415%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path15

Path Summary:

Slack	3.549
Data Arrival Time	3.667
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[5].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R12C13[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/CLK
0.520	0.340	tC2Q	RF	12	R12C13[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q
3.667	3.146	tNET	FF	1	IOR6[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[5].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR6[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[5].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[5].u_ides4
7.216	0.000	tSu		1	IOR6[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.146, 90.257%; tC2Q: 0.340, 9.743%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path16

Path Summary:

Slack	3.549
Data Arrival Time	3.667
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[4].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R12C13[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/CLK
0.520	0.340	tC2Q	RF	12	R12C13[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q
3.667	3.146	tNET	FF	1	IOR6[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[4].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR6[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[4].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[4].u_ides4
7.216	0.000	tSu		1	IOR6[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.146, 90.257%; tC2Q: 0.340, 9.743%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path17

Path Summary:

Slack	3.550
Data Arrival Time	3.666
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[4].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/CLK
0.520	0.340	tC2Q	RF	12	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q
3.666	3.146	tNET	FF	1	IOR21[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[4].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR21[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[4].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[4].u_ides4
7.216	0.000	tSu		1	IOR21[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.146, 90.256%; tC2Q: 0.340, 9.744%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path18

Path Summary:

Slack	3.554
Data Arrival Time	3.662
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[3].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/CLK
0.520	0.340	tC2Q	RF	12	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q
3.662	3.141	tNET	FF	1	IOR25[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[3].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR25[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[3].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[3].u_ides4
7.216	0.000	tSu		1	IOR25[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.141, 90.243%; tC2Q: 0.340, 9.757%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path19

Path Summary:

Slack	3.675
Data Arrival Time	3.541
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R12C13[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/CLK
0.520	0.340	tC2Q	RF	12	R12C13[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q
3.541	3.020	tNET	FF	1	IOR3[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR3[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4
7.216	0.000	tSu		1	IOR3[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.020, 89.892%; tC2Q: 0.340, 10.108%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path20

Path Summary:

Slack	3.677
Data Arrival Time	3.539
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[6].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/CLK
0.520	0.340	tC2Q	RF	12	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q
3.539	3.019	tNET	FF	1	IOR20[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[6].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR20[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[6].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[6].u_ides4
7.216	0.000	tSu		1	IOR20[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.019, 89.886%; tC2Q: 0.340, 10.113%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path21

Path Summary:

Slack	3.677
Data Arrival Time	3.539
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[5].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/CLK
0.520	0.340	tC2Q	RF	12	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q
3.539	3.019	tNET	FF	1	IOR20[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[5].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR20[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[5].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[5].u_ides4
7.216	0.000	tSu		1	IOR20[B]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.019, 89.886%; tC2Q: 0.340, 10.113%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path22

Path Summary:

Slack	3.798
Data Arrival Time	3.418
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[7].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/CLK
0.520	0.340	tC2Q	RF	12	R15C13[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_3_s0/Q
3.418	2.898	tNET	FF	1	IOR18[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[7].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR18[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[7].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[7].u_ides4
7.216	0.000	tSu		1	IOR18[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.898, 89.509%; tC2Q: 0.340, 10.491%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path23

Path Summary:

Slack	3.916
Data Arrival Time	3.300
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[6].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R12C13[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/CLK
0.520	0.340	tC2Q	RF	12	R12C13[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q
3.300	2.779	tNET	FF	1	IOR4[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[6].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR4[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[6].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[6].u_ides4
7.216	0.000	tSu		1	IOR4[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.779, 89.110%; tC2Q: 0.340, 10.890%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Path24

Path Summary:

Slack	3.935
Data Arrival Time	10.235
Data Required Time	14.170
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/curr_state.WRITE_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R18C7[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	227	R18C7[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.200	2.680	tNET	FF	1	R17C27[3][B]	u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/I0
4.015	0.814	tINS	FF	9	R17C27[3][B]	u_psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/F
5.597	1.583	tNET	FF	1	R18C40[3][B]	u_test/next_state.WRITE_BURST_s11/I2
6.206	0.609	tINS	FF	3	R18C40[3][B]	u_test/next_state.WRITE_BURST_s11/F
8.858	2.651	tNET	FF	1	R21C19[2][B]	u_test/next_state.WRITE_WAITE_s12/I3
9.467	0.609	tINS	FF	1	R21C19[2][B]	u_test/next_state.WRITE_WAITE_s12/F
9.471	0.004	tNET	FF	1	R21C19[0][B]	u_test/next_state.WRITE_WAITE_s10/I0
10.235	0.765	tINS	FF	1	R21C19[0][B]	u_test/next_state.WRITE_WAITE_s10/F
10.235	0.000	tNET	FF	1	R21C19[0][B]	u_test/curr_state.WRITE_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
14.286	14.286					active clock edge time
14.286	0.000					clk_x1
14.286	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.467	0.181	tNET	RR	1	R21C19[0][B]	u_test/curr_state.WRITE_WAITE_s0/CLK
14.170	-0.296	tSu		1	R21C19[0][B]	u_test/curr_state.WRITE_WAITE_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	14.286
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.797, 27.821%; route: 6.918, 68.802%; tC2Q: 0.340, 3.378%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path25

Path Summary:

Slack	4.030
Data Arrival Time	3.186
Data Required Time	7.216
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[0].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R12C13[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/CLK
0.520	0.340	tC2Q	RF	12	R12C13[1][B]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/calib_2_s0/Q
3.186	2.665	tNET	FF	1	IOR14[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[0].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.143	7.143					active clock edge time
7.143	0.000					clk_x2
7.143	0.000	tCL	RR	82	-	u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
7.246	0.103	tNET	RR	1	IOR14[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[0].u_ides4/FCLK
7.216	-0.030	tUnc				u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[0].u_ides4
7.216	0.000	tSu		1	IOR14[A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/iserdes_gen[0].u_ides4

Path Statistics:

Clock Skew	-0.078
Setup Relationship	7.143
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.665, 88.697%; tC2Q: 0.340, 11.303%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.103, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.412
Data Arrival Time	0.560
Data Required Time	0.148
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C7[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.384	0.247	tC2Q	RR	2	R18C7[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q
0.560	0.176	tNET	RR	1	R18C7[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C7[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.148	0.011	tHld		1	R18C7[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path2

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/cyc_cnt_1_s3
To	u_test/cyc_cnt_1_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C38[0][A]	u_test/cyc_cnt_1_s3/CLK
0.384	0.247	tC2Q	RR	5	R12C38[0][A]	u_test/cyc_cnt_1_s3/Q
0.386	0.002	tNET	RR	1	R12C38[0][A]	u_test/n2139_s3/I2
0.661	0.276	tINS	RF	1	R12C38[0][A]	u_test/n2139_s3/F
0.661	0.000	tNET	FF	1	R12C38[0][A]	u_test/cyc_cnt_1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C38[0][A]	u_test/cyc_cnt_1_s3/CLK
0.137	0.000	tHld		1	R12C38[0][A]	u_test/cyc_cnt_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path3

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/WR_CNT_7_s3
To	u_test/WR_CNT_7_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R23C18[0][A]	u_test/WR_CNT_7_s3/CLK
0.384	0.247	tC2Q	RR	5	R23C18[0][A]	u_test/WR_CNT_7_s3/Q
0.386	0.002	tNET	RR	1	R23C18[0][A]	u_test/n149_s5/I0
0.661	0.276	tINS	RF	1	R23C18[0][A]	u_test/n149_s5/F
0.661	0.000	tNET	FF	1	R23C18[0][A]	u_test/WR_CNT_7_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R23C18[0][A]	u_test/WR_CNT_7_s3/CLK
0.137	0.000	tHld		1	R23C18[0][A]	u_test/WR_CNT_7_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path4

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/check_data_29_s1
To	u_test/check_data_29_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C41[1][A]	u_test/check_data_29_s1/CLK
0.384	0.247	tC2Q	RR	3	R9C41[1][A]	u_test/check_data_29_s1/Q
0.386	0.002	tNET	RR	1	R9C41[1][A]	u_test/n2280_s1/I3
0.661	0.276	tINS	RF	1	R9C41[1][A]	u_test/n2280_s1/F
0.661	0.000	tNET	FF	1	R9C41[1][A]	u_test/check_data_29_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C41[1][A]	u_test/check_data_29_s1/CLK
0.137	0.000	tHld		1	R9C41[1][A]	u_test/check_data_29_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path5

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_72_s1
To	u_test/wr_data_add_72_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R20C36[0][A]	u_test/wr_data_add_72_s1/CLK
0.384	0.247	tC2Q	RR	3	R20C36[0][A]	u_test/wr_data_add_72_s1/Q
0.386	0.002	tNET	RR	1	R20C36[0][A]	u_test/n962_s1/I2
0.661	0.276	tINS	RF	1	R20C36[0][A]	u_test/n962_s1/F
0.661	0.000	tNET	FF	1	R20C36[0][A]	u_test/wr_data_add_72_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R20C36[0][A]	u_test/wr_data_add_72_s1/CLK
0.137	0.000	tHld		1	R20C36[0][A]	u_test/wr_data_add_72_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path6

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_90_s1
To	u_test/wr_data_add_90_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C36[0][A]	u_test/wr_data_add_90_s1/CLK
0.384	0.247	tC2Q	RR	4	R9C36[0][A]	u_test/wr_data_add_90_s1/Q
0.386	0.002	tNET	RR	1	R9C36[0][A]	u_test/n944_s1/I2
0.661	0.276	tINS	RF	1	R9C36[0][A]	u_test/n944_s1/F
0.661	0.000	tNET	FF	1	R9C36[0][A]	u_test/wr_data_add_90_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C36[0][A]	u_test/wr_data_add_90_s1/CLK
0.137	0.000	tHld		1	R9C36[0][A]	u_test/wr_data_add_90_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path7

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_121_s1
To	u_test/wr_data_add_121_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C34[1][A]	u_test/wr_data_add_121_s1/CLK
0.384	0.247	tC2Q	RR	3	R15C34[1][A]	u_test/wr_data_add_121_s1/Q
0.386	0.002	tNET	RR	1	R15C34[1][A]	u_test/n913_s1/I2
0.661	0.276	tINS	RF	1	R15C34[1][A]	u_test/n913_s1/F
0.661	0.000	tNET	FF	1	R15C34[1][A]	u_test/wr_data_add_121_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C34[1][A]	u_test/wr_data_add_121_s1/CLK
0.137	0.000	tHld		1	R15C34[1][A]	u_test/wr_data_add_121_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path8

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R7C14[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/CLK
0.384	0.247	tC2Q	RR	4	R7C14[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/Q
0.386	0.002	tNET	RR	1	R7C14[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2278_s3/I2
0.661	0.276	tINS	RF	1	R7C14[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2278_s3/F
0.661	0.000	tNET	FF	1	R7C14[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R7C14[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/CLK
0.137	0.000	tHld		1	R7C14[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path9

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_2_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_2_s1/CLK
0.384	0.247	tC2Q	RR	4	R11C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_2_s1/Q
0.386	0.002	tNET	RR	1	R11C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3886_s3/I1
0.661	0.276	tINS	RF	1	R11C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3886_s3/F
0.661	0.000	tNET	FF	1	R11C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_2_s1/CLK
0.137	0.000	tHld		1	R11C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path10

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C6[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/CLK
0.384	0.247	tC2Q	RR	4	R12C6[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/Q
0.386	0.002	tNET	RR	1	R12C6[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2494_s3/I1
0.661	0.276	tINS	RF	1	R12C6[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2494_s3/F
0.661	0.000	tNET	FF	1	R12C6[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C6[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/CLK
0.137	0.000	tHld		1	R12C6[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path11

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R8C14[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/CLK
0.384	0.247	tC2Q	RR	3	R8C14[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/Q
0.386	0.002	tNET	RR	1	R8C14[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2274_s1/I3
0.661	0.276	tINS	RF	1	R8C14[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2274_s1/F
0.661	0.000	tNET	FF	1	R8C14[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R8C14[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/CLK
0.137	0.000	tHld		1	R8C14[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path12

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_6_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_6_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C9[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_6_s1/CLK
0.384	0.247	tC2Q	RR	3	R11C9[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_6_s1/Q
0.386	0.002	tNET	RR	1	R11C9[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2193_s1/I3
0.661	0.276	tINS	RF	1	R11C9[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2193_s1/F
0.661	0.000	tNET	FF	1	R11C9[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C9[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_6_s1/CLK
0.137	0.000	tHld		1	R11C9[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path13

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_5_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_5_s1/CLK
0.384	0.247	tC2Q	RR	3	R16C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_5_s1/Q
0.386	0.002	tNET	RR	1	R16C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n577_s1/I3
0.661	0.276	tINS	RF	1	R16C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n577_s1/F
0.661	0.000	tNET	FF	1	R16C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_5_s1/CLK
0.137	0.000	tHld		1	R16C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path14

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/CLK
0.384	0.247	tC2Q	RR	2	R17C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/Q
0.386	0.002	tNET	RR	1	R17C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n576_s1/I3
0.661	0.276	tINS	RF	1	R17C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n576_s1/F
0.661	0.000	tNET	FF	1	R17C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/CLK
0.137	0.000	tHld		1	R17C10[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path15

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_12_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_12_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_12_s1/CLK
0.384	0.247	tC2Q	RR	3	R9C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_12_s1/Q
0.386	0.002	tNET	RR	1	R9C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n441_s1/I3
0.661	0.276	tINS	RF	1	R9C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n441_s1/F
0.661	0.000	tNET	FF	1	R9C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_12_s1/CLK
0.137	0.000	tHld		1	R9C15[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_12_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path16

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_14_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_14_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C15[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_14_s1/CLK
0.384	0.247	tC2Q	RR	3	R9C15[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_14_s1/Q
0.386	0.002	tNET	RR	1	R9C15[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n439_s3/I0
0.661	0.276	tINS	RF	1	R9C15[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n439_s3/F
0.661	0.000	tNET	FF	1	R9C15[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_14_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C15[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_14_s1/CLK
0.137	0.000	tHld		1	R9C15[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_14_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path17

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].add_cnt_1_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].add_cnt_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C8[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].add_cnt_1_s0/CLK
0.384	0.247	tC2Q	RR	3	R13C8[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].add_cnt_1_s0/Q
0.386	0.002	tNET	RR	1	R13C8[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3287_s1/I1
0.661	0.276	tINS	RF	1	R13C8[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n3287_s1/F
0.661	0.000	tNET	FF	1	R13C8[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].add_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C8[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].add_cnt_1_s0/CLK
0.137	0.000	tHld		1	R13C8[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].add_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path18

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/CLK
0.384	0.247	tC2Q	RR	3	R14C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/Q
0.386	0.002	tNET	RR	1	R14C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2823_s1/I1
0.661	0.276	tINS	RF	1	R14C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2823_s1/F
0.661	0.000	tNET	FF	1	R14C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0/CLK
0.137	0.000	tHld		1	R14C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].add_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path19

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C6[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/CLK
0.384	0.247	tC2Q	RR	2	R16C6[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/Q
0.386	0.002	tNET	RR	1	R16C6[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2358_s1/I2
0.661	0.276	tINS	RF	1	R16C6[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2358_s1/F
0.661	0.000	tNET	FF	1	R16C6[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C6[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/CLK
0.137	0.000	tHld		1	R16C6[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path20

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C7[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.384	0.247	tC2Q	RR	2	R18C7[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q
0.386	0.002	tNET	RR	1	R18C7[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_DONE_s27/I1
0.661	0.276	tINS	RF	1	R18C7[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_DONE_s27/F
0.661	0.000	tNET	FF	1	R18C7[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C7[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.137	0.000	tHld		1	R18C7[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path21

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/CLK
0.384	0.247	tC2Q	RR	2	R18C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/Q
0.386	0.002	tNET	RR	1	R18C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_WAITE_s27/I3
0.661	0.276	tINS	RF	1	R18C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_WAITE_s27/F
0.661	0.000	tNET	FF	1	R18C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0/CLK
0.137	0.000	tHld		1	R18C8[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_WAITE_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path22

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/LA_cnt_2_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/LA_cnt_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C31[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/LA_cnt_2_s1/CLK
0.384	0.247	tC2Q	RR	2	R15C31[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/LA_cnt_2_s1/Q
0.386	0.002	tNET	RR	1	R15C31[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/n395_s1/I3
0.661	0.276	tINS	RF	1	R15C31[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/n395_s1/F
0.661	0.000	tNET	FF	1	R15C31[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/LA_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C31[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/LA_cnt_2_s1/CLK
0.137	0.000	tHld		1	R15C31[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/LA_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path23

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_6_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_6_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C32[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_6_s1/CLK
0.384	0.247	tC2Q	RR	3	R16C32[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_6_s1/Q
0.386	0.002	tNET	RR	1	R16C32[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/n281_s1/I3
0.661	0.276	tINS	RF	1	R16C32[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/n281_s1/F
0.661	0.000	tNET	FF	1	R16C32[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C32[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_6_s1/CLK
0.137	0.000	tHld		1	R16C32[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path24

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_8_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_8_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C32[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_8_s1/CLK
0.384	0.247	tC2Q	RR	3	R15C32[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_8_s1/Q
0.386	0.002	tNET	RR	1	R15C32[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/n279_s1/I3
0.661	0.276	tINS	RF	1	R15C32[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/n279_s1/F
0.661	0.000	tNET	FF	1	R15C32[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C32[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_8_s1/CLK
0.137	0.000	tHld		1	R15C32[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[3].u_psram_lane/burst_cnt_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path25

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/LA_cnt_1_s3
To	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/LA_cnt_1_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C28[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/LA_cnt_1_s3/CLK
0.384	0.247	tC2Q	RR	3	R11C28[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/LA_cnt_1_s3/Q
0.386	0.002	tNET	RR	1	R11C28[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/n396_s3/I1
0.661	0.276	tINS	RF	1	R11C28[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/n396_s3/F
0.661	0.000	tNET	FF	1	R11C28[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/LA_cnt_1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1567	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C28[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/LA_cnt_1_s3/CLK
0.137	0.000	tHld		1	R11C28[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/LA_cnt_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_127_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_127_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_127_s0/CLK

MPW2

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_111_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_111_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_111_s0/CLK

MPW3

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_103_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_103_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_103_s0/CLK

MPW4

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_99_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_99_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_99_s0/CLK

MPW5

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_97_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_97_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_97_s0/CLK

MPW6

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_96_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_96_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_96_s0/CLK

MPW7

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/rd_data_d_32_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/rd_data_d_32_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/rd_data_d_32_s0/CLK

MPW8

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dq_25_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dq_25_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dq_25_s0/CLK

MPW9

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/dqstx1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/dqstx1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[2].u_psram_lane/dqstx1_s0/CLK

MPW10

MPW Summary:

Slack:	6.159
Actual Width:	7.085
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_test/addr_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
7.143	0.000			active clock edge time
7.143	0.000			clk_x1
7.143	0.000	tCL	FF	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
7.338	0.195	tNET	FF	u_test/addr_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
14.286	0.000			active clock edge time
14.286	0.000			clk_x1
14.286	0.000	tCL	RR	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
14.423	0.137	tNET	RR	u_test/addr_12_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
1567	clk_x1	3.085	0.195
282	curr_state.WRITE_BURST	6.278	2.438
227	init_calib_d	3.085	4.614
152	config_done_Z	8.735	3.009
150	wr_data_127_11	6.265	2.556
129	rd_data_valid_d0	6.318	3.188
127	wr_data_add_127_10	7.660	2.562
82	clk_x2	0.170	0.296
74	wr_data_d0_0_5	11.994	1.647
66	n2516_3	6.341	1.989

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R16C9	62.50%
R21C13	59.72%
R14C26	58.33%
R17C31	58.33%
R20C13	56.94%
R14C39	55.56%
R16C8	55.56%
R22C30	54.17%
R13C22	54.17%
R15C30	54.17%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name clk_x1 -period 14.286 -waveform {0 7.143} [get_nets {clk_x1}]
TC_CLOCK	Actived	create_clock -name clk_x2 -period 7.143 -waveform {0 3.571} [get_nets {u_psram_memory_interface_top/u_apsram_top/clk_x2}]