Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_1ch_Refdesign\project\fpga_project\src\apsram_syn_top.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_1ch_Refdesign\project\fpga_project\src\apsram_test.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_1ch_Refdesign\project\fpga_project\src\gowin_rpll\gowin_rpll.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_1ch_Refdesign\project\fpga_project\src\uhs_psram_memory_interface\uhs_psram_memory_interface.v |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
| Part Number | GW1NR-LV9MG100PAC7/I6 |
| Device | GW1NR-9C |
| Created Time | Tue Mar 09 17:15:57 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | syn_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.676s, Peak memory usage = 270.613MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 270.613MB Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 270.613MB Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.108s, Peak memory usage = 270.613MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 270.613MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 270.613MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 270.613MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 270.613MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 270.613MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.119s, Peak memory usage = 270.613MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 270.613MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 270.613MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.206s, Peak memory usage = 270.613MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 270.613MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 270.613MB |
Resource
Resource Usage Summary
| I/O Port | 4 |
| Emedded Port | 52 |
| I/O Buf | 52 |
| IBUF | 2 |
| OBUF | 6 |
| TBUF | 4 |
| IOBUF | 36 |
| ELVDS_OBUF | 4 |
| Register | 1482 |
| DFF | 1 |
| DFFP | 9 |
| DFFPE | 12 |
| DFFC | 710 |
| DFFCE | 750 |
| LUT | 2335 |
| LUT2 | 705 |
| LUT3 | 632 |
| LUT4 | 998 |
| ALU | 155 |
| ALU | 155 |
| SSRAM | 36 |
| RAM16S4 | 36 |
| INV | 29 |
| INV | 29 |
| IOLOGIC | 120 |
| IDES4 | 32 |
| OSER4 | 48 |
| IODELAY | 40 |
| CLOCK | 4 |
| DLL | 1 |
| CLKDIV | 1 |
| DHCEN | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Logic | 2735(2364 LUTs, 155 ALUs, 36 SSRAMs) / 8640 | 32% |
| Register | 1482 / 6900 | 21% |
| --Register as Latch | 0 / 6900 | 0% |
| --Register as FF | 1482 / 6900 | 21% |
| BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
| your_instance_name/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.250 | 160.0 | 0.000 | 3.125 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUT |
| your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.250 | 160.0 | 1.563 | 4.688 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTP |
| your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | Generated | 25.000 | 40.0 | 0.000 | 12.500 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD |
| your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 18.750 | 53.3 | 0.000 | 9.375 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD3 |
| u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | your_instance_name/rpll_inst/CLKOUT | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | 40.0(MHz) | 176.3(MHz) | 5 | TOP |
| 2 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | 80.0(MHz) | 287.3(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.067 |
| Data Arrival Time | 11.645 |
| Data Required Time | 12.712 |
| From | u_psram_memory_interface_top/u_apsram_top/u_dll |
| To | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 7.552 | 1.302 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 7.821 | 0.269 | tNET | RR | 3 | u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 8.005 | 0.184 | tINS | RR | 82 | u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT |
| 8.274 | 0.269 | tNET | RR | 8 | u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN |
| 8.694 | 0.420 | tINS | RF | 1 | u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0] |
| 9.050 | 0.356 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1 |
| 9.824 | 0.774 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT |
| 9.824 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN |
| 9.866 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT |
| 9.866 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN |
| 9.908 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT |
| 9.908 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN |
| 9.951 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT |
| 9.951 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN |
| 9.993 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT |
| 9.993 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN |
| 10.035 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT |
| 10.035 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN |
| 10.077 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT |
| 10.077 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN |
| 10.120 | 0.042 | tINS | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT |
| 10.475 | 0.356 | tNET | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n761_s3/I1 |
| 11.290 | 0.814 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n761_s3/F |
| 11.645 | 0.356 | tNET | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.769 | 0.269 | tCL | RR | 1567 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.038 | 0.269 | tNET | RR | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1/CLK |
| 13.008 | -0.030 | tUnc | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1 | ||
| 12.712 | -0.296 | tSu | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1 |
| Clock Skew: | -1.217 |
| Setup Relationship: | 6.250 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.184, 40.607%; route: 0.269, 59.393% |
| Arrival Data Path Delay: | cell: 2.304, 63.296%; route: 1.067, 29.314%; tC2Q: 0.269, 7.390% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Path 2
Path Summary:| Slack | 1.472 |
| Data Arrival Time | 11.505 |
| Data Required Time | 12.976 |
| From | u_psram_memory_interface_top/u_apsram_top/u_dll |
| To | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 7.552 | 1.302 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 7.821 | 0.269 | tNET | RR | 3 | u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 8.005 | 0.184 | tINS | RR | 82 | u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT |
| 8.274 | 0.269 | tNET | RR | 8 | u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN |
| 8.694 | 0.420 | tINS | RF | 1 | u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0] |
| 9.050 | 0.356 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1 |
| 9.824 | 0.774 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT |
| 9.824 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN |
| 9.866 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT |
| 9.866 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN |
| 9.908 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT |
| 9.908 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN |
| 9.951 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT |
| 9.951 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN |
| 9.993 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT |
| 9.993 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN |
| 10.035 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT |
| 10.035 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN |
| 10.077 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT |
| 10.077 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN |
| 10.120 | 0.042 | tINS | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT |
| 10.475 | 0.356 | tNET | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0 |
| 11.236 | 0.760 | tINS | FR | 8 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F |
| 11.505 | 0.269 | tNET | RR | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.769 | 0.269 | tCL | RR | 1567 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.038 | 0.269 | tNET | RR | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0/CLK |
| 13.008 | -0.030 | tUnc | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0 | ||
| 12.976 | -0.032 | tSu | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0 |
| Clock Skew: | -1.217 |
| Setup Relationship: | 6.250 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.184, 40.607%; route: 0.269, 59.393% |
| Arrival Data Path Delay: | cell: 2.250, 64.297%; route: 0.980, 28.016%; tC2Q: 0.269, 7.687% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Path 3
Path Summary:| Slack | 1.472 |
| Data Arrival Time | 11.505 |
| Data Required Time | 12.976 |
| From | u_psram_memory_interface_top/u_apsram_top/u_dll |
| To | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 7.552 | 1.302 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 7.821 | 0.269 | tNET | RR | 3 | u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 8.005 | 0.184 | tINS | RR | 82 | u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT |
| 8.274 | 0.269 | tNET | RR | 8 | u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN |
| 8.694 | 0.420 | tINS | RF | 1 | u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0] |
| 9.050 | 0.356 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1 |
| 9.824 | 0.774 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT |
| 9.824 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN |
| 9.866 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT |
| 9.866 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN |
| 9.908 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT |
| 9.908 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN |
| 9.951 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT |
| 9.951 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN |
| 9.993 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT |
| 9.993 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN |
| 10.035 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT |
| 10.035 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN |
| 10.077 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT |
| 10.077 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN |
| 10.120 | 0.042 | tINS | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT |
| 10.475 | 0.356 | tNET | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0 |
| 11.236 | 0.760 | tINS | FR | 8 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F |
| 11.505 | 0.269 | tNET | RR | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.769 | 0.269 | tCL | RR | 1567 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.038 | 0.269 | tNET | RR | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0/CLK |
| 13.008 | -0.030 | tUnc | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0 | ||
| 12.976 | -0.032 | tSu | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0 |
| Clock Skew: | -1.217 |
| Setup Relationship: | 6.250 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.184, 40.607%; route: 0.269, 59.393% |
| Arrival Data Path Delay: | cell: 2.250, 64.297%; route: 0.980, 28.016%; tC2Q: 0.269, 7.687% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Path 4
Path Summary:| Slack | 1.472 |
| Data Arrival Time | 11.505 |
| Data Required Time | 12.976 |
| From | u_psram_memory_interface_top/u_apsram_top/u_dll |
| To | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 7.552 | 1.302 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 7.821 | 0.269 | tNET | RR | 3 | u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 8.005 | 0.184 | tINS | RR | 82 | u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT |
| 8.274 | 0.269 | tNET | RR | 8 | u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN |
| 8.694 | 0.420 | tINS | RF | 1 | u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0] |
| 9.050 | 0.356 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1 |
| 9.824 | 0.774 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT |
| 9.824 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN |
| 9.866 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT |
| 9.866 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN |
| 9.908 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT |
| 9.908 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN |
| 9.951 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT |
| 9.951 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN |
| 9.993 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT |
| 9.993 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN |
| 10.035 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT |
| 10.035 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN |
| 10.077 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT |
| 10.077 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN |
| 10.120 | 0.042 | tINS | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT |
| 10.475 | 0.356 | tNET | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0 |
| 11.236 | 0.760 | tINS | FR | 8 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F |
| 11.505 | 0.269 | tNET | RR | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.769 | 0.269 | tCL | RR | 1567 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.038 | 0.269 | tNET | RR | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0/CLK |
| 13.008 | -0.030 | tUnc | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0 | ||
| 12.976 | -0.032 | tSu | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0 |
| Clock Skew: | -1.217 |
| Setup Relationship: | 6.250 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.184, 40.607%; route: 0.269, 59.393% |
| Arrival Data Path Delay: | cell: 2.250, 64.297%; route: 0.980, 28.016%; tC2Q: 0.269, 7.687% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Path 5
Path Summary:| Slack | 1.472 |
| Data Arrival Time | 11.505 |
| Data Required Time | 12.976 |
| From | u_psram_memory_interface_top/u_apsram_top/u_dll |
| To | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 7.552 | 1.302 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 7.821 | 0.269 | tNET | RR | 3 | u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 8.005 | 0.184 | tINS | RR | 82 | u_psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT |
| 8.274 | 0.269 | tNET | RR | 8 | u_psram_memory_interface_top/u_apsram_top/u_dll/CLKIN |
| 8.694 | 0.420 | tINS | RF | 1 | u_psram_memory_interface_top/u_apsram_top/u_dll/STEP[0] |
| 9.050 | 0.356 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/I1 |
| 9.824 | 0.774 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s19/COUT |
| 9.824 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/CIN |
| 9.866 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s20/COUT |
| 9.866 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/CIN |
| 9.908 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s21/COUT |
| 9.908 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/CIN |
| 9.951 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s22/COUT |
| 9.951 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/CIN |
| 9.993 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s23/COUT |
| 9.993 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/CIN |
| 10.035 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s24/COUT |
| 10.035 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/CIN |
| 10.077 | 0.042 | tINS | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s25/COUT |
| 10.077 | 0.000 | tNET | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/CIN |
| 10.120 | 0.042 | tINS | FF | 2 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n751_s26/COUT |
| 10.475 | 0.356 | tNET | FF | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/I0 |
| 11.236 | 0.760 | tINS | FR | 8 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/n845_s1/F |
| 11.505 | 0.269 | tNET | RR | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.769 | 0.269 | tCL | RR | 1567 | u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.038 | 0.269 | tNET | RR | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0/CLK |
| 13.008 | -0.030 | tUnc | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0 | ||
| 12.976 | -0.032 | tSu | 1 | u_psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0 |
| Clock Skew: | -1.217 |
| Setup Relationship: | 6.250 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.184, 40.607%; route: 0.269, 59.393% |
| Arrival Data Path Delay: | cell: 2.250, 64.297%; route: 0.980, 28.016%; tC2Q: 0.269, 7.687% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |