Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\UHS_PSRAM_1\data\PSRAM_256_TOP.v
C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\UHS_PSRAM_1\data\apsram_256_code.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9C
Created Time Tue Mar 09 17:06:48 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module UHS_PSRAM_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 39.949MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 39.949MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 39.949MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 39.949MB
    Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 39.949MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 39.949MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.949MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 39.949MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 39.949MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 39.949MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 39.949MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 39.949MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 55.047MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.16s, Peak memory usage = 55.047MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 55.047MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 55.047MB

Resource

Resource Usage Summary

I/O Port 125
I/O Buf 125
    IBUF 78
    OBUF 38
    IOBUF 9
Register 420
    DFFP 5
    DFFPE 3
    DFFC 231
    DFFCE 181
LUT 688
    LUT2 167
    LUT3 261
    LUT4 260
ALU 42
    ALU 42
INV 9
    INV 9
IOLOGIC 28
    IDES4 8
    OSER4 11
    IODELAY 9
BSRAM 1
    SDPX9B 1
CLOCK 3
    DLL 1
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Logic 739(697 LUTs, 42 ALUs) / 8640 9%
Register 420 / 6693 6%
  --Register as Latch 0 / 6693 0%
  --Register as FF 420 / 6693 6%
BSRAM 1 / 26 4%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
u_apsram_top/clkdiv/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 memory_clk_ibuf/I memory_clk u_apsram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 130.6(MHz) 5 TOP
2 u_apsram_top/clkdiv/CLKOUT.default_gen_clk 50.0(MHz) 212.9(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.346
Data Arrival Time 8.599
Data Required Time 10.945
From u_apsram_top/u_psram_sync/cs_memsync_2_s0
To u_apsram_top/u_psram_sync/cs_memsync_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_2_s0/CLK
1.803 0.458 tC2Q RF 8 u_apsram_top/u_psram_sync/cs_memsync_2_s0/Q
2.283 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s16/I1
3.382 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n282_s16/F
3.862 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s15/I1
4.961 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n282_s15/F
5.441 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s13/I1
6.540 1.099 tINS FF 5 u_apsram_top/u_psram_sync/n282_s13/F
7.020 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n337_s12/I1
8.119 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n337_s12/F
8.599 0.480 tNET FF 1 u_apsram_top/u_psram_sync/cs_memsync_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 31 clk_ibuf/O
11.345 0.363 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_0_s0/CLK
10.945 -0.400 tSu 1 u_apsram_top/u_psram_sync/cs_memsync_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.396, 60.598%; route: 2.400, 33.084%; tC2Q: 0.458, 6.318%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 2.413
Data Arrival Time 8.532
Data Required Time 10.945
From u_apsram_top/u_psram_sync/cs_memsync_2_s0
To u_apsram_top/u_psram_sync/cs_memsync_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_2_s0/CLK
1.803 0.458 tC2Q RF 8 u_apsram_top/u_psram_sync/cs_memsync_2_s0/Q
2.283 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s16/I1
3.382 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n282_s16/F
3.862 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s15/I1
4.961 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n282_s15/F
5.441 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s13/I1
6.540 1.099 tINS FF 5 u_apsram_top/u_psram_sync/n282_s13/F
7.020 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n315_s12/I0
8.052 1.032 tINS FF 1 u_apsram_top/u_psram_sync/n315_s12/F
8.532 0.480 tNET FF 1 u_apsram_top/u_psram_sync/cs_memsync_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 31 clk_ibuf/O
11.345 0.363 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_2_s0/CLK
10.945 -0.400 tSu 1 u_apsram_top/u_psram_sync/cs_memsync_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 2.413
Data Arrival Time 8.532
Data Required Time 10.945
From u_apsram_top/u_psram_sync/cs_memsync_2_s0
To u_apsram_top/u_psram_sync/cs_memsync_3_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_2_s0/CLK
1.803 0.458 tC2Q RF 8 u_apsram_top/u_psram_sync/cs_memsync_2_s0/Q
2.283 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s16/I1
3.382 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n282_s16/F
3.862 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s15/I1
4.961 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n282_s15/F
5.441 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s13/I1
6.540 1.099 tINS FF 5 u_apsram_top/u_psram_sync/n282_s13/F
7.020 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n304_s12/I0
8.052 1.032 tINS FF 1 u_apsram_top/u_psram_sync/n304_s12/F
8.532 0.480 tNET FF 1 u_apsram_top/u_psram_sync/cs_memsync_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 31 clk_ibuf/O
11.345 0.363 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
10.945 -0.400 tSu 1 u_apsram_top/u_psram_sync/cs_memsync_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 2.413
Data Arrival Time 8.532
Data Required Time 10.945
From u_apsram_top/u_psram_sync/cs_memsync_2_s0
To u_apsram_top/u_psram_sync/cs_memsync_4_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_2_s0/CLK
1.803 0.458 tC2Q RF 8 u_apsram_top/u_psram_sync/cs_memsync_2_s0/Q
2.283 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s16/I1
3.382 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n282_s16/F
3.862 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s15/I1
4.961 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n282_s15/F
5.441 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s13/I1
6.540 1.099 tINS FF 5 u_apsram_top/u_psram_sync/n282_s13/F
7.020 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n293_s12/I0
8.052 1.032 tINS FF 1 u_apsram_top/u_psram_sync/n293_s12/F
8.532 0.480 tNET FF 1 u_apsram_top/u_psram_sync/cs_memsync_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 31 clk_ibuf/O
11.345 0.363 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_4_s0/CLK
10.945 -0.400 tSu 1 u_apsram_top/u_psram_sync/cs_memsync_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 2.413
Data Arrival Time 8.532
Data Required Time 10.945
From u_apsram_top/u_psram_sync/cs_memsync_2_s0
To u_apsram_top/u_psram_sync/cs_memsync_5_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_2_s0/CLK
1.803 0.458 tC2Q RF 8 u_apsram_top/u_psram_sync/cs_memsync_2_s0/Q
2.283 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s16/I1
3.382 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n282_s16/F
3.862 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s15/I1
4.961 1.099 tINS FF 1 u_apsram_top/u_psram_sync/n282_s15/F
5.441 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s13/I1
6.540 1.099 tINS FF 5 u_apsram_top/u_psram_sync/n282_s13/F
7.020 0.480 tNET FF 1 u_apsram_top/u_psram_sync/n282_s12/I0
8.052 1.032 tINS FF 1 u_apsram_top/u_psram_sync/n282_s12/F
8.532 0.480 tNET FF 1 u_apsram_top/u_psram_sync/cs_memsync_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 31 clk_ibuf/O
11.345 0.363 tNET RR 1 u_apsram_top/u_psram_sync/cs_memsync_5_s0/CLK
10.945 -0.400 tSu 1 u_apsram_top/u_psram_sync/cs_memsync_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%