Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\a.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\fpga_project.sdc
GOWIN version	V1.9.7.02Beta
Part Number	GW1NR-LV9QN88PC6/I5
Device	GW1NR-9C
Created Time	Tue Mar 09 17:34:21 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C
Hold Delay Model	Fast 1.26V 0C
Numbers of Paths Analyzed	2082
Numbers of Endpoints Analyzed	2041
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	16.667	59.999	0.000	8.334			clk
clk_x1	Base	16.667	59.999	0.000	8.334			clk_x1
clk_x2	Base	8.333	120.005	0.000	4.167			memory_clk
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Generated	2.500	399.992	0.625	1.875	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTP
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk	Generated	5.000	199.996	0.000	2.500	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTD
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Generated	7.500	133.331	0.000	3.750	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	59.999(MHz)	104.108(MHz)	5	TOP
2	clk_x1	59.999(MHz)	85.881(MHz)	6	TOP

No timing paths to get frequency of clk_x2!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
clk_x1	Setup	0.000	0
clk_x1	Hold	0.000	0
clk_x2	Setup	0.000	0
clk_x2	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	4.921	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	8.333	-0.145	3.527
2	5.023	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/curr_state.READ_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	11.244
3	5.023	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/curr_state.CMD_WAITE_s0/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	11.244
4	5.064	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/curr_state.WRITE_BURST_s0/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	11.203
5	5.076	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_15_s1/CE	clk_x1:[R]	clk_x1:[R]	16.667	0.000	11.547
6	5.367	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	8.333	-0.145	3.081
7	5.382	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	8.333	-0.145	3.066
8	5.382	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	8.333	-0.145	3.066
9	5.424	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/Full_s0/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.843
10	5.475	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_28_s1/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.792
11	5.507	u_test/check_data_17_s1/Q	u_test/error_d_s0/CE	clk_x1:[R]	clk_x1:[R]	16.667	0.000	11.117
12	5.537	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	8.333	-0.145	2.911
13	5.582	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_18_s1/CE	clk_x1:[R]	clk_x1:[R]	16.667	0.000	11.041
14	5.623	u_test/burst_rnum_0_s3/Q	u_test/curr_state.IDLE_s0/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.644
15	5.631	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_44_s1/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.636
16	5.631	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_50_s1/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.636
17	5.631	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_56_s1/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.636
18	5.662	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/curr_state.READ_BURST_s0/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.605
19	5.739	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_15_s1/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.528
20	5.768	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_24_s1/CE	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.856
21	5.798	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_26_s1/CE	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.825
22	5.841	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_48_s1/D	clk_x1:[R]	clk_x1:[R]	16.667	0.000	10.426
23	5.846	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	8.333	-0.145	2.602
24	5.846	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	8.333	-0.145	2.602
25	5.851	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB	clk_x1:[R]	clk_x2:[R]	8.333	-0.145	2.597

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.556	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CE	clk_x1:[R]	clk_x1:[R]	0.571
2	0.708	button/cnt_0_s0/Q	button/cnt_0_s0/D	clk:[R]	clk:[R]	0.708
3	0.708	u_test/check_data_54_s1/Q	u_test/check_data_54_s1/D	clk_x1:[R]	clk_x1:[R]	0.708
4	0.708	u_test/check_data_58_s1/Q	u_test/check_data_58_s1/D	clk_x1:[R]	clk_x1:[R]	0.708
5	0.708	u_test/check_data_60_s1/Q	u_test/check_data_60_s1/D	clk_x1:[R]	clk_x1:[R]	0.708
6	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_4_s3/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_4_s3/D	clk_x1:[R]	clk_x1:[R]	0.708
7	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_1_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_1_s1/D	clk_x1:[R]	clk_x1:[R]	0.708
8	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/D	clk_x1:[R]	clk_x1:[R]	0.708
9	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/D	clk_x1:[R]	clk_x1:[R]	0.708
10	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_3_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_3_s1/D	clk_x1:[R]	clk_x1:[R]	0.708
11	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_3_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_3_s1/D	clk_x1:[R]	clk_x1:[R]	0.708
12	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/D	clk_x1:[R]	clk_x1:[R]	0.708
13	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/D	clk_x1:[R]	clk_x1:[R]	0.708
14	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/D	clk_x1:[R]	clk_x1:[R]	0.708
15	0.708	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/D	clk_x1:[R]	clk_x1:[R]	0.708
16	0.709	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1/D	clk:[R]	clk:[R]	0.709
17	0.709	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1/D	clk:[R]	clk:[R]	0.709
18	0.709	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/D	clk:[R]	clk:[R]	0.709
19	0.709	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/D	clk:[R]	clk:[R]	0.709
20	0.709	u_test/cyc_cnt_0_s3/Q	u_test/cyc_cnt_0_s3/D	clk_x1:[R]	clk_x1:[R]	0.709
21	0.709	u_test/wr_data_add_0_s3/Q	u_test/wr_data_add_0_s3/D	clk_x1:[R]	clk_x1:[R]	0.709
22	0.709	u_test/check_data_4_s1/Q	u_test/check_data_4_s1/D	clk_x1:[R]	clk_x1:[R]	0.709
23	0.709	u_test/check_data_7_s1/Q	u_test/check_data_7_s1/D	clk_x1:[R]	clk_x1:[R]	0.709
24	0.709	u_test/check_data_14_s1/Q	u_test/check_data_14_s1/D	clk_x1:[R]	clk_x1:[R]	0.709
25	0.709	u_test/check_data_15_s1/Q	u_test/check_data_15_s1/D	clk_x1:[R]	clk_x1:[R]	0.709

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	7.736	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_10_s1/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.722
2	7.736	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_11_s1/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.722
3	7.736	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_12_s1/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.722
4	7.736	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_3_s1/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.722
5	7.736	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].wr_ptr_0_s1/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.722
6	7.736	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CONFIG_MR8_WAITE_s0/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.722
7	7.755	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_init/MR_cnt_0_s1/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.702
8	7.755	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_1_s0/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.702
9	7.755	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_3_s0/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.702
10	7.755	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cmdr_done_s1/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.702
11	7.755	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/dqtx1_s0/CLEAR	clk:[R]	clk_x1:[R]	16.667	2.136	6.702
12	8.409	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/mem_mem_0_0_s/RESETB	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
13	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
14	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
15	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
16	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
17	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
18	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
19	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
20	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
21	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
22	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
23	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[6].dq_oser4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
24	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887
25	8.569	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[4].dq_oser4/RESET	clk:[R]	clk_x1:[R]	16.667	2.136	5.887

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_0_s3/CLEAR	clk:[R]	clk:[R]	2.857
2	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLEAR	clk:[R]	clk:[R]	2.857
3	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_3_s3/CLEAR	clk:[R]	clk:[R]	2.857
4	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_4_s3/CLEAR	clk:[R]	clk:[R]	2.857
5	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_6_s3/CLEAR	clk:[R]	clk:[R]	2.857
6	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s3/CLEAR	clk:[R]	clk:[R]	2.857
7	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_10_s3/CLEAR	clk:[R]	clk:[R]	2.857
8	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_14_s3/CLEAR	clk:[R]	clk:[R]	2.857
9	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_15_s4/CLEAR	clk:[R]	clk:[R]	2.857
10	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1/CLEAR	clk:[R]	clk:[R]	2.857
11	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_5_s1/CLEAR	clk:[R]	clk:[R]	2.857
12	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1/CLEAR	clk:[R]	clk:[R]	2.857
13	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_9_s1/CLEAR	clk:[R]	clk:[R]	2.857
14	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/CLEAR	clk:[R]	clk:[R]	2.857
15	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_12_s1/CLEAR	clk:[R]	clk:[R]	2.857
16	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/CLEAR	clk:[R]	clk:[R]	2.857
17	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_1_s0/PRESET	clk:[R]	clk:[R]	2.857
18	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_syn_1_s0/CLEAR	clk:[R]	clk:[R]	2.857
19	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_0_s0/CLEAR	clk:[R]	clk:[R]	2.857
20	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_1_s0/CLEAR	clk:[R]	clk:[R]	2.857
21	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0/CLEAR	clk:[R]	clk:[R]	2.857
22	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/flag_0_s0/CLEAR	clk:[R]	clk:[R]	2.857
23	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/flag_1_s0/CLEAR	clk:[R]	clk:[R]	2.857
24	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/dll_rst_s0/PRESET	clk:[R]	clk:[R]	2.857
25	2.842	button/out_s0/Q	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_0_s0/CLEAR	clk:[R]	clk:[R]	2.857

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.415	7.665	1.250	Low Pulse Width	clk	led_0_s1
2	6.415	7.665	1.250	Low Pulse Width	clk	button/in_reg2_s0
3	6.415	7.665	1.250	Low Pulse Width	clk	button/cnt_16_s0
4	6.415	7.665	1.250	Low Pulse Width	clk	button/cnt_8_s0
5	6.415	7.665	1.250	Low Pulse Width	clk	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_2_s0
6	6.415	7.665	1.250	Low Pulse Width	clk	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
7	6.415	7.665	1.250	Low Pulse Width	clk	button/cnt_9_s0
8	6.415	7.665	1.250	Low Pulse Width	clk	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0
9	6.415	7.665	1.250	Low Pulse Width	clk	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_5_s0
10	6.415	7.665	1.250	Low Pulse Width	clk	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_0_s3

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	4.921
Data Arrival Time	3.769
Data Required Time	8.690
From	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.700	0.458	tC2Q	RF	9	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
3.769	3.069	tNET	FF	1	IOR24[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_x2
8.333	0.000	tCL	RR	1	PLL_R	your_instance_name/rpll_inst/CLKOUT
8.333	0.000	tNET	RR	3	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN
8.581	0.248	tINS	RR	21	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
8.720	0.139	tNET	RR	1	IOR24[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/FCLK
8.690	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4
8.690	0.000	tSu		1	IOR24[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew	0.145
Setup Relationship	8.333
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.069, 87.005%; tC2Q: 0.458, 12.995%
Required Clock Path Delay	cell: 0.248, 64.110%; route: 0.139, 35.890%

Path2

Path Summary:

Slack	5.023
Data Arrival Time	11.486
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/curr_state.READ_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.653	2.952	tNET	FF	1	R16C20[3][A]	psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/I0
4.685	1.032	tINS	FF	9	R16C20[3][A]	psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/F
5.515	0.831	tNET	FF	1	R17C18[1][B]	u_test/next_state.CYC_DONE_s17/I0
6.614	1.099	tINS	FF	2	R17C18[1][B]	u_test/next_state.CYC_DONE_s17/F
6.625	0.011	tNET	FF	1	R17C18[3][A]	u_test/next_state.READ_BURST_s16/I2
7.724	1.099	tINS	FF	2	R17C18[3][A]	u_test/next_state.READ_BURST_s16/F
9.344	1.620	tNET	FF	1	R18C18[0][B]	u_test/next_state.CMD_WAITE_s15/I2
10.376	1.032	tINS	FF	2	R18C18[0][B]	u_test/next_state.CMD_WAITE_s15/F
10.387	0.011	tNET	FF	1	R18C18[0][A]	u_test/next_state.READ_WAITE_s12/I1
11.486	1.099	tINS	FF	1	R18C18[0][A]	u_test/next_state.READ_WAITE_s12/F
11.486	0.000	tNET	FF	1	R18C18[0][A]	u_test/curr_state.READ_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R18C18[0][A]	u_test/curr_state.READ_WAITE_s0/CLK
16.509	-0.400	tSu		1	R18C18[0][A]	u_test/curr_state.READ_WAITE_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 5.361, 47.679%; route: 5.425, 48.245%; tC2Q: 0.458, 4.076%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path3

Path Summary:

Slack	5.023
Data Arrival Time	11.486
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/curr_state.CMD_WAITE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.653	2.952	tNET	FF	1	R16C20[3][A]	psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/I0
4.685	1.032	tINS	FF	9	R16C20[3][A]	psram_memory_interface_top/u_apsram_top/cmd_rdy_d_s/F
5.515	0.831	tNET	FF	1	R17C18[1][B]	u_test/next_state.CYC_DONE_s17/I0
6.614	1.099	tINS	FF	2	R17C18[1][B]	u_test/next_state.CYC_DONE_s17/F
6.625	0.011	tNET	FF	1	R17C18[3][A]	u_test/next_state.READ_BURST_s16/I2
7.724	1.099	tINS	FF	2	R17C18[3][A]	u_test/next_state.READ_BURST_s16/F
9.344	1.620	tNET	FF	1	R18C18[0][B]	u_test/next_state.CMD_WAITE_s15/I2
10.376	1.032	tINS	FF	2	R18C18[0][B]	u_test/next_state.CMD_WAITE_s15/F
10.387	0.011	tNET	FF	1	R18C18[1][A]	u_test/next_state.CMD_WAITE_s13/I1
11.486	1.099	tINS	FF	1	R18C18[1][A]	u_test/next_state.CMD_WAITE_s13/F
11.486	0.000	tNET	FF	1	R18C18[1][A]	u_test/curr_state.CMD_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R18C18[1][A]	u_test/curr_state.CMD_WAITE_s0/CLK
16.509	-0.400	tSu		1	R18C18[1][A]	u_test/curr_state.CMD_WAITE_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 5.361, 47.679%; route: 5.425, 48.245%; tC2Q: 0.458, 4.076%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path4

Path Summary:

Slack	5.064
Data Arrival Time	11.445
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/curr_state.WRITE_BURST_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.543	2.843	tNET	FF	1	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.575	1.032	tINS	FF	5	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
5.567	0.992	tNET	FF	1	R18C20[2][A]	u_test/next_state.CMD_WAITE_s16/I1
6.628	1.061	tINS	FR	5	R18C20[2][A]	u_test/next_state.CMD_WAITE_s16/F
7.051	0.423	tNET	RR	1	R18C19[0][B]	u_test/next_state.WRITE_BURST_s17/I2
8.077	1.026	tINS	RR	2	R18C19[0][B]	u_test/next_state.WRITE_BURST_s17/F
8.498	0.421	tNET	RR	1	R17C19[3][B]	u_test/next_state.WRITE_BURST_s14/I3
9.124	0.626	tINS	RF	1	R17C19[3][B]	u_test/next_state.WRITE_BURST_s14/F
10.413	1.289	tNET	FF	1	R14C17[1][A]	u_test/next_state.WRITE_BURST_s12/I3
11.445	1.032	tINS	FF	1	R14C17[1][A]	u_test/next_state.WRITE_BURST_s12/F
11.445	0.000	tNET	FF	1	R14C17[1][A]	u_test/curr_state.WRITE_BURST_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R14C17[1][A]	u_test/curr_state.WRITE_BURST_s0/CLK
16.509	-0.400	tSu		1	R14C17[1][A]	u_test/curr_state.WRITE_BURST_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 4.777, 42.642%; route: 5.967, 53.267%; tC2Q: 0.458, 4.091%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack	5.076
Data Arrival Time	11.789
Data Required Time	16.866
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_15_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/CLK
0.700	0.458	tC2Q	RF	6	R13C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/Q
1.532	0.832	tNET	FF	1	R14C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s2/I1
2.631	1.099	tINS	FF	33	R14C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s2/F
5.404	2.773	tNET	FF	1	R12C35[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s0/I2
6.226	0.822	tINS	FF	7	R12C35[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s0/F
7.058	0.832	tNET	FF	1	R13C37[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1656_s1/I2
7.880	0.822	tINS	FF	8	R13C37[3][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1656_s1/F
9.207	1.326	tNET	FF	1	R15C38[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1656_s0/I1
10.268	1.061	tINS	FR	1	R15C38[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1656_s0/F
11.789	1.522	tNET	RR	1	R15C38[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_15_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R15C38[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_15_s1/CLK
16.866	-0.043	tSu		1	R15C38[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_15_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.804, 32.943%; route: 7.285, 63.088%; tC2Q: 0.458, 3.969%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack	5.367
Data Arrival Time	3.323
Data Required Time	8.690
From	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.700	0.458	tC2Q	RF	9	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
3.323	2.623	tNET	FF	1	IOB29[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_x2
8.333	0.000	tCL	RR	1	PLL_R	your_instance_name/rpll_inst/CLKOUT
8.333	0.000	tNET	RR	3	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN
8.581	0.248	tINS	RR	21	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
8.720	0.139	tNET	RR	1	IOB29[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/FCLK
8.690	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4
8.690	0.000	tSu		1	IOB29[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew	0.145
Setup Relationship	8.333
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.623, 85.126%; tC2Q: 0.458, 14.874%
Required Clock Path Delay	cell: 0.248, 64.110%; route: 0.139, 35.890%

Path7

Path Summary:

Slack	5.382
Data Arrival Time	3.308
Data Required Time	8.690
From	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.700	0.458	tC2Q	RF	9	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
3.308	2.608	tNET	FF	1	IOB41[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_x2
8.333	0.000	tCL	RR	1	PLL_R	your_instance_name/rpll_inst/CLKOUT
8.333	0.000	tNET	RR	3	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN
8.581	0.248	tINS	RR	21	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
8.720	0.139	tNET	RR	1	IOB41[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/FCLK
8.690	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4
8.690	0.000	tSu		1	IOB41[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew	0.145
Setup Relationship	8.333
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.608, 85.051%; tC2Q: 0.458, 14.949%
Required Clock Path Delay	cell: 0.248, 64.110%; route: 0.139, 35.890%

Path8

Path Summary:

Slack	5.382
Data Arrival Time	3.308
Data Required Time	8.690
From	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.700	0.458	tC2Q	RF	9	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
3.308	2.608	tNET	FF	1	IOB41[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_x2
8.333	0.000	tCL	RR	1	PLL_R	your_instance_name/rpll_inst/CLKOUT
8.333	0.000	tNET	RR	3	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN
8.581	0.248	tINS	RR	21	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
8.720	0.139	tNET	RR	1	IOB41[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/FCLK
8.690	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4
8.690	0.000	tSu		1	IOB41[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4

Path Statistics:

Clock Skew	0.145
Setup Relationship	8.333
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.608, 85.051%; tC2Q: 0.458, 14.949%
Required Clock Path Delay	cell: 0.248, 64.110%; route: 0.139, 35.890%

Path9

Path Summary:

Slack	5.424
Data Arrival Time	11.085
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/Full_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
5.775	5.075	tNET	FF	1	R21C34[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/n7_s2/I3
6.807	1.032	tINS	FF	2	R21C34[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/n7_s2/F
7.303	0.496	tNET	FF	2	R21C35[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_next_0_s/I1
7.853	0.550	tINS	FR	1	R21C35[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_next_0_s/COUT
7.853	0.000	tNET	RR	2	R21C35[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_next_1_s/CIN
7.910	0.057	tINS	RF	1	R21C35[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_next_1_s/COUT
7.910	0.000	tNET	FF	2	R21C35[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_next_2_s/CIN
7.967	0.057	tINS	FF	1	R21C35[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_next_2_s/COUT
7.967	0.000	tNET	FF	2	R21C35[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_next_3_s/CIN
8.530	0.563	tINS	FF	2	R21C35[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_next_3_s/SUM
8.541	0.011	tNET	FF	1	R21C35[3][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wfull_val_s2/I2
9.567	1.026	tINS	FR	1	R21C35[3][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wfull_val_s2/F
9.986	0.419	tNET	RR	1	R21C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wfull_val_s0/I1
11.085	1.099	tINS	RF	1	R21C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wfull_val_s0/F
11.085	0.000	tNET	FF	1	R21C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/Full_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R21C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/Full_s0/CLK
16.509	-0.400	tSu		1	R21C34[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/Full_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 4.384, 40.433%; route: 6.000, 55.339%; tC2Q: 0.458, 4.227%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path10

Path Summary:

Slack	5.475
Data Arrival Time	11.034
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_28_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.543	2.843	tNET	FF	1	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.575	1.032	tINS	FF	5	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.694	2.119	tNET	FF	1	R9C18[3][B]	u_test/next_state.IDLE_s15/I0
7.793	1.099	tINS	FF	63	R9C18[3][B]	u_test/next_state.IDLE_s15/F
10.002	2.209	tNET	FF	1	R14C23[2][A]	u_test/n1302_s1/I0
11.034	1.032	tINS	FF	1	R14C23[2][A]	u_test/n1302_s1/F
11.034	0.000	tNET	FF	1	R14C23[2][A]	u_test/check_data_28_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R14C23[2][A]	u_test/check_data_28_s1/CLK
16.509	-0.400	tSu		1	R14C23[2][A]	u_test/check_data_28_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.163, 29.309%; route: 7.170, 66.444%; tC2Q: 0.458, 4.247%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack	5.507
Data Arrival Time	11.359
Data Required Time	16.866
From	u_test/check_data_17_s1
To	u_test/error_d_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R9C18[0][B]	u_test/check_data_17_s1/CLK
0.700	0.458	tC2Q	RF	6	R9C18[0][B]	u_test/check_data_17_s1/Q
3.144	2.444	tNET	FF	1	R12C23[0][B]	u_test/n1495_s31/I0
3.946	0.802	tINS	FR	1	R12C23[0][B]	u_test/n1495_s31/F
4.365	0.419	tNET	RR	1	R13C23[0][B]	u_test/n1495_s14/I1
4.991	0.626	tINS	RF	1	R13C23[0][B]	u_test/n1495_s14/F
5.966	0.975	tNET	FF	1	R12C21[1][A]	u_test/n1495_s3/I3
7.065	1.099	tINS	FF	1	R12C21[1][A]	u_test/n1495_s3/F
7.869	0.804	tNET	FF	1	R13C22[2][B]	u_test/n1495_s0/I2
8.494	0.625	tINS	FR	1	R13C22[2][B]	u_test/n1495_s0/F
11.359	2.865	tNET	RR	1	IOR24[A]	u_test/error_d_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOR24[A]	u_test/error_d_s0/CLK
16.866	-0.043	tSu		1	IOR24[A]	u_test/error_d_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.152, 28.353%; route: 7.507, 67.524%; tC2Q: 0.458, 4.123%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack	5.537
Data Arrival Time	3.153
Data Required Time	8.690
From	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.700	0.458	tC2Q	RF	9	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
3.153	2.452	tNET	FF	1	IOB43[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_x2
8.333	0.000	tCL	RR	1	PLL_R	your_instance_name/rpll_inst/CLKOUT
8.333	0.000	tNET	RR	3	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN
8.581	0.248	tINS	RR	21	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
8.720	0.139	tNET	RR	1	IOB43[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/FCLK
8.690	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4
8.690	0.000	tSu		1	IOB43[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4

Path Statistics:

Clock Skew	0.145
Setup Relationship	8.333
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.452, 84.253%; tC2Q: 0.458, 15.747%
Required Clock Path Delay	cell: 0.248, 64.110%; route: 0.139, 35.890%

Path13

Path Summary:

Slack	5.582
Data Arrival Time	11.283
Data Required Time	16.866
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_18_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/CLK
0.700	0.458	tC2Q	RF	6	R13C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/Q
1.532	0.832	tNET	FF	1	R14C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s2/I1
2.631	1.099	tINS	FF	33	R14C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s2/F
5.404	2.773	tNET	FF	1	R12C35[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s0/I2
6.226	0.822	tINS	FF	7	R12C35[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s0/F
6.248	0.022	tNET	FF	1	R12C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n2163_s4/I0
7.347	1.099	tINS	FF	36	R12C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n2163_s4/F
8.701	1.354	tNET	FF	1	R13C38[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1653_s0/I2
9.762	1.061	tINS	FR	1	R13C38[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1653_s0/F
11.283	1.522	tNET	RR	1	R13C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_18_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R13C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_18_s1/CLK
16.866	-0.043	tSu		1	R13C38[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_18_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 4.081, 36.962%; route: 6.502, 58.887%; tC2Q: 0.458, 4.151%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack	5.623
Data Arrival Time	10.886
Data Required Time	16.509
From	u_test/burst_rnum_0_s3
To	u_test/curr_state.IDLE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R20C15[0][A]	u_test/burst_rnum_0_s3/CLK
0.700	0.458	tC2Q	RF	12	R20C15[0][A]	u_test/burst_rnum_0_s3/Q
2.351	1.651	tNET	FF	2	R17C16[1][A]	u_test/n46_s0/I1
3.396	1.045	tINS	FF	1	R17C16[1][A]	u_test/n46_s0/COUT
3.396	0.000	tNET	FF	2	R17C16[1][B]	u_test/n47_s0/CIN
3.453	0.057	tINS	FF	1	R17C16[1][B]	u_test/n47_s0/COUT
3.453	0.000	tNET	FF	2	R17C16[2][A]	u_test/n48_s0/CIN
3.510	0.057	tINS	FF	1	R17C16[2][A]	u_test/n48_s0/COUT
3.510	0.000	tNET	FF	2	R17C16[2][B]	u_test/n49_s0/CIN
3.567	0.057	tINS	FF	1	R17C16[2][B]	u_test/n49_s0/COUT
3.567	0.000	tNET	FF	2	R17C17[0][A]	u_test/n50_s0/CIN
3.624	0.057	tINS	FF	1	R17C17[0][A]	u_test/n50_s0/COUT
3.624	0.000	tNET	FF	2	R17C17[0][B]	u_test/n51_s0/CIN
3.681	0.057	tINS	FF	1	R17C17[0][B]	u_test/n51_s0/COUT
3.681	0.000	tNET	FF	2	R17C17[1][A]	u_test/n52_s0/CIN
3.738	0.057	tINS	FF	1	R17C17[1][A]	u_test/n52_s0/COUT
3.738	0.000	tNET	FF	2	R17C17[1][B]	u_test/n53_s0/CIN
3.795	0.057	tINS	FF	1	R17C17[1][B]	u_test/n53_s0/COUT
3.795	0.000	tNET	FF	2	R17C17[2][A]	u_test/n54_s0/CIN
3.852	0.057	tINS	FF	1	R17C17[2][A]	u_test/n54_s0/COUT
3.852	0.000	tNET	FF	2	R17C17[2][B]	u_test/n55_s0/CIN
3.909	0.057	tINS	FF	5	R17C17[2][B]	u_test/n55_s0/COUT
5.782	1.873	tNET	FF	1	R20C20[1][B]	u_test/next_state.CYC_DONE_s19/I0
6.408	0.626	tINS	FF	2	R20C20[1][B]	u_test/next_state.CYC_DONE_s19/F
8.683	2.274	tNET	FF	1	R14C17[0][B]	u_test/next_state.IDLE_s14/I2
9.782	1.099	tINS	FF	1	R14C17[0][B]	u_test/next_state.IDLE_s14/F
9.787	0.005	tNET	FF	1	R14C17[1][B]	u_test/next_state.IDLE_s13/I2
10.886	1.099	tINS	FF	1	R14C17[1][B]	u_test/next_state.IDLE_s13/F
10.886	0.000	tNET	FF	1	R14C17[1][B]	u_test/curr_state.IDLE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R14C17[1][B]	u_test/curr_state.IDLE_s0/CLK
16.509	-0.400	tSu		1	R14C17[1][B]	u_test/curr_state.IDLE_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 4.382, 41.168%; route: 5.804, 54.526%; tC2Q: 0.458, 4.306%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack	5.631
Data Arrival Time	10.878
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_44_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.543	2.843	tNET	FF	1	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.575	1.032	tINS	FF	5	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.694	2.119	tNET	FF	1	R9C18[3][B]	u_test/next_state.IDLE_s15/I0
7.793	1.099	tINS	FF	63	R9C18[3][B]	u_test/next_state.IDLE_s15/F
9.846	2.053	tNET	FF	1	R12C13[0][A]	u_test/n1286_s1/I2
10.878	1.032	tINS	FF	1	R12C13[0][A]	u_test/n1286_s1/F
10.878	0.000	tNET	FF	1	R12C13[0][A]	u_test/check_data_44_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R12C13[0][A]	u_test/check_data_44_s1/CLK
16.509	-0.400	tSu		1	R12C13[0][A]	u_test/check_data_44_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.163, 29.738%; route: 7.015, 65.953%; tC2Q: 0.458, 4.309%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack	5.631
Data Arrival Time	10.878
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_50_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.543	2.843	tNET	FF	1	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.575	1.032	tINS	FF	5	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.694	2.119	tNET	FF	1	R9C18[3][B]	u_test/next_state.IDLE_s15/I0
7.793	1.099	tINS	FF	63	R9C18[3][B]	u_test/next_state.IDLE_s15/F
9.846	2.053	tNET	FF	1	R12C13[1][B]	u_test/n1280_s1/I2
10.878	1.032	tINS	FF	1	R12C13[1][B]	u_test/n1280_s1/F
10.878	0.000	tNET	FF	1	R12C13[1][B]	u_test/check_data_50_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R12C13[1][B]	u_test/check_data_50_s1/CLK
16.509	-0.400	tSu		1	R12C13[1][B]	u_test/check_data_50_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.163, 29.738%; route: 7.015, 65.953%; tC2Q: 0.458, 4.309%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack	5.631
Data Arrival Time	10.878
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_56_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.543	2.843	tNET	FF	1	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.575	1.032	tINS	FF	5	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.694	2.119	tNET	FF	1	R9C18[3][B]	u_test/next_state.IDLE_s15/I0
7.793	1.099	tINS	FF	63	R9C18[3][B]	u_test/next_state.IDLE_s15/F
9.846	2.053	tNET	FF	1	R12C13[2][A]	u_test/n1274_s1/I2
10.878	1.032	tINS	FF	1	R12C13[2][A]	u_test/n1274_s1/F
10.878	0.000	tNET	FF	1	R12C13[2][A]	u_test/check_data_56_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R12C13[2][A]	u_test/check_data_56_s1/CLK
16.509	-0.400	tSu		1	R12C13[2][A]	u_test/check_data_56_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.163, 29.738%; route: 7.015, 65.953%; tC2Q: 0.458, 4.309%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack	5.662
Data Arrival Time	10.847
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/curr_state.READ_BURST_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.543	2.843	tNET	FF	1	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.575	1.032	tINS	FF	5	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
5.567	0.992	tNET	FF	1	R18C20[2][A]	u_test/next_state.CMD_WAITE_s16/I1
6.666	1.099	tINS	FF	5	R18C20[2][A]	u_test/next_state.CMD_WAITE_s16/F
7.508	0.842	tNET	FF	1	R18C18[1][B]	u_test/next_state.READ_BURST_s17/I3
8.569	1.061	tINS	FR	1	R18C18[1][B]	u_test/next_state.READ_BURST_s17/F
8.988	0.419	tNET	RR	1	R17C18[3][B]	u_test/next_state.READ_BURST_s18/I3
9.810	0.822	tINS	RF	1	R17C18[3][B]	u_test/next_state.READ_BURST_s18/F
9.815	0.005	tNET	FF	1	R17C18[2][A]	u_test/next_state.READ_BURST_s14/I0
10.847	1.032	tINS	FF	1	R17C18[2][A]	u_test/next_state.READ_BURST_s14/F
10.847	0.000	tNET	FF	1	R17C18[2][A]	u_test/curr_state.READ_BURST_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R17C18[2][A]	u_test/curr_state.READ_BURST_s0/CLK
16.509	-0.400	tSu		1	R17C18[2][A]	u_test/curr_state.READ_BURST_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 5.046, 47.581%; route: 5.101, 48.097%; tC2Q: 0.458, 4.322%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack	5.739
Data Arrival Time	10.770
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_15_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.543	2.843	tNET	FF	1	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.575	1.032	tINS	FF	5	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.694	2.119	tNET	FF	1	R9C18[3][B]	u_test/next_state.IDLE_s15/I0
7.793	1.099	tINS	FF	63	R9C18[3][B]	u_test/next_state.IDLE_s15/F
9.671	1.878	tNET	FF	1	R12C21[0][A]	u_test/n1315_s1/I0
10.770	1.099	tINS	FF	1	R12C21[0][A]	u_test/n1315_s1/F
10.770	0.000	tNET	FF	1	R12C21[0][A]	u_test/check_data_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R12C21[0][A]	u_test/check_data_15_s1/CLK
16.509	-0.400	tSu		1	R12C21[0][A]	u_test/check_data_15_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.230, 30.680%; route: 6.840, 64.967%; tC2Q: 0.458, 4.353%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack	5.768
Data Arrival Time	11.098
Data Required Time	16.866
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_24_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/CLK
0.700	0.458	tC2Q	RF	6	R13C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/Q
1.532	0.832	tNET	FF	1	R14C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s2/I1
2.631	1.099	tINS	FF	33	R14C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s2/F
5.404	2.773	tNET	FF	1	R12C35[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s0/I2
6.226	0.822	tINS	FF	7	R12C35[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s0/F
6.248	0.022	tNET	FF	1	R12C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n2163_s4/I0
7.347	1.099	tINS	FF	36	R12C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n2163_s4/F
8.216	0.869	tNET	FF	1	R13C37[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1647_s0/I2
9.242	1.026	tINS	FR	1	R13C37[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1647_s0/F
11.098	1.856	tNET	RR	1	R13C37[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_24_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R13C37[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_24_s1/CLK
16.866	-0.043	tSu		1	R13C37[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_24_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 4.046, 37.270%; route: 6.352, 58.508%; tC2Q: 0.458, 4.222%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack	5.798
Data Arrival Time	11.067
Data Required Time	16.866
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_26_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/CLK
0.700	0.458	tC2Q	RF	6	R13C30[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_0_s1/Q
1.532	0.832	tNET	FF	1	R14C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s2/I1
2.631	1.099	tINS	FF	33	R14C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s2/F
5.404	2.773	tNET	FF	1	R12C35[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s0/I2
6.226	0.822	tINS	FF	7	R12C35[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1607_s0/F
7.067	0.841	tNET	FF	1	R13C37[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1640_s1/I2
7.693	0.626	tINS	FF	8	R13C37[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1640_s1/F
8.520	0.826	tNET	FF	1	R14C37[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1645_s0/I0
9.546	1.026	tINS	FR	1	R14C37[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1645_s0/F
11.067	1.522	tNET	RR	1	R14C37[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_26_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R14C37[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_26_s1/CLK
16.866	-0.043	tSu		1	R14C37[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_26_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 3.573, 33.006%; route: 6.794, 62.760%; tC2Q: 0.458, 4.234%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack	5.841
Data Arrival Time	10.668
Data Required Time	16.509
From	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_48_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.700	0.458	tC2Q	RF	111	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
3.543	2.843	tNET	FF	1	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/I0
4.575	1.032	tINS	FF	5	R18C28[3][A]	psram_memory_interface_top/u_apsram_top/rd_data_valid_d_s1/F
6.694	2.119	tNET	FF	1	R9C18[3][B]	u_test/next_state.IDLE_s15/I0
7.793	1.099	tINS	FF	63	R9C18[3][B]	u_test/next_state.IDLE_s15/F
9.846	2.053	tNET	FF	1	R12C13[0][B]	u_test/n1282_s1/I2
10.668	0.822	tINS	FF	1	R12C13[0][B]	u_test/n1282_s1/F
10.668	0.000	tNET	FF	1	R12C13[0][B]	u_test/check_data_48_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R12C13[0][B]	u_test/check_data_48_s1/CLK
16.509	-0.400	tSu		1	R12C13[0][B]	u_test/check_data_48_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	16.667
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 2.953, 28.322%; route: 7.015, 67.282%; tC2Q: 0.458, 4.396%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack	5.846
Data Arrival Time	2.844
Data Required Time	8.690
From	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.700	0.458	tC2Q	RF	9	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
2.844	2.144	tNET	FF	1	IOB33[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_x2
8.333	0.000	tCL	RR	1	PLL_R	your_instance_name/rpll_inst/CLKOUT
8.333	0.000	tNET	RR	3	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN
8.581	0.248	tINS	RR	21	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
8.720	0.139	tNET	RR	1	IOB33[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/FCLK
8.690	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4
8.690	0.000	tSu		1	IOB33[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew	0.145
Setup Relationship	8.333
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.144, 82.386%; tC2Q: 0.458, 17.614%
Required Clock Path Delay	cell: 0.248, 64.110%; route: 0.139, 35.890%

Path24

Path Summary:

Slack	5.846
Data Arrival Time	2.844
Data Required Time	8.690
From	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.700	0.458	tC2Q	RF	9	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
2.844	2.144	tNET	FF	1	IOB33[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_x2
8.333	0.000	tCL	RR	1	PLL_R	your_instance_name/rpll_inst/CLKOUT
8.333	0.000	tNET	RR	3	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN
8.581	0.248	tINS	RR	21	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
8.720	0.139	tNET	RR	1	IOB33[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/FCLK
8.690	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4
8.690	0.000	tSu		1	IOB33[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew	0.145
Setup Relationship	8.333
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.144, 82.386%; tC2Q: 0.458, 17.614%
Required Clock Path Delay	cell: 0.248, 64.110%; route: 0.139, 35.890%

Path25

Path Summary:

Slack	5.851
Data Arrival Time	2.839
Data Required Time	8.690
From	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4
Launch Clk	clk_x1:[R]
Latch Clk	clk_x2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.242	0.242	tNET	RR	1	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/CLK
0.700	0.458	tC2Q	RF	9	R13C33[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/calib_0_s0/Q
2.839	2.139	tNET	FF	1	IOB31[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.333	8.333					active clock edge time
8.333	0.000					clk_x2
8.333	0.000	tCL	RR	1	PLL_R	your_instance_name/rpll_inst/CLKOUT
8.333	0.000	tNET	RR	3	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN
8.581	0.248	tINS	RR	21	-	psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT
8.720	0.139	tNET	RR	1	IOB31[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/FCLK
8.690	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4
8.690	0.000	tSu		1	IOB31[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew	0.145
Setup Relationship	8.333
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.139, 82.351%; tC2Q: 0.458, 17.649%
Required Clock Path Delay	cell: 0.248, 64.110%; route: 0.139, 35.890%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.556
Data Arrival Time	0.754
Data Required Time	0.198
From	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.516	0.333	tC2Q	RR	2	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q
0.754	0.238	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.198	0.015	tHld		1	R13C33[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path2

Path Summary:

Slack	0.708
Data Arrival Time	2.570
Data Required Time	1.862
From	button/cnt_0_s0
To	button/cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R11C20[0][A]	button/cnt_0_s0/CLK
2.195	0.333	tC2Q	RR	3	R11C20[0][A]	button/cnt_0_s0/Q
2.198	0.002	tNET	RR	1	R11C20[0][A]	button/n35_s2/I
2.570	0.372	tINS	RF	1	R11C20[0][A]	button/n35_s2/O
2.570	0.000	tNET	FF	1	R11C20[0][A]	button/cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R11C20[0][A]	button/cnt_0_s0/CLK
1.862	0.000	tHld		1	R11C20[0][A]	button/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path3

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	u_test/check_data_54_s1
To	u_test/check_data_54_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C17[0][A]	u_test/check_data_54_s1/CLK
0.516	0.333	tC2Q	RR	5	R12C17[0][A]	u_test/check_data_54_s1/Q
0.519	0.002	tNET	RR	1	R12C17[0][A]	u_test/n1276_s1/I3
0.891	0.372	tINS	RF	1	R12C17[0][A]	u_test/n1276_s1/F
0.891	0.000	tNET	FF	1	R12C17[0][A]	u_test/check_data_54_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C17[0][A]	u_test/check_data_54_s1/CLK
0.183	0.000	tHld		1	R12C17[0][A]	u_test/check_data_54_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path4

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	u_test/check_data_58_s1
To	u_test/check_data_58_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C23[1][A]	u_test/check_data_58_s1/CLK
0.516	0.333	tC2Q	RR	6	R13C23[1][A]	u_test/check_data_58_s1/Q
0.519	0.002	tNET	RR	1	R13C23[1][A]	u_test/n1272_s1/I3
0.891	0.372	tINS	RF	1	R13C23[1][A]	u_test/n1272_s1/F
0.891	0.000	tNET	FF	1	R13C23[1][A]	u_test/check_data_58_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C23[1][A]	u_test/check_data_58_s1/CLK
0.183	0.000	tHld		1	R13C23[1][A]	u_test/check_data_58_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path5

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	u_test/check_data_60_s1
To	u_test/check_data_60_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C14[1][A]	u_test/check_data_60_s1/CLK
0.516	0.333	tC2Q	RR	4	R12C14[1][A]	u_test/check_data_60_s1/Q
0.519	0.002	tNET	RR	1	R12C14[1][A]	u_test/n1270_s1/I3
0.891	0.372	tINS	RF	1	R12C14[1][A]	u_test/n1270_s1/F
0.891	0.000	tNET	FF	1	R12C14[1][A]	u_test/check_data_60_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C14[1][A]	u_test/check_data_60_s1/CLK
0.183	0.000	tHld		1	R12C14[1][A]	u_test/check_data_60_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path6

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_4_s3
To	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_4_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R11C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_4_s3/CLK
0.516	0.333	tC2Q	RR	4	R11C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_4_s3/Q
0.519	0.002	tNET	RR	1	R11C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n586_s4/I1
0.891	0.372	tINS	RF	1	R11C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n586_s4/F
0.891	0.000	tNET	FF	1	R11C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_4_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R11C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_4_s3/CLK
0.183	0.000	tHld		1	R11C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_4_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path7

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_1_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R14C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_1_s1/CLK
0.516	0.333	tC2Q	RR	5	R14C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_1_s1/Q
0.519	0.002	tNET	RR	1	R14C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1586_s1/I2
0.891	0.372	tINS	RF	1	R14C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1586_s1/F
0.891	0.000	tNET	FF	1	R14C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R14C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_1_s1/CLK
0.183	0.000	tHld		1	R14C30[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path8

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R14C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/CLK
0.516	0.333	tC2Q	RR	4	R14C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/Q
0.519	0.002	tNET	RR	1	R14C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1585_s1/I3
0.891	0.372	tINS	RF	1	R14C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1585_s1/F
0.891	0.000	tNET	FF	1	R14C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R14C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1/CLK
0.183	0.000	tHld		1	R14C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path9

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C28[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/CLK
0.516	0.333	tC2Q	RR	3	R12C28[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/Q
0.519	0.002	tNET	RR	1	R12C28[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1368_s1/I3
0.891	0.372	tINS	RF	1	R12C28[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1368_s1/F
0.891	0.000	tNET	FF	1	R12C28[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C28[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1/CLK
0.183	0.000	tHld		1	R12C28[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path10

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_3_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R14C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_3_s1/CLK
0.516	0.333	tC2Q	RR	3	R14C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_3_s1/Q
0.519	0.002	tNET	RR	1	R14C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1288_s1/I1
0.891	0.372	tINS	RF	1	R14C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1288_s1/F
0.891	0.000	tNET	FF	1	R14C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R14C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_3_s1/CLK
0.183	0.000	tHld		1	R14C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path11

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_3_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R9C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_3_s1/CLK
0.516	0.333	tC2Q	RR	2	R9C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_3_s1/Q
0.519	0.002	tNET	RR	1	R9C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n587_s1/I2
0.891	0.372	tINS	RF	1	R9C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n587_s1/F
0.891	0.000	tNET	FF	1	R9C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R9C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_3_s1/CLK
0.183	0.000	tHld		1	R9C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path12

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R9C32[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/CLK
0.516	0.333	tC2Q	RR	3	R9C32[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/Q
0.519	0.002	tNET	RR	1	R9C32[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n584_s1/I1
0.891	0.372	tINS	RF	1	R9C32[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n584_s1/F
0.891	0.000	tNET	FF	1	R9C32[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R9C32[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1/CLK
0.183	0.000	tHld		1	R9C32[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path13

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/CLK
0.516	0.333	tC2Q	RR	2	R15C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/Q
0.519	0.002	tNET	RR	1	R15C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n450_s1/I2
0.891	0.372	tINS	RF	1	R15C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n450_s1/F
0.891	0.000	tNET	FF	1	R15C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R15C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/CLK
0.183	0.000	tHld		1	R15C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path14

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C34[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/CLK
0.516	0.333	tC2Q	RR	2	R13C34[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/Q
0.519	0.002	tNET	RR	1	R13C34[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1449_s1/I2
0.891	0.372	tINS	RF	1	R13C34[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n1449_s1/F
0.891	0.000	tNET	FF	1	R13C34[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C34[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0/CLK
0.183	0.000	tHld		1	R13C34[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].add_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path15

Path Summary:

Slack	0.708
Data Arrival Time	0.891
Data Required Time	0.183
From	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.516	0.333	tC2Q	RR	2	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q
0.519	0.002	tNET	RR	1	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_DONE_s27/I1
0.891	0.372	tINS	RF	1	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/n_state.INIT_CALIB_DONE_s27/F
0.891	0.000	tNET	FF	1	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.183	0.000	tHld		1	R13C33[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.INIT_CALIB_DONE_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path16

Path Summary:

Slack	0.709
Data Arrival Time	2.571
Data Required Time	1.862
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C25[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1/CLK
2.195	0.333	tC2Q	RR	4	R20C25[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1/Q
2.199	0.004	tNET	RR	1	R20C25[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n49_s1/I2
2.571	0.372	tINS	RF	1	R20C25[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n49_s1/F
2.571	0.000	tNET	FF	1	R20C25[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C25[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1/CLK
1.862	0.000	tHld		1	R20C25[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path17

Path Summary:

Slack	0.709
Data Arrival Time	2.571
Data Required Time	1.862
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1/CLK
2.195	0.333	tC2Q	RR	3	R20C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1/Q
2.199	0.004	tNET	RR	1	R20C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n44_s1/I2
2.571	0.372	tINS	RF	1	R20C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n44_s1/F
2.571	0.000	tNET	FF	1	R20C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1/CLK
1.862	0.000	tHld		1	R20C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path18

Path Summary:

Slack	0.709
Data Arrival Time	2.571
Data Required Time	1.862
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C27[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/CLK
2.195	0.333	tC2Q	RR	3	R20C27[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/Q
2.199	0.004	tNET	RR	1	R20C27[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n40_s1/I2
2.571	0.372	tINS	RF	1	R20C27[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n40_s1/F
2.571	0.000	tNET	FF	1	R20C27[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C27[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/CLK
1.862	0.000	tHld		1	R20C27[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path19

Path Summary:

Slack	0.709
Data Arrival Time	2.571
Data Required Time	1.862
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R21C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/CLK
2.195	0.333	tC2Q	RR	3	R21C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/Q
2.199	0.004	tNET	RR	1	R21C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n38_s1/I2
2.571	0.372	tINS	RF	1	R21C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/n38_s1/F
2.571	0.000	tNET	FF	1	R21C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R21C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/CLK
1.862	0.000	tHld		1	R21C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path20

Path Summary:

Slack	0.709
Data Arrival Time	0.892
Data Required Time	0.183
From	u_test/cyc_cnt_0_s3
To	u_test/cyc_cnt_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R21C20[1][A]	u_test/cyc_cnt_0_s3/CLK
0.516	0.333	tC2Q	RR	6	R21C20[1][A]	u_test/cyc_cnt_0_s3/Q
0.520	0.004	tNET	RR	1	R21C20[1][A]	u_test/n1124_s3/I2
0.892	0.372	tINS	RF	1	R21C20[1][A]	u_test/n1124_s3/F
0.892	0.000	tNET	FF	1	R21C20[1][A]	u_test/cyc_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R21C20[1][A]	u_test/cyc_cnt_0_s3/CLK
0.183	0.000	tHld		1	R21C20[1][A]	u_test/cyc_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path21

Path Summary:

Slack	0.709
Data Arrival Time	0.892
Data Required Time	0.183
From	u_test/wr_data_add_0_s3
To	u_test/wr_data_add_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R20C16[1][A]	u_test/wr_data_add_0_s3/CLK
0.516	0.333	tC2Q	RR	6	R20C16[1][A]	u_test/wr_data_add_0_s3/Q
0.520	0.004	tNET	RR	1	R20C16[1][A]	u_test/n579_s3/I1
0.892	0.372	tINS	RF	1	R20C16[1][A]	u_test/n579_s3/F
0.892	0.000	tNET	FF	1	R20C16[1][A]	u_test/wr_data_add_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R20C16[1][A]	u_test/wr_data_add_0_s3/CLK
0.183	0.000	tHld		1	R20C16[1][A]	u_test/wr_data_add_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path22

Path Summary:

Slack	0.709
Data Arrival Time	0.892
Data Required Time	0.183
From	u_test/check_data_4_s1
To	u_test/check_data_4_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R11C16[0][A]	u_test/check_data_4_s1/CLK
0.516	0.333	tC2Q	RR	5	R11C16[0][A]	u_test/check_data_4_s1/Q
0.520	0.004	tNET	RR	1	R11C16[0][A]	u_test/n1326_s1/I1
0.892	0.372	tINS	RF	1	R11C16[0][A]	u_test/n1326_s1/F
0.892	0.000	tNET	FF	1	R11C16[0][A]	u_test/check_data_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R11C16[0][A]	u_test/check_data_4_s1/CLK
0.183	0.000	tHld		1	R11C16[0][A]	u_test/check_data_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path23

Path Summary:

Slack	0.709
Data Arrival Time	0.892
Data Required Time	0.183
From	u_test/check_data_7_s1
To	u_test/check_data_7_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R11C22[0][A]	u_test/check_data_7_s1/CLK
0.516	0.333	tC2Q	RR	3	R11C22[0][A]	u_test/check_data_7_s1/Q
0.520	0.004	tNET	RR	1	R11C22[0][A]	u_test/n1323_s1/I3
0.892	0.372	tINS	RF	1	R11C22[0][A]	u_test/n1323_s1/F
0.892	0.000	tNET	FF	1	R11C22[0][A]	u_test/check_data_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R11C22[0][A]	u_test/check_data_7_s1/CLK
0.183	0.000	tHld		1	R11C22[0][A]	u_test/check_data_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path24

Path Summary:

Slack	0.709
Data Arrival Time	0.892
Data Required Time	0.183
From	u_test/check_data_14_s1
To	u_test/check_data_14_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R11C22[1][A]	u_test/check_data_14_s1/CLK
0.516	0.333	tC2Q	RR	4	R11C22[1][A]	u_test/check_data_14_s1/Q
0.520	0.004	tNET	RR	1	R11C22[1][A]	u_test/n1316_s1/I3
0.892	0.372	tINS	RF	1	R11C22[1][A]	u_test/n1316_s1/F
0.892	0.000	tNET	FF	1	R11C22[1][A]	u_test/check_data_14_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R11C22[1][A]	u_test/check_data_14_s1/CLK
0.183	0.000	tHld		1	R11C22[1][A]	u_test/check_data_14_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path25

Path Summary:

Slack	0.709
Data Arrival Time	0.892
Data Required Time	0.183
From	u_test/check_data_15_s1
To	u_test/check_data_15_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C21[0][A]	u_test/check_data_15_s1/CLK
0.516	0.333	tC2Q	RR	4	R12C21[0][A]	u_test/check_data_15_s1/Q
0.520	0.004	tNET	RR	1	R12C21[0][A]	u_test/n1315_s1/I1
0.892	0.372	tINS	RF	1	R12C21[0][A]	u_test/n1315_s1/F
0.892	0.000	tNET	FF	1	R12C21[0][A]	u_test/check_data_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C21[0][A]	u_test/check_data_15_s1/CLK
0.183	0.000	tHld		1	R12C21[0][A]	u_test/check_data_15_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	7.736
Data Arrival Time	9.100
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_10_s1
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.100	3.799	tNET	FF	1	R13C39[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R13C39[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_10_s1/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_10_s1
16.836	-0.043	tSu		1	R13C39[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_10_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.228%; route: 5.442, 80.953%; tC2Q: 0.458, 6.818%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path2

Path Summary:

Slack	7.736
Data Arrival Time	9.100
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_11_s1
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.100	3.799	tNET	FF	1	R13C39[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R13C39[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_11_s1/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_11_s1
16.836	-0.043	tSu		1	R13C39[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_11_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.228%; route: 5.442, 80.953%; tC2Q: 0.458, 6.818%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path3

Path Summary:

Slack	7.736
Data Arrival Time	9.100
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_12_s1
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.100	3.799	tNET	FF	1	R13C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R13C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_12_s1/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_12_s1
16.836	-0.043	tSu		1	R13C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].id_reg_12_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.228%; route: 5.442, 80.953%; tC2Q: 0.458, 6.818%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path4

Path Summary:

Slack	7.736
Data Arrival Time	9.100
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_3_s1
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.100	3.799	tNET	FF	1	R13C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R13C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_3_s1/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_3_s1
16.836	-0.043	tSu		1	R13C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_3_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.228%; route: 5.442, 80.953%; tC2Q: 0.458, 6.818%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack	7.736
Data Arrival Time	9.100
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].wr_ptr_0_s1
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.100	3.799	tNET	FF	1	R13C31[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].wr_ptr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R13C31[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].wr_ptr_0_s1/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].wr_ptr_0_s1
16.836	-0.043	tSu		1	R13C31[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].wr_ptr_0_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.228%; route: 5.442, 80.953%; tC2Q: 0.458, 6.818%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack	7.736
Data Arrival Time	9.100
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CONFIG_MR8_WAITE_s0
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.100	3.799	tNET	FF	1	R13C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CONFIG_MR8_WAITE_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R13C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CONFIG_MR8_WAITE_s0/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CONFIG_MR8_WAITE_s0
16.836	-0.043	tSu		1	R13C31[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/c_state.CONFIG_MR8_WAITE_s0

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.228%; route: 5.442, 80.953%; tC2Q: 0.458, 6.818%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path7

Path Summary:

Slack	7.755
Data Arrival Time	9.080
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_init/MR_cnt_0_s1
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.080	3.779	tNET	FF	1	R11C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/MR_cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R11C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/MR_cnt_0_s1/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_init/MR_cnt_0_s1
16.836	-0.043	tSu		1	R11C31[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_init/MR_cnt_0_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.264%; route: 5.422, 80.898%; tC2Q: 0.458, 6.838%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack	7.755
Data Arrival Time	9.080
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_1_s0
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.080	3.779	tNET	FF	1	R22C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R22C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_1_s0/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_1_s0
16.836	-0.043	tSu		1	R22C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_1_s0

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.264%; route: 5.422, 80.898%; tC2Q: 0.458, 6.838%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack	7.755
Data Arrival Time	9.080
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_3_s0
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.080	3.779	tNET	FF	1	R22C35[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R22C35[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_3_s0/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_3_s0
16.836	-0.043	tSu		1	R22C35[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/wbin_3_s0

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.264%; route: 5.422, 80.898%; tC2Q: 0.458, 6.838%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path10

Path Summary:

Slack	7.755
Data Arrival Time	9.080
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cmdr_done_s1
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.080	3.779	tNET	FF	1	R20C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cmdr_done_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R20C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cmdr_done_s1/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cmdr_done_s1
16.836	-0.043	tSu		1	R20C35[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cmdr_done_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.264%; route: 5.422, 80.898%; tC2Q: 0.458, 6.838%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack	7.755
Data Arrival Time	9.080
Data Required Time	16.836
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/dqtx1_s0
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
9.080	3.779	tNET	FF	1	R20C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/dqtx1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	R20C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/dqtx1_s0/CLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/dqtx1_s0
16.836	-0.043	tSu		1	R20C39[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/dqtx1_s0

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 12.264%; route: 5.422, 80.898%; tC2Q: 0.458, 6.838%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack	8.409
Data Arrival Time	8.265
Data Required Time	16.674
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	36	BSRAM_R28[10]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/mem_mem_0_0_s/RESETB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	BSRAM_R28[10]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/mem_mem_0_0_s/CLKB
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/mem_mem_0_0_s
16.674	-0.205	tSu		1	BSRAM_R28[10]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/u_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path13

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	2	IOB8[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB8[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
16.834	-0.045	tSu		1	IOB8[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	4	IOR24[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOR24[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4
16.834	-0.045	tSu		1	IOR24[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	4	IOB41[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB41[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4
16.834	-0.045	tSu		1	IOB41[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	4	IOB33[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB33[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4
16.834	-0.045	tSu		1	IOB33[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	4	IOB31[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB31[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4
16.834	-0.045	tSu		1	IOB31[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	4	IOB33[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB33[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4
16.834	-0.045	tSu		1	IOB33[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	4	IOB29[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB29[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4
16.834	-0.045	tSu		1	IOB29[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	4	IOB43[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB43[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4
16.834	-0.045	tSu		1	IOB43[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	4	IOB41[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB41[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4
16.834	-0.045	tSu		1	IOB41[A]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	2	IOR24[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOR24[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4
16.834	-0.045	tSu		1	IOR24[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[6].dq_oser4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	2	IOB41[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[6].dq_oser4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB41[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[6].dq_oser4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[6].dq_oser4
16.834	-0.045	tSu		1	IOB41[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[6].dq_oser4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	2	IOB33[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB33[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4
16.834	-0.045	tSu		1	IOB33[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack	8.569
Data Arrival Time	8.265
Data Required Time	16.834
From	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[4].dq_oser4
Launch Clk	clk:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.982	0.982	tINS	RR	57	IOR5[A]	clk_ibuf/O
2.378	1.396	tNET	RR	1	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK
2.836	0.458	tC2Q	RF	8	R17C24[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/Q
4.479	1.643	tNET	FF	1	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/I0
5.301	0.822	tINS	FF	409	R17C8[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/ddr_rsti_s0/F
8.265	2.964	tNET	FF	2	IOB31[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[4].dq_oser4/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
16.667	16.667					active clock edge time
16.667	0.000					clk_x1
16.667	0.000	tCL	RR	703	BOTTOMSIDE[0]	psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
16.909	0.242	tNET	RR	1	IOB31[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[4].dq_oser4/PCLK
16.879	-0.030	tUnc				psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[4].dq_oser4
16.834	-0.045	tSu		1	IOB31[B]	psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[4].dq_oser4

Path Statistics:

Clock Skew	-2.136
Setup Relationship	16.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.982, 41.291%; route: 1.396, 58.709%
Arrival Data Path Delay	cell: 0.822, 13.963%; route: 4.607, 78.252%; tC2Q: 0.458, 7.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_0_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R20C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_0_s3/CLK
1.877	0.015	tHld		1	R20C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path2

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R20C27[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C27[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3/CLK
1.877	0.015	tHld		1	R20C27[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path3

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_3_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R21C25[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_3_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R21C25[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_3_s3/CLK
1.877	0.015	tHld		1	R21C25[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_3_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path4

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_4_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R21C25[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R21C25[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_4_s3/CLK
1.877	0.015	tHld		1	R21C25[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_4_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path5

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_6_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R20C26[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_6_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C26[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_6_s3/CLK
1.877	0.015	tHld		1	R20C26[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_6_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path6

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R21C26[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R21C26[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s3/CLK
1.877	0.015	tHld		1	R21C26[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path7

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_10_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R20C27[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_10_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C27[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_10_s3/CLK
1.877	0.015	tHld		1	R20C27[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_10_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path8

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_14_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R18C26[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_14_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R18C26[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_14_s3/CLK
1.877	0.015	tHld		1	R18C26[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_14_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path9

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_15_s4
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R18C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_15_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R18C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_15_s4/CLK
1.877	0.015	tHld		1	R18C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_15_s4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path10

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R20C25[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C25[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1/CLK
1.877	0.015	tHld		1	R20C25[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path11

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_5_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R21C25[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R21C25[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_5_s1/CLK
1.877	0.015	tHld		1	R21C25[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path12

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R20C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1/CLK
1.877	0.015	tHld		1	R20C26[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path13

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_9_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R21C27[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R21C27[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_9_s1/CLK
1.877	0.015	tHld		1	R21C27[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path14

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R20C27[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C27[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1/CLK
1.877	0.015	tHld		1	R20C27[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path15

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_12_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R20C27[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R20C27[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_12_s1/CLK
1.877	0.015	tHld		1	R20C27[0][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_12_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path16

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R21C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R21C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/CLK
1.877	0.015	tHld		1	R21C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path17

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R18C26[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_1_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R18C26[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_1_s0/CLK
1.877	0.015	tHld		1	R18C26[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path18

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_syn_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R11C26[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R11C26[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_syn_1_s0/CLK
1.877	0.015	tHld		1	R11C26[1][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_syn_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path19

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R18C26[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R18C26[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_0_s0/CLK
1.877	0.015	tHld		1	R18C26[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path20

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R17C25[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R17C25[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_1_s0/CLK
1.877	0.015	tHld		1	R17C25[2][B]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path21

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R17C25[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R17C25[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0/CLK
1.877	0.015	tHld		1	R17C25[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/count_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path22

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/flag_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R17C26[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/flag_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R17C26[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/flag_0_s0/CLK
1.877	0.015	tHld		1	R17C26[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/flag_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path23

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/flag_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R17C25[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/flag_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R17C25[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/flag_1_s0/CLK
1.877	0.015	tHld		1	R17C25[2][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/flag_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path24

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/dll_rst_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R9C12[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/dll_rst_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C12[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/dll_rst_s0/CLK
1.877	0.015	tHld		1	R9C12[0][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/dll_rst_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Path25

Path Summary:

Slack	2.842
Data Arrival Time	4.719
Data Required Time	1.877
From	button/out_s0
To	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R9C21[2][A]	button/out_s0/CLK
2.195	0.333	tC2Q	RR	1	R9C21[2][A]	button/out_s0/Q
2.432	0.236	tNET	RR	1	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/I
3.156	0.724	tINS	RR	325	R9C21[2][B]	psram_memory_interface_top/u_apsram_top/n455_s2/O
4.719	1.564	tNET	RR	1	R17C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR5[A]	clk_ibuf/I
0.844	0.844	tINS	RR	57	IOR5[A]	clk_ibuf/O
1.862	1.018	tNET	RR	1	R17C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_0_s0/CLK
1.877	0.015	tHld		1	R17C27[1][A]	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%
Arrival Data Path Delay	cell: 0.724, 25.338%; route: 1.800, 62.996%; tC2Q: 0.333, 11.666%
Required Clock Path Delay	cell: 0.844, 45.350%; route: 1.018, 54.650%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.415
Actual Width:	7.665
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	led_0_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
8.334	0.000			active clock edge time
8.334	0.000			clk
8.334	0.000	tCL	FF	clk_ibuf/I
9.318	0.984	tINS	FF	clk_ibuf/O
10.864	1.546	tNET	FF	led_0_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
16.667	0.000			active clock edge time
16.667	0.000			clk
16.667	0.000	tCL	RR	clk_ibuf/I
17.511	0.844	tINS	RR	clk_ibuf/O
18.529	1.018	tNET	RR	led_0_s1/CLK

MPW2

MPW Summary:

Slack:	6.415
Actual Width:	7.665
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	button/in_reg2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
8.334	0.000			active clock edge time
8.334	0.000			clk
8.334	0.000	tCL	FF	clk_ibuf/I
9.318	0.984	tINS	FF	clk_ibuf/O
10.864	1.546	tNET	FF	button/in_reg2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
16.667	0.000			active clock edge time
16.667	0.000			clk
16.667	0.000	tCL	RR	clk_ibuf/I
17.511	0.844	tINS	RR	clk_ibuf/O
18.529	1.018	tNET	RR	button/in_reg2_s0/CLK

MPW3

MPW Summary:

Slack:	6.415
Actual Width:	7.665
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	button/cnt_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
8.334	0.000			active clock edge time
8.334	0.000			clk
8.334	0.000	tCL	FF	clk_ibuf/I
9.318	0.984	tINS	FF	clk_ibuf/O
10.864	1.546	tNET	FF	button/cnt_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
16.667	0.000			active clock edge time
16.667	0.000			clk
16.667	0.000	tCL	RR	clk_ibuf/I
17.511	0.844	tINS	RR	clk_ibuf/O
18.529	1.018	tNET	RR	button/cnt_16_s0/CLK

MPW4

MPW Summary:

Slack:	6.415
Actual Width:	7.665
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	button/cnt_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
8.334	0.000			active clock edge time
8.334	0.000			clk
8.334	0.000	tCL	FF	clk_ibuf/I
9.318	0.984	tINS	FF	clk_ibuf/O
10.864	1.546	tNET	FF	button/cnt_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
16.667	0.000			active clock edge time
16.667	0.000			clk
16.667	0.000	tCL	RR	clk_ibuf/I
17.511	0.844	tINS	RR	clk_ibuf/O
18.529	1.018	tNET	RR	button/cnt_8_s0/CLK

MPW5

MPW Summary:

Slack:	6.415
Actual Width:	7.665
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
8.334	0.000			active clock edge time
8.334	0.000			clk
8.334	0.000	tCL	FF	clk_ibuf/I
9.318	0.984	tINS	FF	clk_ibuf/O
10.864	1.546	tNET	FF	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
16.667	0.000			active clock edge time
16.667	0.000			clk
16.667	0.000	tCL	RR	clk_ibuf/I
17.511	0.844	tINS	RR	clk_ibuf/O
18.529	1.018	tNET	RR	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_2_s0/CLK

MPW6

MPW Summary:

Slack:	6.415
Actual Width:	7.665
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
8.334	0.000			active clock edge time
8.334	0.000			clk
8.334	0.000	tCL	FF	clk_ibuf/I
9.318	0.984	tINS	FF	clk_ibuf/O
10.864	1.546	tNET	FF	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
16.667	0.000			active clock edge time
16.667	0.000			clk
16.667	0.000	tCL	RR	clk_ibuf/I
17.511	0.844	tINS	RR	clk_ibuf/O
18.529	1.018	tNET	RR	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_3_s0/CLK

MPW7

MPW Summary:

Slack:	6.415
Actual Width:	7.665
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	button/cnt_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
8.334	0.000			active clock edge time
8.334	0.000			clk
8.334	0.000	tCL	FF	clk_ibuf/I
9.318	0.984	tINS	FF	clk_ibuf/O
10.864	1.546	tNET	FF	button/cnt_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
16.667	0.000			active clock edge time
16.667	0.000			clk
16.667	0.000	tCL	RR	clk_ibuf/I
17.511	0.844	tINS	RR	clk_ibuf/O
18.529	1.018	tNET	RR	button/cnt_9_s0/CLK

MPW8

MPW Summary:

Slack:	6.415
Actual Width:	7.665
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
8.334	0.000			active clock edge time
8.334	0.000			clk
8.334	0.000	tCL	FF	clk_ibuf/I
9.318	0.984	tINS	FF	clk_ibuf/O
10.864	1.546	tNET	FF	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
16.667	0.000			active clock edge time
16.667	0.000			clk
16.667	0.000	tCL	RR	clk_ibuf/I
17.511	0.844	tINS	RR	clk_ibuf/O
18.529	1.018	tNET	RR	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_4_s0/CLK

MPW9

MPW Summary:

Slack:	6.415
Actual Width:	7.665
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
8.334	0.000			active clock edge time
8.334	0.000			clk
8.334	0.000	tCL	FF	clk_ibuf/I
9.318	0.984	tINS	FF	clk_ibuf/O
10.864	1.546	tNET	FF	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
16.667	0.000			active clock edge time
16.667	0.000			clk
16.667	0.000	tCL	RR	clk_ibuf/I
17.511	0.844	tINS	RR	clk_ibuf/O
18.529	1.018	tNET	RR	psram_memory_interface_top/u_apsram_top/u_psram_sync/cs_memsync_5_s0/CLK

MPW10

MPW Summary:

Slack:	6.415
Actual Width:	7.665
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_0_s3

Late clock Path:

AT	DELAY	TYPE	RF	NODE
8.334	0.000			active clock edge time
8.334	0.000			clk
8.334	0.000	tCL	FF	clk_ibuf/I
9.318	0.984	tINS	FF	clk_ibuf/O
10.864	1.546	tNET	FF	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_0_s3/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
16.667	0.000			active clock edge time
16.667	0.000			clk
16.667	0.000	tCL	RR	clk_ibuf/I
17.511	0.844	tINS	RR	clk_ibuf/O
18.529	1.018	tNET	RR	psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_0_s3/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
703	clk_x1	4.921	0.257
409	ddr_rsti	7.736	3.799
325	n455_6	9.617	3.278
111	init_calib_d	5.023	6.062
90	curr_state.WRITE_BURST	7.564	3.284
69	rd_data_valid_d	9.858	3.136
63	next_state.IDLE_19	5.475	2.209
57	wr_data_31_11	6.385	3.945
57	clk_d	7.062	1.546
39	curr_state.CYC_DONE	9.655	2.155

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R18C15	51.39%
R18C16	51.39%
R20C15	50.00%
R28C33	47.22%
R20C30	47.22%
R20C31	47.22%
R16C20	44.44%
R14C24	44.44%
R17C26	44.44%
R18C17	44.44%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 16.667 -waveform {0 8.334} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name clk_x1 -period 16.667 -waveform {0 8.334} [get_nets {clk_x1}]
TC_CLOCK	Actived	create_clock -name clk_x2 -period 8.333 -waveform {0 4.167} [get_nets {memory_clk}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {clk_x2 clk_x1}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_x1}] -to [get_clocks {clk clk_x2}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_x2}] -to [get_clocks {clk_x1 clk}]