Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\apsram_test.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\button.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\gowin_rpll\gowin_rpll.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\top.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_256_solo_Refdesign\project\fpga_project\src\uhs_psram_memory_interface\uhs_psram_memory_interface.v |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
| Part Number | GW1NR-LV9QN88PC6/I5 |
| Device | GW1NR-9C |
| Created Time | Tue Mar 09 17:34:16 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | syn_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.34s, Peak memory usage = 289.480MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 289.480MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 289.480MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 289.480MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 289.480MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 289.480MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 289.480MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 289.480MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 289.480MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 289.480MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 289.480MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 289.480MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.122s, Peak memory usage = 289.480MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 289.480MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 289.480MB |
Resource
Resource Usage Summary
| I/O Port | 17 |
| I/O Buf | 17 |
| IBUF | 2 |
| OBUF | 6 |
| IOBUF | 9 |
| Register | 738 |
| DFF | 3 |
| DFFE | 1 |
| DFFR | 20 |
| DFFP | 8 |
| DFFPE | 3 |
| DFFC | 317 |
| DFFCE | 386 |
| LUT | 1147 |
| LUT2 | 243 |
| LUT3 | 328 |
| LUT4 | 576 |
| ALU | 129 |
| ALU | 129 |
| INV | 11 |
| INV | 11 |
| IOLOGIC | 28 |
| IDES4 | 8 |
| OSER4 | 11 |
| IODELAY | 9 |
| BSRAM | 1 |
| SDPX9B | 1 |
| CLOCK | 4 |
| DLL | 1 |
| CLKDIV | 1 |
| DHCEN | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Logic | 1287(1158 LUTs, 129 ALUs) / 8640 | 15% |
| Register | 738 / 6693 | 11% |
| --Register as Latch | 0 / 6693 | 0% |
| --Register as FF | 738 / 6693 | 11% |
| BSRAM | 1 / 26 | 4% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 41.667 | 24.0 | 0.000 | 20.833 | clk_ibuf/I | ||
| your_instance_name/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.250 | 160.0 | 0.000 | 3.125 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUT |
| your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.250 | 160.0 | 1.563 | 4.688 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTP |
| your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD |
| your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 18.750 | 53.3 | 0.000 | 9.375 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD3 |
| psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | your_instance_name/rpll_inst/CLKOUT | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 24.0(MHz) | 130.6(MHz) | 5 | TOP |
| 2 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | 80.0(MHz) | 212.9(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -0.735 |
| Data Arrival Time | 13.531 |
| Data Required Time | 12.797 |
| From | psram_memory_interface_top/u_apsram_top/u_dll |
| To | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 8.008 | 1.758 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 8.371 | 0.363 | tNET | RR | 3 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 8.619 | 0.248 | tINS | RR | 21 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT |
| 8.982 | 0.363 | tNET | RR | 8 | psram_memory_interface_top/u_apsram_top/u_dll/CLKIN |
| 9.548 | 0.566 | tINS | RF | 1 | psram_memory_interface_top/u_apsram_top/u_dll/STEP[0] |
| 10.028 | 0.480 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s19/I1 |
| 11.073 | 1.045 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s19/COUT |
| 11.073 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s20/CIN |
| 11.130 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s20/COUT |
| 11.130 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s21/CIN |
| 11.187 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s21/COUT |
| 11.187 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s22/CIN |
| 11.244 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s22/COUT |
| 11.244 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s23/CIN |
| 11.301 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s23/COUT |
| 11.301 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s24/CIN |
| 11.358 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s24/COUT |
| 11.358 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s25/CIN |
| 11.415 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s25/COUT |
| 11.415 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s26/CIN |
| 11.472 | 0.057 | tINS | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s26/COUT |
| 11.952 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n209_s3/I1 |
| 13.051 | 1.099 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n209_s3/F |
| 13.531 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.864 | 0.363 | tCL | RR | 703 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.227 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1/CLK |
| 13.197 | -0.030 | tUnc | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1 | ||
| 12.797 | -0.400 | tSu | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_0_s1 |
| Clock Skew: | -1.642 |
| Setup Relationship: | 6.250 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.248, 40.607%; route: 0.363, 59.393% |
| Arrival Data Path Delay: | cell: 3.109, 63.296%; route: 1.440, 29.314%; tC2Q: 0.363, 7.390% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 2
Path Summary:| Slack | -0.188 |
| Data Arrival Time | 13.341 |
| Data Required Time | 13.153 |
| From | psram_memory_interface_top/u_apsram_top/u_dll |
| To | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 8.008 | 1.758 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 8.371 | 0.363 | tNET | RR | 3 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 8.619 | 0.248 | tINS | RR | 21 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT |
| 8.982 | 0.363 | tNET | RR | 8 | psram_memory_interface_top/u_apsram_top/u_dll/CLKIN |
| 9.548 | 0.566 | tINS | RF | 1 | psram_memory_interface_top/u_apsram_top/u_dll/STEP[0] |
| 10.028 | 0.480 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s19/I1 |
| 11.073 | 1.045 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s19/COUT |
| 11.073 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s20/CIN |
| 11.130 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s20/COUT |
| 11.130 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s21/CIN |
| 11.187 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s21/COUT |
| 11.187 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s22/CIN |
| 11.244 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s22/COUT |
| 11.244 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s23/CIN |
| 11.301 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s23/COUT |
| 11.301 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s24/CIN |
| 11.358 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s24/COUT |
| 11.358 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s25/CIN |
| 11.415 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s25/COUT |
| 11.415 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s26/CIN |
| 11.472 | 0.057 | tINS | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s26/COUT |
| 11.952 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n289_s1/I0 |
| 12.978 | 1.026 | tINS | FR | 8 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n289_s1/F |
| 13.341 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.864 | 0.363 | tCL | RR | 703 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.227 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0/CLK |
| 13.197 | -0.030 | tUnc | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0 | ||
| 13.153 | -0.043 | tSu | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_1_s0 |
| Clock Skew: | -1.642 |
| Setup Relationship: | 6.250 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.248, 40.607%; route: 0.363, 59.393% |
| Arrival Data Path Delay: | cell: 3.036, 64.297%; route: 1.323, 28.016%; tC2Q: 0.363, 7.687% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 3
Path Summary:| Slack | -0.188 |
| Data Arrival Time | 13.341 |
| Data Required Time | 13.153 |
| From | psram_memory_interface_top/u_apsram_top/u_dll |
| To | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 8.008 | 1.758 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 8.371 | 0.363 | tNET | RR | 3 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 8.619 | 0.248 | tINS | RR | 21 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT |
| 8.982 | 0.363 | tNET | RR | 8 | psram_memory_interface_top/u_apsram_top/u_dll/CLKIN |
| 9.548 | 0.566 | tINS | RF | 1 | psram_memory_interface_top/u_apsram_top/u_dll/STEP[0] |
| 10.028 | 0.480 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s19/I1 |
| 11.073 | 1.045 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s19/COUT |
| 11.073 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s20/CIN |
| 11.130 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s20/COUT |
| 11.130 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s21/CIN |
| 11.187 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s21/COUT |
| 11.187 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s22/CIN |
| 11.244 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s22/COUT |
| 11.244 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s23/CIN |
| 11.301 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s23/COUT |
| 11.301 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s24/CIN |
| 11.358 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s24/COUT |
| 11.358 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s25/CIN |
| 11.415 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s25/COUT |
| 11.415 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s26/CIN |
| 11.472 | 0.057 | tINS | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s26/COUT |
| 11.952 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n289_s1/I0 |
| 12.978 | 1.026 | tINS | FR | 8 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n289_s1/F |
| 13.341 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.864 | 0.363 | tCL | RR | 703 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.227 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0/CLK |
| 13.197 | -0.030 | tUnc | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0 | ||
| 13.153 | -0.043 | tSu | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_2_s0 |
| Clock Skew: | -1.642 |
| Setup Relationship: | 6.250 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.248, 40.607%; route: 0.363, 59.393% |
| Arrival Data Path Delay: | cell: 3.036, 64.297%; route: 1.323, 28.016%; tC2Q: 0.363, 7.687% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 4
Path Summary:| Slack | -0.188 |
| Data Arrival Time | 13.341 |
| Data Required Time | 13.153 |
| From | psram_memory_interface_top/u_apsram_top/u_dll |
| To | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 8.008 | 1.758 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 8.371 | 0.363 | tNET | RR | 3 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 8.619 | 0.248 | tINS | RR | 21 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT |
| 8.982 | 0.363 | tNET | RR | 8 | psram_memory_interface_top/u_apsram_top/u_dll/CLKIN |
| 9.548 | 0.566 | tINS | RF | 1 | psram_memory_interface_top/u_apsram_top/u_dll/STEP[0] |
| 10.028 | 0.480 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s19/I1 |
| 11.073 | 1.045 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s19/COUT |
| 11.073 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s20/CIN |
| 11.130 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s20/COUT |
| 11.130 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s21/CIN |
| 11.187 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s21/COUT |
| 11.187 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s22/CIN |
| 11.244 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s22/COUT |
| 11.244 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s23/CIN |
| 11.301 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s23/COUT |
| 11.301 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s24/CIN |
| 11.358 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s24/COUT |
| 11.358 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s25/CIN |
| 11.415 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s25/COUT |
| 11.415 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s26/CIN |
| 11.472 | 0.057 | tINS | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s26/COUT |
| 11.952 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n289_s1/I0 |
| 12.978 | 1.026 | tINS | FR | 8 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n289_s1/F |
| 13.341 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.864 | 0.363 | tCL | RR | 703 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.227 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0/CLK |
| 13.197 | -0.030 | tUnc | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0 | ||
| 13.153 | -0.043 | tSu | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_3_s0 |
| Clock Skew: | -1.642 |
| Setup Relationship: | 6.250 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.248, 40.607%; route: 0.363, 59.393% |
| Arrival Data Path Delay: | cell: 3.036, 64.297%; route: 1.323, 28.016%; tC2Q: 0.363, 7.687% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 5
Path Summary:| Slack | -0.188 |
| Data Arrival Time | 13.341 |
| Data Required Time | 13.153 |
| From | psram_memory_interface_top/u_apsram_top/u_dll |
| To | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 8.008 | 1.758 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 8.371 | 0.363 | tNET | RR | 3 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKIN |
| 8.619 | 0.248 | tINS | RR | 21 | psram_memory_interface_top/u_apsram_top/u_dqce_clk_x2/CLKOUT |
| 8.982 | 0.363 | tNET | RR | 8 | psram_memory_interface_top/u_apsram_top/u_dll/CLKIN |
| 9.548 | 0.566 | tINS | RF | 1 | psram_memory_interface_top/u_apsram_top/u_dll/STEP[0] |
| 10.028 | 0.480 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s19/I1 |
| 11.073 | 1.045 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s19/COUT |
| 11.073 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s20/CIN |
| 11.130 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s20/COUT |
| 11.130 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s21/CIN |
| 11.187 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s21/COUT |
| 11.187 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s22/CIN |
| 11.244 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s22/COUT |
| 11.244 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s23/CIN |
| 11.301 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s23/COUT |
| 11.301 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s24/CIN |
| 11.358 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s24/COUT |
| 11.358 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s25/CIN |
| 11.415 | 0.057 | tINS | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s25/COUT |
| 11.415 | 0.000 | tNET | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s26/CIN |
| 11.472 | 0.057 | tINS | FF | 2 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n199_s26/COUT |
| 11.952 | 0.480 | tNET | FF | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n289_s1/I0 |
| 12.978 | 1.026 | tINS | FR | 8 | psram_memory_interface_top/u_apsram_top/u_psram_wd/n289_s1/F |
| 13.341 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.500 | 0.000 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.864 | 0.363 | tCL | RR | 703 | psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT |
| 13.227 | 0.363 | tNET | RR | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0/CLK |
| 13.197 | -0.030 | tUnc | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0 | ||
| 13.153 | -0.043 | tSu | 1 | psram_memory_interface_top/u_apsram_top/u_psram_wd/step_4_s0 |
| Clock Skew: | -1.642 |
| Setup Relationship: | 6.250 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.248, 40.607%; route: 0.363, 59.393% |
| Arrival Data Path Delay: | cell: 3.036, 64.297%; route: 1.323, 28.016%; tC2Q: 0.363, 7.687% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |