PnR Messages

Report Title PnR Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\impl\gwsynthesis\dk_video.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\dk_video.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\dk_video.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW2AR-LV18QN88PC8/I7
Device GW2AR-18
Device Version C
Created Time Wed Jan 10 10:16:27 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.402s, Elapsed time = 0h 0m 0.403s Placement Phase 1: CPU time = 0h 0m 0.27s, Elapsed time = 0h 0m 0.27s Placement Phase 2: CPU time = 0h 0m 0.709s, Elapsed time = 0h 0m 0.709s Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.436s, Elapsed time = 0h 0m 0.435s Routing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 643MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 2222/20736 11%
    --LUT,ALU,ROM16 2222(2030 LUT, 192 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 1141/15828 8%
    --Logic Register as Latch 0/15552 0%
    --Logic Register as FF 1141/15552 8%
    --I/O Register as Latch 0/276 0%
    --I/O Register as FF 0/276 0%
CLS 1469/10368 15%
I/O Port 12 -
I/O Buf 8 -
    --Input Buf 2 -
    --Output Buf 6 -
    --Inout Buf 0 -
IOLOGIC 16 IDES4
22 OSER4
4 OSER10
18 IODELAY
 50%
BSRAM 4 SDPB
2 SDPX9B
 14%
DSP 00%
PLL 2/2 100%
DCS 0/8 0%
DQCE 0/24 0%
OSC 0/1 0%
CLKDIV 2/8 25%
DLLDLY 0/8 0%
DQS 0/1 0%
DHCEN 1/16 7%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 0/8(0%)
bank 1 0/9(0%)
bank 2 0/4(0%)
bank 3 4/17(23%)
bank 4 0/8(0%)
bank 5 8/10(80%)
bank 6 0/9(0%)
bank 7 0/1(0%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 3/8(38%)
LW 5/8(63%)
GCLK_PIN 0/5(0%)
PLL 2/2(100%)
CLKDIV 2/8(25%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
I_clk_d PRIMARY BR BL
pix_clk PRIMARY BL
dma_clk PRIMARY TR TL BR BL
hdmi_rst_n LW -
n14_11 LW -
Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r[1] LW -
Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r[1] LW -
PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/ddr_rsti LW -
memory_clk HCLK BOTTOM[0] LEFT[0] RIGHT[0]
serial_clk HCLK BOTTOM[0] BOTTOM[1]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
I_clk 51/3 Y in IOR45[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
I_rst_n 56/3 Y in IOR36[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
O_led[0] 48/3 Y out IOR49[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_led[1] 49/3 Y out IOR49[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_tmds_clk_p O_tmds_clk_n 25,26/5 Y out IOB6 LVDS25 3.5 NA NA NA NA NA NA NA 2.5
O_tmds_data_p[0] O_tmds_data_n[0] 27,28/5 Y out IOB8 LVDS25 3.5 NA NA NA NA NA NA NA 2.5
O_tmds_data_p[1] O_tmds_data_n[1] 29,30/5 Y out IOB14 LVDS25 3.5 NA NA NA NA NA NA NA 2.5
O_tmds_data_p[2] O_tmds_data_n[2] 31,32/5 Y out IOB18 LVDS25 3.5 NA NA NA NA NA NA NA 2.5

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
86/0 - in IOT4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
85/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
84/0 - in IOT6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
83/0 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
82/0 - in IOT17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
81/0 - in IOT17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
80/0 - in IOT27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
79/0 - in IOT27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
77/1 - in IOT30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
76/1 - in IOT30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
75/1 - in IOT34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
74/1 - in IOT34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
73/1 - in IOT40[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
72/1 - in IOT40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
71/1 - in IOT44[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
70/1 - in IOT44[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
69/1 - in IOT50[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
25/5 O_tmds_clk_p out IOB6[A] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
26/5 O_tmds_clk_n out IOB6[B] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
27/5 O_tmds_data_p[0] out IOB8[A] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
28/5 O_tmds_data_n[0] out IOB8[B] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
29/5 O_tmds_data_p[1] out IOB14[A] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
30/5 O_tmds_data_n[1] out IOB14[B] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
31/5 O_tmds_data_p[2] out IOB18[A] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
32/5 O_tmds_data_n[2] out IOB18[B] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
33/5 - in IOB24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
34/5 - in IOB24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
35/4 - in IOB30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
36/4 - in IOB30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
37/4 - in IOB34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
38/4 - in IOB34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/4 - in IOB40[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/4 - in IOB40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/4 - in IOB42[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/4 - in IOB43[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/7 - in IOL7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/6 - in IOL29[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
11/6 - in IOL29[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/6 - in IOL45[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/6 - in IOL47[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
16/6 - in IOL47[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/6 - in IOL49[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
18/6 - in IOL49[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/6 - in IOL51[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
20/6 - in IOL51[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/2 - out IOR25[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
5/2 - in IOR25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
6/2 - in IOR26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/2 - in IOR26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
63/3 - in IOR29[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
88/3 - in IOR30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
87/3 - in IOR30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
9/3 - in IOR31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
62/3 - in IOR33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
61/3 - in IOR33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
60/3 - in IOR34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
59/3 - in IOR34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
57/3 - in IOR35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
56/3 I_rst_n in IOR36[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
55/3 - in IOR36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
54/3 - in IOR38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
53/3 - in IOR38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
52/3 - in IOR39[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
51/3 I_clk in IOR45[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
49/3 O_led[1] out IOR49[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
48/3 O_led[0] out IOR49[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3