Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\VFB\data\vfb_top.v D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\VFB\data\vfb_wrapper.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-6 |
| Part Number | GW1NSR-LV4CQN48PC7/I6 |
| Device | GW1NSR-4C |
| Created Time | Tue Oct 24 14:28:00 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Video_Frame_Buffer_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.337s, Peak memory usage = 36.988MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 36.988MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 36.988MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 36.988MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 36.988MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 36.988MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 36.988MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 36.988MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 36.988MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 36.988MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 36.988MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 36.988MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 51.883MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 51.883MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 51.883MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 51.883MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 139 |
| I/O Buf | 139 |
| IBUF | 60 |
| OBUF | 79 |
| Register | 339 |
| DFF | 1 |
| DFFS | 8 |
| DFFR | 2 |
| DFFP | 28 |
| DFFPE | 2 |
| DFFC | 228 |
| DFFCE | 70 |
| LUT | 423 |
| LUT2 | 90 |
| LUT3 | 136 |
| LUT4 | 197 |
| ALU | 38 |
| ALU | 38 |
| INV | 5 |
| INV | 5 |
| BSRAM | 2 |
| SDPB | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 466(428 LUT, 38 ALU) / 4608 | 11% |
| Register | 339 / 3570 | 10% |
| --Register as Latch | 0 / 3570 | 0% |
| --Register as FF | 339 / 3570 | 10% |
| BSRAM | 2 / 10 | 20% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_vin0_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_vin0_clk_ibuf/I | ||
| I_dma_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_dma_clk_ibuf/I | ||
| I_vout0_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_vout0_clk_ibuf/I | ||
| vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 | Base | 20.000 | 50.0 | 0.000 | 10.000 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_s2/O | ||
| vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 | Base | 20.000 | 50.0 | 0.000 | 10.000 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_s2/O | ||
| vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n35_6 | Base | 20.000 | 50.0 | 0.000 | 10.000 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n35_s2/O |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_vin0_clk | 50.0(MHz) | 150.7(MHz) | 6 | TOP |
| 2 | I_dma_clk | 50.0(MHz) | 122.5(MHz) | 9 | TOP |
| 3 | I_vout0_clk | 50.0(MHz) | 138.3(MHz) | 8 | TOP |
| 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 | 50.0(MHz) | 1008.4(MHz) | 1 | TOP |
| 5 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 | 50.0(MHz) | 1008.4(MHz) | 1 | TOP |
| 6 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n35_6 | 50.0(MHz) | 1008.4(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 11.836 |
| Data Arrival Time | 8.864 |
| Data Required Time | 20.700 |
| From | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1 |
| To | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0 |
| Launch Clk | I_dma_clk[R] |
| Latch Clk | I_dma_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_dma_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_dma_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 219 | I_dma_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1/CLK |
| 1.336 | 0.340 | tC2Q | RF | 16 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1/Q |
| 1.692 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s4/I1 |
| 2.506 | 0.814 | tINS | FF | 8 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s4/F |
| 2.862 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/I3 |
| 3.326 | 0.464 | tINS | FF | 8 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/F |
| 3.681 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s4/I3 |
| 4.145 | 0.464 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s4/F |
| 4.501 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s3/I1 |
| 5.315 | 0.814 | tINS | FF | 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s3/F |
| 5.671 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_7_s1/I0 |
| 6.436 | 0.765 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_7_s1/F |
| 6.791 | 0.356 | tNET | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n323_s0/I0 |
| 7.501 | 0.710 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n323_s0/COUT |
| 7.501 | 0.000 | tNET | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n324_s0/CIN |
| 7.544 | 0.042 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n324_s0/COUT |
| 7.899 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2 |
| 8.508 | 0.609 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F |
| 8.864 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_dma_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_dma_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 219 | I_dma_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK |
| 20.700 | -0.296 | tSu | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 4.682, 59.516%; route: 2.845, 36.167%; tC2Q: 0.340, 4.317% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 2
Path Summary:| Slack | 12.769 |
| Data Arrival Time | 7.931 |
| Data Required Time | 20.700 |
| From | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0 |
| To | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0 |
| Launch Clk | I_vout0_clk[R] |
| Latch Clk | I_vout0_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vout0_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vout0_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 57 | I_vout0_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/CLK |
| 1.336 | 0.340 | tC2Q | RF | 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/Q |
| 1.692 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s4/I1 |
| 2.506 | 0.814 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s4/F |
| 2.862 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s4/I3 |
| 3.326 | 0.464 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s4/F |
| 3.681 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_7_s4/I2 |
| 4.291 | 0.609 | tINS | FF | 3 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_7_s4/F |
| 4.646 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_6_s0/I1 |
| 5.461 | 0.814 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_6_s0/F |
| 5.816 | 0.356 | tNET | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n322_s0/I0 |
| 6.526 | 0.710 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n322_s0/COUT |
| 6.526 | 0.000 | tNET | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n323_s0/CIN |
| 6.568 | 0.042 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n323_s0/COUT |
| 6.568 | 0.000 | tNET | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n324_s0/CIN |
| 6.611 | 0.042 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n324_s0/COUT |
| 6.966 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2 |
| 7.575 | 0.609 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F |
| 7.931 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_vout0_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_vout0_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 57 | I_vout0_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK |
| 20.700 | -0.296 | tSu | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 4.105, 59.198%; route: 2.490, 35.904%; tC2Q: 0.340, 4.898% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 3
Path Summary:| Slack | 13.257 |
| Data Arrival Time | 7.443 |
| Data Required Time | 20.700 |
| From | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5 |
| To | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0 |
| Launch Clk | I_dma_clk[R] |
| Latch Clk | I_dma_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_dma_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_dma_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 219 | I_dma_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLK |
| 1.336 | 0.340 | tC2Q | RF | 3 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/Q |
| 1.692 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n60_s2/I1 |
| 2.506 | 0.814 | tINS | FF | 43 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n60_s2/F |
| 2.862 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_3_s1/I0 |
| 3.627 | 0.765 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_3_s1/F |
| 3.982 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_4_s0/I1 |
| 4.797 | 0.814 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_4_s0/F |
| 5.152 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s1/I1 |
| 5.967 | 0.814 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s1/F |
| 6.322 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/I0 |
| 7.087 | 0.765 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/F |
| 7.443 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_dma_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_dma_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 219 | I_dma_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/CLK |
| 20.700 | -0.296 | tSu | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 3.973, 61.625%; route: 2.134, 33.106%; tC2Q: 0.340, 5.269% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 4
Path Summary:| Slack | 13.363 |
| Data Arrival Time | 7.337 |
| Data Required Time | 20.700 |
| From | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0 |
| To | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0 |
| Launch Clk | I_vin0_clk[R] |
| Latch Clk | I_vin0_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vin0_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vin0_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 62 | I_vin0_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/CLK |
| 1.336 | 0.340 | tC2Q | RF | 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/Q |
| 1.692 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_1_s1/I1 |
| 2.506 | 0.814 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_1_s1/F |
| 2.862 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_5_s1/I2 |
| 3.471 | 0.609 | tINS | FF | 8 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_5_s1/F |
| 3.827 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_6_s0/I1 |
| 4.641 | 0.814 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_6_s0/F |
| 4.997 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s2/I1 |
| 5.811 | 0.814 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s2/F |
| 6.167 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s0/I1 |
| 6.981 | 0.814 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s0/F |
| 7.337 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_vin0_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_vin0_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 62 | I_vin0_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0/CLK |
| 20.700 | -0.296 | tSu | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 3.867, 60.984%; route: 2.134, 33.659%; tC2Q: 0.340, 5.357% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 5
Path Summary:| Slack | 13.413 |
| Data Arrival Time | 7.287 |
| Data Required Time | 20.700 |
| From | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0 |
| To | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wptr_8_s1 |
| Launch Clk | I_vin0_clk[R] |
| Latch Clk | I_vin0_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vin0_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vin0_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 62 | I_vin0_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/CLK |
| 1.336 | 0.340 | tC2Q | RF | 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/Q |
| 1.692 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_1_s1/I1 |
| 2.506 | 0.814 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_1_s1/F |
| 2.862 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_5_s1/I2 |
| 3.471 | 0.609 | tINS | FF | 8 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_5_s1/F |
| 3.827 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_9_s5/I1 |
| 4.641 | 0.814 | tINS | FF | 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_9_s5/F |
| 4.997 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_9_s3/I1 |
| 5.811 | 0.814 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_9_s3/F |
| 6.167 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_8_s1/I0 |
| 6.931 | 0.765 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_8_s1/F |
| 7.287 | 0.356 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wptr_8_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_vin0_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_vin0_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 62 | I_vin0_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wptr_8_s1/CLK |
| 20.700 | -0.296 | tSu | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wptr_8_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 3.817, 60.676%; route: 2.134, 33.925%; tC2Q: 0.340, 5.399% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |