Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\gowin_rpll\gw_rpll.v E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\gowin_rpll\pix_rpll.v E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\SDRAM_controller_top_SIP\SDRAM_controller_top_SIP.v E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\syn_code\syn_gen.v E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\testpattern.v E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\video_frame_buffer\video_frame_buffer.v E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\video_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2AR-LV18EQ144C8/I7 |
| Device | GW2AR-18 |
| Device Version | C |
| Created Time | Wed Jan 10 09:25:15 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | video_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.421s, Peak memory usage = 375.770MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 375.770MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 375.770MB Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 375.770MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 375.770MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 375.770MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 375.770MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 375.770MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 375.770MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 375.770MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 375.770MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 406.578MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 406.578MB Generate output files: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 406.578MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 406.578MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 35 |
| Embedded Port | 55 |
| I/O Buf | 90 |
| IBUF | 2 |
| OBUF | 56 |
| IOBUF | 32 |
| Register | 1087 |
| DFF | 39 |
| DFFE | 159 |
| DFFS | 22 |
| DFFR | 41 |
| DFFP | 33 |
| DFFPE | 5 |
| DFFC | 535 |
| DFFCE | 253 |
| LUT | 1366 |
| LUT2 | 207 |
| LUT3 | 386 |
| LUT4 | 773 |
| ALU | 104 |
| ALU | 104 |
| SSRAM | 9 |
| RAM16S4 | 9 |
| INV | 22 |
| INV | 22 |
| BSRAM | 9 |
| SDPB | 8 |
| SDPX9B | 1 |
| CLOCK | 2 |
| rPLL | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1546(1388 LUT, 104 ALU, 9 RAM16) / 20736 | 8% |
| Register | 1087 / 16077 | 7% |
| --Register as Latch | 0 / 16077 | 0% |
| --Register as FF | 1087 / 16077 | 7% |
| BSRAM | 9 / 46 | 20% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_clk_ibuf/I | ||
| Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n38_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n38_s2/O | ||
| Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n43_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n43_s2/O | ||
| Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6_0 | Base | 10.000 | 100.0 | 0.000 | 5.000 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_s2/O | ||
| pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 15.385 | 65.0 | 0.000 | 7.692 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUT |
| pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 15.385 | 65.0 | 0.000 | 7.692 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUTP |
| pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 30.769 | 32.5 | 0.000 | 15.385 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUTD |
| pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 46.154 | 21.7 | 0.000 | 23.077 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUTD3 |
| gw_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 8.333 | 120.0 | 0.000 | 4.167 | I_clk_ibuf/I | I_clk | gw_rpll_inst/rpll_inst/CLKOUT |
| gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 8.333 | 120.0 | 0.521 | 4.688 | I_clk_ibuf/I | I_clk | gw_rpll_inst/rpll_inst/CLKOUTP |
| gw_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 16.667 | 60.0 | 0.000 | 8.333 | I_clk_ibuf/I | I_clk | gw_rpll_inst/rpll_inst/CLKOUTD |
| gw_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 25.000 | 40.0 | 0.000 | 12.500 | I_clk_ibuf/I | I_clk | gw_rpll_inst/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_clk | 50.0(MHz) | 229.9(MHz) | 6 | TOP |
| 2 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n38_6 | 100.0(MHz) | 1984.1(MHz) | 1 | TOP |
| 3 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n43_6 | 100.0(MHz) | 1984.1(MHz) | 1 | TOP |
| 4 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6_0 | 100.0(MHz) | 1984.1(MHz) | 1 | TOP |
| 5 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | 65.0(MHz) | 173.6(MHz) | 9 | TOP |
| 6 | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | 120.0(MHz) | 155.1(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -0.416 |
| Data Arrival Time | 93.863 |
| Data Required Time | 93.447 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_0_s1 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_0_s1 |
| Launch Clk | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk[R] |
| Latch Clk | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 92.188 | 0.000 | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | |||
| 93.214 | 1.027 | tCL | RR | 613 | gw_rpll_inst/rpll_inst/CLKOUTP |
| 93.394 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_0_s1/CLK |
| 93.626 | 0.232 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_0_s1/Q |
| 93.863 | 0.237 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 92.308 | 0.000 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 93.337 | 1.029 | tCL | RR | 161 | pix_rpll_inst/rpll_inst/CLKOUT |
| 93.517 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_0_s1/CLK |
| 93.482 | -0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_0_s1 | ||
| 93.447 | -0.035 | tSu | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_0_s1 |
| Clock Skew: | 0.002 |
| Setup Relationship: | 0.120 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 2
Path Summary:| Slack | -0.416 |
| Data Arrival Time | 93.863 |
| Data Required Time | 93.447 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_1_s1 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_1_s1 |
| Launch Clk | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk[R] |
| Latch Clk | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 92.188 | 0.000 | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | |||
| 93.214 | 1.027 | tCL | RR | 613 | gw_rpll_inst/rpll_inst/CLKOUTP |
| 93.394 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_1_s1/CLK |
| 93.626 | 0.232 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_1_s1/Q |
| 93.863 | 0.237 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 92.308 | 0.000 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 93.337 | 1.029 | tCL | RR | 161 | pix_rpll_inst/rpll_inst/CLKOUT |
| 93.517 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_1_s1/CLK |
| 93.482 | -0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_1_s1 | ||
| 93.447 | -0.035 | tSu | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_1_s1 |
| Clock Skew: | 0.002 |
| Setup Relationship: | 0.120 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 3
Path Summary:| Slack | -0.416 |
| Data Arrival Time | 93.863 |
| Data Required Time | 93.447 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_2_s1 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_2_s1 |
| Launch Clk | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk[R] |
| Latch Clk | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 92.188 | 0.000 | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | |||
| 93.214 | 1.027 | tCL | RR | 613 | gw_rpll_inst/rpll_inst/CLKOUTP |
| 93.394 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_2_s1/CLK |
| 93.626 | 0.232 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_2_s1/Q |
| 93.863 | 0.237 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 92.308 | 0.000 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 93.337 | 1.029 | tCL | RR | 161 | pix_rpll_inst/rpll_inst/CLKOUT |
| 93.517 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_2_s1/CLK |
| 93.482 | -0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_2_s1 | ||
| 93.447 | -0.035 | tSu | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_2_s1 |
| Clock Skew: | 0.002 |
| Setup Relationship: | 0.120 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 4
Path Summary:| Slack | -0.416 |
| Data Arrival Time | 93.863 |
| Data Required Time | 93.447 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_3_s1 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_3_s1 |
| Launch Clk | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk[R] |
| Latch Clk | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 92.188 | 0.000 | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | |||
| 93.214 | 1.027 | tCL | RR | 613 | gw_rpll_inst/rpll_inst/CLKOUTP |
| 93.394 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_3_s1/CLK |
| 93.626 | 0.232 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_3_s1/Q |
| 93.863 | 0.237 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 92.308 | 0.000 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 93.337 | 1.029 | tCL | RR | 161 | pix_rpll_inst/rpll_inst/CLKOUT |
| 93.517 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_3_s1/CLK |
| 93.482 | -0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_3_s1 | ||
| 93.447 | -0.035 | tSu | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_3_s1 |
| Clock Skew: | 0.002 |
| Setup Relationship: | 0.120 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 5
Path Summary:| Slack | -0.416 |
| Data Arrival Time | 93.863 |
| Data Required Time | 93.447 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_4_s1 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_4_s1 |
| Launch Clk | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk[R] |
| Latch Clk | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 92.188 | 0.000 | gw_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | |||
| 93.214 | 1.027 | tCL | RR | 613 | gw_rpll_inst/rpll_inst/CLKOUTP |
| 93.394 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_4_s1/CLK |
| 93.626 | 0.232 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_4_s1/Q |
| 93.863 | 0.237 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 92.308 | 0.000 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 93.337 | 1.029 | tCL | RR | 161 | pix_rpll_inst/rpll_inst/CLKOUT |
| 93.517 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_4_s1/CLK |
| 93.482 | -0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_4_s1 | ||
| 93.447 | -0.035 | tSu | 1 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_4_s1 |
| Clock Skew: | 0.002 |
| Setup Relationship: | 0.120 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |