Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\VFB\data\vfb_top.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\VFB\data\vfb_wrapper.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2AR-LV18QN88PC8/I7
Device GW2AR-18
Device Version C
Created Time Wed Jan 10 10:16:05 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Video_Frame_Buffer_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.177s, Peak memory usage = 42.594MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 42.594MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 42.594MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 42.594MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 42.594MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 42.594MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 42.594MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 42.594MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 42.594MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 42.594MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 42.594MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 42.594MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 72.598MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 72.598MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 72.598MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 72.598MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 206
I/O Buf 204
    IBUF 90
    OBUF 114
Register 321
    DFF 1
    DFFP 28
    DFFPE 2
    DFFC 226
    DFFCE 64
LUT 497
    LUT2 66
    LUT3 206
    LUT4 225
ALU 38
    ALU 38
INV 5
    INV 5
BSRAM 4
    SDPB 4

Resource Utilization Summary

Resource Usage Utilization
Logic 540(502 LUT, 38 ALU) / 20736 3%
Register 321 / 15750 3%
  --Register as Latch 0 / 15750 0%
  --Register as FF 321 / 15750 3%
BSRAM 4 / 46 9%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_vin0_clk Base 10.000 100.0 0.000 5.000 I_vin0_clk_ibuf/I
I_dma_clk Base 10.000 100.0 0.000 5.000 I_dma_clk_ibuf/I
I_vout0_clk Base 10.000 100.0 0.000 5.000 I_vout0_clk_ibuf/I
vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 Base 10.000 100.0 0.000 5.000 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_s2/O
vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 Base 10.000 100.0 0.000 5.000 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_s2/O
vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6 Base 10.000 100.0 0.000 5.000 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_vin0_clk 100.0(MHz) 224.0(MHz) 6 TOP
2 I_dma_clk 100.0(MHz) 180.2(MHz) 9 TOP
3 I_vout0_clk 100.0(MHz) 190.2(MHz) 9 TOP
4 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 100.0(MHz) 1984.1(MHz) 1 TOP
5 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 100.0(MHz) 1984.1(MHz) 1 TOP
6 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6 100.0(MHz) 1984.1(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.451
Data Arrival Time 6.377
Data Required Time 10.828
From vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1
To vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 201 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1/CLK
1.095 0.232 tC2Q RF 15 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1/Q
1.332 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s4/I1
1.887 0.555 tINS FF 8 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s4/F
2.124 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/I3
2.495 0.371 tINS FF 9 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/F
2.732 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s4/I2
3.185 0.453 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s4/F
3.422 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s3/I2
3.875 0.453 tINS FF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s3/F
4.112 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_7_s1/I0
4.629 0.517 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_7_s1/F
4.866 0.237 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n451_s0/I0
5.415 0.549 tINS FR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n451_s0/COUT
5.415 0.000 tNET RR 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n452_s0/CIN
5.450 0.035 tINS RF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n452_s0/COUT
5.687 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2
6.140 0.453 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F
6.377 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 201 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK
10.828 -0.035 tSu 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.386, 61.409%; route: 1.896, 34.384%; tC2Q: 0.232, 4.207%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 4.743
Data Arrival Time 6.085
Data Required Time 10.828
From vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0
To vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Launch Clk I_vout0_clk[R]
Latch Clk I_vout0_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vout0_clk
0.000 0.000 tCL RR 1 I_vout0_clk_ibuf/I
0.683 0.683 tINS RR 59 I_vout0_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/CLK
1.095 0.232 tC2Q RF 34 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/Q
1.332 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s5/I1
1.887 0.555 tINS FF 8 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s5/F
2.124 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s4/I1
2.679 0.555 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s4/F
2.916 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s3/I2
3.369 0.453 tINS FF 3 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s3/F
3.606 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_2_s0/I1
4.161 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_2_s0/F
4.398 0.237 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n425_s0/I0
4.946 0.549 tINS FR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n425_s0/COUT
4.946 0.000 tNET RR 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n426_s0/CIN
4.982 0.035 tINS RF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n426_s0/COUT
4.982 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n427_s0/CIN
5.017 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n427_s0/COUT
5.017 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n428_s0/CIN
5.052 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n428_s0/COUT
5.052 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n429_s0/CIN
5.087 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n429_s0/COUT
5.087 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n430_s0/CIN
5.123 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n430_s0/COUT
5.123 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n431_s0/CIN
5.158 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n431_s0/COUT
5.395 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2
5.848 0.453 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F
6.085 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vout0_clk
10.000 0.000 tCL RR 1 I_vout0_clk_ibuf/I
10.682 0.683 tINS RR 59 I_vout0_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK
10.828 -0.035 tSu 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.331, 63.789%; route: 1.659, 31.768%; tC2Q: 0.232, 4.443%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 5.536
Data Arrival Time 5.292
Data Required Time 10.828
From vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1
To vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_20_s1
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 201 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/CLK
1.095 0.232 tC2Q RF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/Q
1.332 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n167_s3/I1
1.887 0.555 tINS FF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n167_s3/F
2.124 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n164_s4/I1
2.679 0.555 tINS FF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n164_s4/F
2.916 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n161_s4/I1
3.471 0.555 tINS FF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n161_s4/F
3.708 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n158_s4/I1
4.263 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n158_s4/F
4.500 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n157_s2/I1
5.055 0.555 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n157_s2/F
5.292 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_20_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 201 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_20_s1/CLK
10.828 -0.035 tSu 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_20_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.775, 62.655%; route: 1.422, 32.107%; tC2Q: 0.232, 5.238%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.536
Data Arrival Time 5.292
Data Required Time 10.828
From vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_8_s1
To vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_20_s1
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 201 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_8_s1/CLK
1.095 0.232 tC2Q RF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_8_s1/Q
1.332 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n226_s3/I1
1.887 0.555 tINS FF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n226_s3/F
2.124 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n223_s4/I1
2.679 0.555 tINS FF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n223_s4/F
2.916 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n220_s4/I1
3.471 0.555 tINS FF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n220_s4/F
3.708 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n217_s4/I1
4.263 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n217_s4/F
4.500 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n216_s2/I1
5.055 0.555 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n216_s2/F
5.292 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_20_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 201 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_20_s1/CLK
10.828 -0.035 tSu 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_20_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.775, 62.655%; route: 1.422, 32.107%; tC2Q: 0.232, 5.238%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 5.536
Data Arrival Time 5.292
Data Required Time 10.828
From vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0
To vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0
Launch Clk I_vin0_clk[R]
Latch Clk I_vin0_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vin0_clk
0.000 0.000 tCL RR 1 I_vin0_clk_ibuf/I
0.683 0.683 tINS RR 64 I_vin0_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/CLK
1.095 0.232 tC2Q RF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/Q
1.332 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_0_s1/I1
1.887 0.555 tINS FF 10 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_0_s1/F
2.124 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_5_s5/I1
2.679 0.555 tINS FF 3 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_5_s5/F
2.916 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s6/I1
3.471 0.555 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s6/F
3.708 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s2/I1
4.263 0.555 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s2/F
4.500 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s0/I1
5.055 0.555 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s0/F
5.292 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vin0_clk
10.000 0.000 tCL RR 1 I_vin0_clk_ibuf/I
10.682 0.683 tINS RR 64 I_vin0_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0/CLK
10.828 -0.035 tSu 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.775, 62.655%; route: 1.422, 32.107%; tC2Q: 0.232, 5.238%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%