Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\SCALER\data\scaler_wrapper.v D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\SCALER\data\static_macro_define.v D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\SCALER\data\scaler_top.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-6 |
| Part Number | GW2A-LV18PG484C8/I7 |
| Device | GW2A-18 |
| Device Version | C |
| Created Time | Tue Oct 24 11:15:04 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Scaler_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.563s, Peak memory usage = 45.063MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 45.063MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 45.063MB Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 45.063MB Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.157s, Peak memory usage = 45.063MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 45.063MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 45.063MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 45.063MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 45.063MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.211s, Peak memory usage = 45.063MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 45.063MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 45.063MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 60.223MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.231s, Peak memory usage = 60.223MB Generate output files: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.249s, Peak memory usage = 60.223MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 60.223MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 161 |
| I/O Buf | 161 |
| IBUF | 133 |
| OBUF | 28 |
| Register | 1076 |
| DFF | 30 |
| DFFR | 3 |
| DFFC | 251 |
| DFFCE | 792 |
| LUT | 933 |
| LUT2 | 165 |
| LUT3 | 419 |
| LUT4 | 349 |
| ALU | 365 |
| ALU | 365 |
| SSRAM | 7 |
| RAM16S4 | 5 |
| RAM16SDP1 | 1 |
| RAM16SDP2 | 1 |
| INV | 31 |
| INV | 31 |
| DSP | |
| MULT18X18 | 12 |
| BSRAM | 12 |
| SDPB | 12 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1371(964 LUT, 365 ALU, 7 RAM16) / 20736 | 7% |
| Register | 1076 / 16509 | 7% |
| --Register as Latch | 0 / 16509 | 0% |
| --Register as FF | 1076 / 16509 | 7% |
| BSRAM | 12 / 46 | 27% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_vin_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_vin_clk_ibuf/I | ||
| I_sysclk | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_sysclk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_vin_clk | 100.0(MHz) | 173.7(MHz) | 9 | TOP |
| 2 | I_sysclk | 100.0(MHz) | 191.6(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.242 |
| Data Arrival Time | 6.585 |
| Data Required Time | 10.828 |
| From | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1 |
| To | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1 |
| Launch Clk | I_vin_clk[R] |
| Latch Clk | I_vin_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vin_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vin_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 115 | I_vin_clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s26/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | scaler_wrapper_inst/mode_control_inst/n362_s26/COUT |
| 1.901 | 0.000 | tNET | RR | 2 | scaler_wrapper_inst/mode_control_inst/n439_s26/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | scaler_wrapper_inst/mode_control_inst/n439_s26/COUT |
| 1.937 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s27/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n362_s27/COUT |
| 1.972 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n439_s27/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n439_s27/COUT |
| 2.007 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s28/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n362_s28/COUT |
| 2.279 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n441_s17/I2 |
| 2.732 | 0.453 | tINS | FF | 2 | scaler_wrapper_inst/mode_control_inst/n441_s17/F |
| 2.969 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s11/I2 |
| 3.422 | 0.453 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s11/F |
| 3.659 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s8/I2 |
| 4.112 | 0.453 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s8/F |
| 4.349 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s6/I1 |
| 4.904 | 0.555 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s6/F |
| 5.141 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s3/I2 |
| 5.594 | 0.453 | tINS | FF | 13 | scaler_wrapper_inst/mode_control_inst/n402_s3/F |
| 5.831 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s2/I0 |
| 6.348 | 0.517 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s2/F |
| 6.585 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_vin_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_vin_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 115 | I_vin_clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.595, 62.815%; route: 1.896, 33.131%; tC2Q: 0.232, 4.054% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 4.242 |
| Data Arrival Time | 6.585 |
| Data Required Time | 10.828 |
| From | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1 |
| To | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_1_s1 |
| Launch Clk | I_vin_clk[R] |
| Latch Clk | I_vin_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vin_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vin_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 115 | I_vin_clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s26/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | scaler_wrapper_inst/mode_control_inst/n362_s26/COUT |
| 1.901 | 0.000 | tNET | RR | 2 | scaler_wrapper_inst/mode_control_inst/n439_s26/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | scaler_wrapper_inst/mode_control_inst/n439_s26/COUT |
| 1.937 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s27/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n362_s27/COUT |
| 1.972 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n439_s27/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n439_s27/COUT |
| 2.007 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s28/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n362_s28/COUT |
| 2.279 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n441_s17/I2 |
| 2.732 | 0.453 | tINS | FF | 2 | scaler_wrapper_inst/mode_control_inst/n441_s17/F |
| 2.969 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s11/I2 |
| 3.422 | 0.453 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s11/F |
| 3.659 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s8/I2 |
| 4.112 | 0.453 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s8/F |
| 4.349 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s6/I1 |
| 4.904 | 0.555 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s6/F |
| 5.141 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s3/I2 |
| 5.594 | 0.453 | tINS | FF | 13 | scaler_wrapper_inst/mode_control_inst/n402_s3/F |
| 5.831 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n401_s2/I0 |
| 6.348 | 0.517 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n401_s2/F |
| 6.585 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_vin_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_vin_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 115 | I_vin_clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_1_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.595, 62.815%; route: 1.896, 33.131%; tC2Q: 0.232, 4.054% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 4.242 |
| Data Arrival Time | 6.585 |
| Data Required Time | 10.828 |
| From | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1 |
| To | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_2_s1 |
| Launch Clk | I_vin_clk[R] |
| Latch Clk | I_vin_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vin_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vin_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 115 | I_vin_clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s26/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | scaler_wrapper_inst/mode_control_inst/n362_s26/COUT |
| 1.901 | 0.000 | tNET | RR | 2 | scaler_wrapper_inst/mode_control_inst/n439_s26/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | scaler_wrapper_inst/mode_control_inst/n439_s26/COUT |
| 1.937 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s27/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n362_s27/COUT |
| 1.972 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n439_s27/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n439_s27/COUT |
| 2.007 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s28/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n362_s28/COUT |
| 2.279 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n441_s17/I2 |
| 2.732 | 0.453 | tINS | FF | 2 | scaler_wrapper_inst/mode_control_inst/n441_s17/F |
| 2.969 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s11/I2 |
| 3.422 | 0.453 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s11/F |
| 3.659 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s8/I2 |
| 4.112 | 0.453 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s8/F |
| 4.349 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s6/I1 |
| 4.904 | 0.555 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s6/F |
| 5.141 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s3/I2 |
| 5.594 | 0.453 | tINS | FF | 13 | scaler_wrapper_inst/mode_control_inst/n402_s3/F |
| 5.831 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n400_s2/I0 |
| 6.348 | 0.517 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n400_s2/F |
| 6.585 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_vin_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_vin_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 115 | I_vin_clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_2_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.595, 62.815%; route: 1.896, 33.131%; tC2Q: 0.232, 4.054% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 4.242 |
| Data Arrival Time | 6.585 |
| Data Required Time | 10.828 |
| From | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1 |
| To | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_3_s1 |
| Launch Clk | I_vin_clk[R] |
| Latch Clk | I_vin_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vin_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vin_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 115 | I_vin_clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s26/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | scaler_wrapper_inst/mode_control_inst/n362_s26/COUT |
| 1.901 | 0.000 | tNET | RR | 2 | scaler_wrapper_inst/mode_control_inst/n439_s26/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | scaler_wrapper_inst/mode_control_inst/n439_s26/COUT |
| 1.937 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s27/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n362_s27/COUT |
| 1.972 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n439_s27/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n439_s27/COUT |
| 2.007 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s28/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n362_s28/COUT |
| 2.279 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n441_s17/I2 |
| 2.732 | 0.453 | tINS | FF | 2 | scaler_wrapper_inst/mode_control_inst/n441_s17/F |
| 2.969 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s11/I2 |
| 3.422 | 0.453 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s11/F |
| 3.659 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s8/I2 |
| 4.112 | 0.453 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s8/F |
| 4.349 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s6/I1 |
| 4.904 | 0.555 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s6/F |
| 5.141 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s3/I2 |
| 5.594 | 0.453 | tINS | FF | 13 | scaler_wrapper_inst/mode_control_inst/n402_s3/F |
| 5.831 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n399_s2/I0 |
| 6.348 | 0.517 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n399_s2/F |
| 6.585 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_vin_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_vin_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 115 | I_vin_clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_3_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.595, 62.815%; route: 1.896, 33.131%; tC2Q: 0.232, 4.054% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 4.242 |
| Data Arrival Time | 6.585 |
| Data Required Time | 10.828 |
| From | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1 |
| To | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1 |
| Launch Clk | I_vin_clk[R] |
| Latch Clk | I_vin_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vin_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vin_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 115 | I_vin_clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s26/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | scaler_wrapper_inst/mode_control_inst/n362_s26/COUT |
| 1.901 | 0.000 | tNET | RR | 2 | scaler_wrapper_inst/mode_control_inst/n439_s26/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | scaler_wrapper_inst/mode_control_inst/n439_s26/COUT |
| 1.937 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s27/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n362_s27/COUT |
| 1.972 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n439_s27/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n439_s27/COUT |
| 2.007 | 0.000 | tNET | FF | 2 | scaler_wrapper_inst/mode_control_inst/n362_s28/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n362_s28/COUT |
| 2.279 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n441_s17/I2 |
| 2.732 | 0.453 | tINS | FF | 2 | scaler_wrapper_inst/mode_control_inst/n441_s17/F |
| 2.969 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s11/I2 |
| 3.422 | 0.453 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s11/F |
| 3.659 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s8/I2 |
| 4.112 | 0.453 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s8/F |
| 4.349 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s6/I1 |
| 4.904 | 0.555 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s6/F |
| 5.141 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n402_s3/I2 |
| 5.594 | 0.453 | tINS | FF | 13 | scaler_wrapper_inst/mode_control_inst/n402_s3/F |
| 5.831 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/n398_s2/I0 |
| 6.348 | 0.517 | tINS | FF | 1 | scaler_wrapper_inst/mode_control_inst/n398_s2/F |
| 6.585 | 0.237 | tNET | FF | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_vin_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_vin_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 115 | I_vin_clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.595, 62.815%; route: 1.896, 33.131%; tC2Q: 0.232, 4.054% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |