Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_DVI_TX_RefDesign\project\impl\gwsynthesis\dk_video.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_DVI_TX_RefDesign\project\src\dk_video.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_DVI_TX_RefDesign\project\src\dk_video.sdc
Version	V1.9.9 Beta-6
Part Number	GW2A-LV18PG484C8/I7
Device	GW2A-18
Device Version	C
Created Time	Fri Oct 27 11:06:16 2023
Legal Announcement	Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	1114
Numbers of Endpoints Analyzed	707
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Objects
I_clk	Base	20.000	50.000	10.000			I_clk
u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk	Generated	2.692	371.429	1.346	I_clk_ibuf/I	I_clk	u_tmds_rpll/rpll_inst/CLKOUT
u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk	Generated	2.692	371.429	1.346	I_clk_ibuf/I	I_clk	u_tmds_rpll/rpll_inst/CLKOUTP
u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk	Generated	5.385	185.714	2.692	I_clk_ibuf/I	I_clk	u_tmds_rpll/rpll_inst/CLKOUTD
u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk	Generated	8.077	123.810	4.038	I_clk_ibuf/I	I_clk	u_tmds_rpll/rpll_inst/CLKOUTD3
u_clkdiv/CLKOUT.default_gen_clk	Generated	13.462	74.286	6.731	u_tmds_rpll/rpll_inst/CLKOUT	u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk	u_clkdiv/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	I_clk	50.000(MHz)	212.206(MHz)	5	TOP
2	u_clkdiv/CLKOUT.default_gen_clk	74.286(MHz)	128.278(MHz)	10	TOP

No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
I_clk	Setup	0.000	0
I_clk	Hold	0.000	0
u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0
u_clkdiv/CLKOUT.default_gen_clk	Setup	0.000	0
u_clkdiv/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	5.666	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	7.761
2	5.735	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	7.691
3	5.913	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	7.514
4	5.961	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	7.466
5	6.009	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	7.418
6	6.036	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	7.391
7	6.036	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	7.391
8	6.141	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	7.286
9	6.224	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	7.202
10	6.228	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	7.199
11	6.501	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.926
12	6.576	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.851
13	6.621	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.806
14	6.630	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.796
15	6.677	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.750
16	6.725	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.701
17	6.744	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.682
18	6.785	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.642
19	6.807	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.620
20	6.878	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.548
21	6.889	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.537
22	6.948	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.479
23	6.952	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.474
24	7.011	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.415
25	7.037	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	13.462	6.390

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.424	cnt_vs_2_s0/Q	cnt_vs_2_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.435
2	0.424	cnt_vs_6_s0/Q	cnt_vs_6_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.435
3	0.425	run_cnt_2_s0/Q	run_cnt_2_s0/D	I_clk:[R]	I_clk:[R]	0.436
4	0.425	run_cnt_5_s0/Q	run_cnt_5_s0/D	I_clk:[R]	I_clk:[R]	0.436
5	0.425	run_cnt_22_s0/Q	run_cnt_22_s0/D	I_clk:[R]	I_clk:[R]	0.436
6	0.425	run_cnt_23_s0/Q	run_cnt_23_s0/D	I_clk:[R]	I_clk:[R]	0.436
7	0.425	testpattern_inst/Color_cnt_0_s3/Q	testpattern_inst/Color_cnt_0_s3/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
8	0.425	testpattern_inst/V_cnt_15_s1/Q	testpattern_inst/V_cnt_15_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
9	0.425	testpattern_inst/Color_trig_num_15_s1/Q	testpattern_inst/Color_trig_num_15_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
10	0.425	testpattern_inst/De_cyc_vcnt_3_s1/Q	testpattern_inst/De_cyc_vcnt_3_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
11	0.425	testpattern_inst/De_cyc_vcnt_15_s1/Q	testpattern_inst/De_cyc_vcnt_15_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
12	0.425	testpattern_inst/De_cyc_hcnt_2_s1/Q	testpattern_inst/De_cyc_hcnt_2_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
13	0.425	testpattern_inst/De_cyc_hcnt_11_s1/Q	testpattern_inst/De_cyc_hcnt_11_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
14	0.425	testpattern_inst/De_cyc_hcnt_13_s1/Q	testpattern_inst/De_cyc_hcnt_13_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
15	0.425	testpattern_inst/De_cyc_hcnt_14_s1/Q	testpattern_inst/De_cyc_hcnt_14_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
16	0.425	testpattern_inst/De_vcnt_3_s1/Q	testpattern_inst/De_vcnt_3_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
17	0.425	testpattern_inst/De_vcnt_7_s1/Q	testpattern_inst/De_vcnt_7_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
18	0.425	testpattern_inst/V_cnt_10_s1/Q	testpattern_inst/V_cnt_10_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
19	0.425	testpattern_inst/H_cnt_8_s0/Q	testpattern_inst/H_cnt_8_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
20	0.425	cnt_vs_0_s1/Q	cnt_vs_0_s1/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
21	0.425	cnt_vs_8_s0/Q	cnt_vs_8_s0/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.436
22	0.427	run_cnt_0_s0/Q	run_cnt_0_s0/D	I_clk:[R]	I_clk:[R]	0.438
23	0.427	run_cnt_20_s0/Q	run_cnt_20_s0/D	I_clk:[R]	I_clk:[R]	0.438
24	0.427	run_cnt_25_s0/Q	run_cnt_25_s0/D	I_clk:[R]	I_clk:[R]	0.438
25	0.427	testpattern_inst/Color_trig_num_12_s3/Q	testpattern_inst/Color_trig_num_12_s3/D	u_clkdiv/CLKOUT.default_gen_clk:[R]	u_clkdiv/CLKOUT.default_gen_clk:[R]	0.438

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	5.654	6.654	1.000	Low Pulse Width	u_clkdiv/CLKOUT.default_gen_clk	vs_r_s0
2	5.654	6.654	1.000	Low Pulse Width	u_clkdiv/CLKOUT.default_gen_clk	cnt_vs_9_s0
3	5.654	6.654	1.000	Low Pulse Width	u_clkdiv/CLKOUT.default_gen_clk	cnt_vs_8_s0
4	5.654	6.654	1.000	Low Pulse Width	u_clkdiv/CLKOUT.default_gen_clk	cnt_vs_7_s0
5	5.654	6.654	1.000	Low Pulse Width	u_clkdiv/CLKOUT.default_gen_clk	cnt_vs_6_s0
6	5.654	6.654	1.000	Low Pulse Width	u_clkdiv/CLKOUT.default_gen_clk	testpattern_inst/O_vs_s0
7	5.654	6.654	1.000	Low Pulse Width	u_clkdiv/CLKOUT.default_gen_clk	testpattern_inst/V_cnt_0_s1
8	5.654	6.654	1.000	Low Pulse Width	u_clkdiv/CLKOUT.default_gen_clk	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0
9	5.654	6.654	1.000	Low Pulse Width	u_clkdiv/CLKOUT.default_gen_clk	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0
10	5.654	6.654	1.000	Low Pulse Width	u_clkdiv/CLKOUT.default_gen_clk	testpattern_inst/V_cnt_1_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.666
Data Arrival Time	8.333
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.925	0.423	tNET	FF	1	R23C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/I0
4.378	0.453	tINS	FF	4	R23C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/F
5.287	0.909	tNET	FF	2	R23C37[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/I1
5.658	0.371	tINS	FF	1	R23C37[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/COUT
5.658	0.000	tNET	FF	2	R23C37[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/CIN
6.128	0.470	tINS	FF	2	R23C37[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/SUM
6.525	0.397	tNET	FF	1	R23C36[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6/I0
7.095	0.570	tINS	FR	1	R23C36[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6/F
7.096	0.001	tNET	RR	1	R23C36[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/I0
7.549	0.453	tINS	RF	1	R23C36[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/F
7.962	0.413	tNET	FF	1	R22C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/I1
8.333	0.371	tINS	FF	1	R22C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/F
8.333	0.000	tNET	FF	1	R22C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R22C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK
13.999	-0.035	tSu		1	R22C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 4.368, 56.285%; route: 3.161, 40.726%; tC2Q: 0.232, 2.989%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack	5.735
Data Arrival Time	8.264
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R23C31[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/CLK
0.805	0.232	tC2Q	RF	7	R23C31[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/Q
1.306	0.501	tNET	FF	1	R21C29[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20/I0
1.876	0.570	tINS	FR	1	R21C29[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20/F
1.877	0.001	tNET	RR	1	R21C29[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/I1
2.394	0.517	tINS	RF	3	R21C29[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/F
2.819	0.425	tNET	FF	1	R22C31[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I0
3.190	0.371	tINS	FF	4	R22C31[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F
3.607	0.417	tNET	FF	1	R21C31[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/I2
4.069	0.462	tINS	FR	3	R21C31[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/F
4.071	0.003	tNET	RR	1	R21C31[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0
4.524	0.453	tINS	RF	4	R21C31[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F
5.096	0.572	tNET	FF	2	R18C31[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/I1
5.467	0.371	tINS	FF	1	R18C31[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/COUT
5.467	0.000	tNET	FF	2	R18C31[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4/CIN
5.937	0.470	tINS	FF	1	R18C31[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4/SUM
6.091	0.154	tNET	FF	1	R18C31[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/I3
6.608	0.517	tINS	FF	1	R18C31[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/F
7.171	0.563	tNET	FF	1	R17C30[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/I0
7.720	0.549	tINS	FR	1	R17C30[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/F
7.893	0.172	tNET	RR	1	R17C29[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/I1
8.264	0.371	tINS	RF	1	R17C29[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/F
8.264	0.000	tNET	FF	1	R17C29[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R17C29[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK
13.999	-0.035	tSu		1	R17C29[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 4.651, 60.472%; route: 2.808, 36.512%; tC2Q: 0.232, 3.016%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack	5.913
Data Arrival Time	8.086
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
6.444	0.887	tNET	FF	1	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/I2
6.961	0.517	tINS	FF	6	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/F
7.537	0.576	tNET	FF	1	R22C33[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n686_s0/I1
8.086	0.549	tINS	FR	1	R22C33[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n686_s0/F
8.086	0.000	tNET	RR	1	R22C33[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R22C33[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0/CLK
13.999	-0.035	tSu		1	R22C33[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.570, 47.513%; route: 3.712, 49.399%; tC2Q: 0.232, 3.088%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack	5.961
Data Arrival Time	8.038
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
6.444	0.887	tNET	FF	1	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/I2
6.961	0.517	tINS	FF	6	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/F
7.667	0.707	tNET	FF	1	R25C37[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0/I0
8.038	0.371	tINS	FF	1	R25C37[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0/F
8.038	0.000	tNET	FF	1	R25C37[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R25C37[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/CLK
13.999	-0.035	tSu		1	R25C37[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.392, 45.434%; route: 3.842, 51.458%; tC2Q: 0.232, 3.108%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack	6.009
Data Arrival Time	7.990
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
6.444	0.887	tNET	FF	1	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/I2
6.961	0.517	tINS	FF	6	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/F
7.528	0.567	tNET	FF	1	R22C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s1/I2
7.990	0.462	tINS	FR	1	R22C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s1/F
7.990	0.000	tNET	RR	1	R22C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R22C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/CLK
13.999	-0.035	tSu		1	R22C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.483, 46.956%; route: 3.703, 49.917%; tC2Q: 0.232, 3.128%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack	6.036
Data Arrival Time	7.963
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
6.444	0.887	tNET	FF	1	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/I2
6.961	0.517	tINS	FF	6	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/F
7.393	0.432	tNET	FF	1	R24C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n687_s1/I1
7.963	0.570	tINS	FR	1	R24C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n687_s1/F
7.963	0.000	tNET	RR	1	R24C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R24C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/CLK
13.999	-0.035	tSu		1	R24C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.591, 48.589%; route: 3.568, 48.272%; tC2Q: 0.232, 3.139%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack	6.036
Data Arrival Time	7.963
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
6.444	0.887	tNET	FF	1	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/I2
6.961	0.517	tINS	FF	6	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/F
7.393	0.432	tNET	FF	1	R24C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0/I1
7.963	0.570	tINS	FR	1	R24C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0/F
7.963	0.000	tNET	RR	1	R24C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R24C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/CLK
13.999	-0.035	tSu		1	R24C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.591, 48.589%; route: 3.568, 48.272%; tC2Q: 0.232, 3.139%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack	6.141
Data Arrival Time	7.859
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
6.444	0.887	tNET	FF	1	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/I2
6.961	0.517	tINS	FF	6	R23C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/F
7.397	0.436	tNET	FF	1	R24C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s1/I1
7.859	0.462	tINS	FR	1	R24C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s1/F
7.859	0.000	tNET	RR	1	R24C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R24C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0/CLK
13.999	-0.035	tSu		1	R24C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.483, 47.805%; route: 3.571, 49.011%; tC2Q: 0.232, 3.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack	6.224
Data Arrival Time	7.775
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
6.371	0.815	tNET	FF	1	R22C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1/I2
6.824	0.453	tINS	FF	2	R22C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1/F
7.226	0.401	tNET	FF	1	R22C32[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n688_s0/I2
7.775	0.549	tINS	FR	1	R22C32[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n688_s0/F
7.775	0.000	tNET	RR	1	R22C32[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R22C32[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0/CLK
13.999	-0.035	tSu		1	R22C32[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.506, 48.680%; route: 3.464, 48.098%; tC2Q: 0.232, 3.221%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack	6.228
Data Arrival Time	7.772
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK
0.805	0.232	tC2Q	RF	5	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q
1.241	0.436	tNET	FF	1	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/I0
1.758	0.517	tINS	FF	4	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/F
2.185	0.428	tNET	FF	1	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/I2
2.702	0.517	tINS	FF	5	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/F
3.140	0.438	tNET	FF	1	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/I1
3.710	0.570	tINS	FR	3	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/F
3.714	0.004	tNET	RR	1	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I3
4.269	0.555	tINS	RF	5	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F
4.778	0.509	tNET	FF	2	R20C38[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/I1
5.149	0.371	tINS	FF	1	R20C38[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/COUT
5.149	0.000	tNET	FF	2	R20C38[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/CIN
5.619	0.470	tINS	FF	1	R20C38[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/SUM
6.275	0.656	tNET	FF	1	R18C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6/I3
6.737	0.462	tINS	FR	1	R18C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6/F
6.738	0.001	tNET	RR	1	R18C35[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/I0
7.308	0.570	tINS	RR	1	R18C35[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/F
7.310	0.001	tNET	RR	1	R18C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/I1
7.772	0.462	tINS	RR	1	R18C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/F
7.772	0.000	tNET	RR	1	R18C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R18C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK
13.999	-0.035	tSu		1	R18C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 4.494, 62.427%; route: 2.473, 34.351%; tC2Q: 0.232, 3.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack	6.501
Data Arrival Time	7.499
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.925	0.423	tNET	FF	1	R23C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/I0
4.378	0.453	tINS	FF	4	R23C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/F
5.287	0.909	tNET	FF	2	R23C37[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/I1
5.658	0.371	tINS	FF	3	R23C37[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/SUM
5.915	0.257	tNET	FF	1	R23C35[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4/I0
6.485	0.570	tINS	FR	1	R23C35[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4/F
6.486	0.001	tNET	RR	1	R23C35[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3/I2
7.035	0.549	tINS	RR	1	R23C35[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3/F
7.037	0.001	tNET	RR	1	R23C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1/I1
7.499	0.462	tINS	RR	1	R23C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1/F
7.499	0.000	tNET	RR	1	R23C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R23C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/CLK
13.999	-0.035	tSu		1	R23C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 4.085, 58.981%; route: 2.609, 37.670%; tC2Q: 0.232, 3.350%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack	6.576
Data Arrival Time	7.424
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R23C31[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/CLK
0.805	0.232	tC2Q	RF	7	R23C31[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/Q
1.306	0.501	tNET	FF	1	R21C29[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20/I0
1.876	0.570	tINS	FR	1	R21C29[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20/F
1.877	0.001	tNET	RR	1	R21C29[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/I1
2.394	0.517	tINS	RF	3	R21C29[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/F
2.819	0.425	tNET	FF	1	R22C31[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I0
3.190	0.371	tINS	FF	4	R22C31[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F
3.607	0.417	tNET	FF	1	R21C31[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/I2
4.069	0.462	tINS	FR	3	R21C31[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/F
4.071	0.003	tNET	RR	1	R21C31[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0
4.524	0.453	tINS	RF	4	R21C31[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F
5.096	0.572	tNET	FF	2	R21C30[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3/I1
5.467	0.371	tINS	FF	2	R21C30[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3/SUM
6.132	0.665	tNET	FF	1	R18C29[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2/I0
6.681	0.549	tINS	FR	1	R18C29[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2/F
6.854	0.172	tNET	RR	1	R17C29[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/I0
7.424	0.570	tINS	RR	1	R17C29[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/F
7.424	0.000	tNET	RR	1	R17C29[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R17C29[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/CLK
13.999	-0.035	tSu		1	R17C29[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.863, 56.387%; route: 2.756, 40.227%; tC2Q: 0.232, 3.386%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack	6.621
Data Arrival Time	7.378
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
6.371	0.815	tNET	FF	1	R22C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1/I2
6.833	0.462	tINS	FR	2	R22C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1/F
7.007	0.174	tNET	RR	1	R22C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0/I1
7.378	0.371	tINS	RF	1	R22C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0/F
7.378	0.000	tNET	FF	1	R22C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R22C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/CLK
13.999	-0.035	tSu		1	R22C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.337, 49.033%; route: 3.237, 47.558%; tC2Q: 0.232, 3.409%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack	6.630
Data Arrival Time	7.369
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK
0.805	0.232	tC2Q	RF	5	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q
1.241	0.436	tNET	FF	1	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/I0
1.758	0.517	tINS	FF	4	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/F
2.163	0.406	tNET	FF	1	R20C33[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s2/I2
2.733	0.570	tINS	FR	3	R20C33[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s2/F
2.910	0.177	tNET	RR	1	R20C34[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16/I3
3.465	0.555	tINS	RF	5	R20C34[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16/F
3.487	0.022	tNET	FF	1	R20C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20/I3
3.940	0.453	tINS	FF	4	R20C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20/F
4.755	0.815	tNET	FF	2	R21C37[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n134_s/I1
5.126	0.371	tINS	FF	1	R21C37[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n134_s/COUT
5.126	0.000	tNET	FF	2	R21C37[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n133_s/CIN
5.596	0.470	tINS	FF	2	R21C37[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n133_s/SUM
6.257	0.662	tNET	FF	1	R18C35[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3/I0
6.628	0.371	tINS	FF	1	R18C35[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3/F
6.799	0.170	tNET	FF	1	R18C36[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1/I1
7.369	0.570	tINS	FR	1	R18C36[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1/F
7.369	0.000	tNET	RR	1	R18C36[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R18C36[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/CLK
13.999	-0.035	tSu		1	R18C36[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.877, 57.048%; route: 2.687, 39.539%; tC2Q: 0.232, 3.414%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack	6.677
Data Arrival Time	7.323
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK
0.805	0.232	tC2Q	RF	5	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q
1.241	0.436	tNET	FF	1	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/I0
1.758	0.517	tINS	FF	4	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/F
2.185	0.428	tNET	FF	1	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/I2
2.702	0.517	tINS	FF	5	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/F
3.140	0.438	tNET	FF	1	R20C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I1
3.710	0.570	tINS	FR	1	R20C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F
3.712	0.001	tNET	RR	1	R20C34[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1/I3
4.229	0.517	tINS	RF	2	R20C34[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1/F
4.876	0.648	tNET	FF	1	R18C35[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0/I0
5.247	0.371	tINS	FF	8	R18C35[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0/F
5.822	0.575	tNET	FF	1	R20C36[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0/I2
6.339	0.517	tINS	FF	1	R20C36[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0/F
6.753	0.413	tNET	FF	1	R18C37[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2/I1
7.323	0.570	tINS	FR	1	R18C37[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2/F
7.323	0.000	tNET	RR	1	R18C37[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R18C37[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0/CLK
13.999	-0.035	tSu		1	R18C37[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.579, 53.023%; route: 2.939, 43.539%; tC2Q: 0.232, 3.437%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack	6.725
Data Arrival Time	7.274
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
5.745	0.188	tNET	FF	1	R22C34[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n679_s1/I1
6.198	0.453	tINS	FF	1	R22C34[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n679_s1/F
6.198	0.000	tNET	FF	1	R22C34[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n679_s0/I0
6.301	0.103	tINS	FF	1	R22C34[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n679_s0/O
6.704	0.403	tNET	FF	1	R22C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n689_s0/I1
7.274	0.570	tINS	FR	1	R22C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n689_s0/F
7.274	0.000	tNET	RR	1	R22C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R22C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0/CLK
13.999	-0.035	tSu		1	R22C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.630, 54.169%; route: 2.839, 42.369%; tC2Q: 0.232, 3.462%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack	6.744
Data Arrival Time	7.255
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
6.222	0.665	tNET	FF	1	R23C37[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n596_s0/I2
6.792	0.570	tINS	FR	1	R23C37[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n596_s0/F
6.793	0.001	tNET	RR	1	R23C37[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n606_s2/I1
7.255	0.462	tINS	RR	1	R23C37[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n606_s2/F
7.255	0.000	tNET	RR	1	R23C37[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R23C37[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0/CLK
13.999	-0.035	tSu		1	R23C37[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.536, 52.917%; route: 2.914, 43.611%; tC2Q: 0.232, 3.472%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack	6.785
Data Arrival Time	7.215
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK
0.805	0.232	tC2Q	RF	5	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q
1.241	0.436	tNET	FF	1	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/I0
1.758	0.517	tINS	FF	4	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/F
2.185	0.428	tNET	FF	1	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/I2
2.702	0.517	tINS	FF	5	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/F
3.140	0.438	tNET	FF	1	R20C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I1
3.710	0.570	tINS	FR	1	R20C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F
3.712	0.001	tNET	RR	1	R20C34[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1/I3
4.229	0.517	tINS	RF	2	R20C34[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1/F
4.876	0.648	tNET	FF	1	R18C35[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0/I0
5.247	0.371	tINS	FF	8	R18C35[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0/F
5.822	0.575	tNET	FF	1	R20C36[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/I2
6.339	0.517	tINS	FF	1	R20C36[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/F
6.753	0.413	tNET	FF	1	R18C36[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/I0
7.215	0.462	tINS	FR	1	R18C36[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/F
7.215	0.000	tNET	RR	1	R18C36[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R18C36[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0/CLK
13.999	-0.035	tSu		1	R18C36[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.471, 52.260%; route: 2.939, 44.247%; tC2Q: 0.232, 3.493%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack	6.807
Data Arrival Time	7.192
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
0.805	0.232	tC2Q	RF	6	R24C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
1.235	0.430	tNET	FF	1	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/I0
1.805	0.570	tINS	FR	3	R22C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3/F
1.979	0.174	tNET	RR	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/I3
2.534	0.555	tINS	RF	1	R22C32[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19/F
2.947	0.413	tNET	FF	1	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I3
3.502	0.555	tINS	FF	4	R22C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.919	0.418	tNET	FF	1	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I2
4.372	0.453	tINS	FF	2	R23C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
5.186	0.814	tNET	FF	1	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
5.557	0.371	tINS	FF	7	R23C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
5.988	0.431	tNET	FF	1	R22C35[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n605_s2/I2
6.558	0.570	tINS	FR	1	R22C35[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n605_s2/F
6.730	0.172	tNET	RR	1	R23C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n605_s1/I0
7.192	0.462	tINS	RR	1	R23C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n605_s1/F
7.192	0.000	tNET	RR	1	R23C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R23C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0/CLK
13.999	-0.035	tSu		1	R23C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.536, 53.416%; route: 2.852, 43.079%; tC2Q: 0.232, 3.505%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack	6.878
Data Arrival Time	7.121
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R23C31[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/CLK
0.805	0.232	tC2Q	RF	7	R23C31[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/Q
1.306	0.501	tNET	FF	1	R21C29[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20/I0
1.876	0.570	tINS	FR	1	R21C29[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20/F
1.877	0.001	tNET	RR	1	R21C29[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/I1
2.394	0.517	tINS	RF	3	R21C29[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/F
2.819	0.425	tNET	FF	1	R22C31[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I0
3.190	0.371	tINS	FF	4	R22C31[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F
3.607	0.417	tNET	FF	1	R21C31[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I0
4.060	0.453	tINS	FF	2	R21C31[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F
4.555	0.496	tNET	FF	1	R17C31[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1
5.008	0.453	tINS	FF	8	R17C31[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F
5.697	0.688	tNET	FF	1	R20C29[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1/I2
6.150	0.453	tINS	FF	2	R20C29[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1/F
6.551	0.401	tNET	FF	1	R22C29[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0/I1
7.121	0.570	tINS	FR	1	R22C29[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0/F
7.121	0.000	tNET	RR	1	R22C29[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R22C29[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0/CLK
13.999	-0.035	tSu		1	R22C29[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.387, 51.722%; route: 2.929, 44.735%; tC2Q: 0.232, 3.543%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack	6.889
Data Arrival Time	7.110
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK
0.805	0.232	tC2Q	RF	5	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q
1.241	0.436	tNET	FF	1	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/I0
1.758	0.517	tINS	FF	4	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/F
2.185	0.428	tNET	FF	1	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/I2
2.702	0.517	tINS	FF	5	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/F
3.140	0.438	tNET	FF	1	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/I1
3.710	0.570	tINS	FR	3	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/F
3.714	0.004	tNET	RR	1	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I3
4.269	0.555	tINS	RF	5	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F
4.696	0.426	tNET	FF	1	R18C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0/I0
5.251	0.555	tINS	FF	8	R18C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0/F
5.517	0.266	tNET	FF	1	R18C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3/I0
6.072	0.555	tINS	FF	5	R18C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3/F
6.648	0.576	tNET	FF	1	R17C35[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s1/I2
7.110	0.462	tINS	FR	1	R17C35[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s1/F
7.110	0.000	tNET	RR	1	R17C35[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R17C35[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0/CLK
13.999	-0.035	tSu		1	R17C35[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.731, 57.072%; route: 2.574, 39.379%; tC2Q: 0.232, 3.549%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack	6.948
Data Arrival Time	7.051
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK
0.805	0.232	tC2Q	RF	5	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q
1.241	0.436	tNET	FF	1	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/I0
1.758	0.517	tINS	FF	4	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/F
2.185	0.428	tNET	FF	1	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/I2
2.702	0.517	tINS	FF	5	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/F
3.140	0.438	tNET	FF	1	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/I1
3.710	0.570	tINS	FR	3	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/F
3.714	0.004	tNET	RR	1	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I3
4.269	0.555	tINS	RF	5	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F
4.696	0.426	tNET	FF	1	R18C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0/I0
5.251	0.555	tINS	FF	8	R18C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0/F
5.832	0.582	tNET	FF	1	R18C34[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n679_s0/S0
6.083	0.251	tINS	FF	1	R18C34[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n679_s0/O
6.502	0.419	tNET	FF	1	R17C35[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0/I0
7.051	0.549	tINS	FR	1	R17C35[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0/F
7.051	0.000	tNET	RR	1	R17C35[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R17C35[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/CLK
13.999	-0.035	tSu		1	R17C35[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.514, 54.239%; route: 2.733, 42.180%; tC2Q: 0.232, 3.581%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack	6.952
Data Arrival Time	7.047
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK
0.805	0.232	tC2Q	RF	5	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q
1.241	0.436	tNET	FF	1	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/I0
1.758	0.517	tINS	FF	4	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/F
2.185	0.428	tNET	FF	1	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/I2
2.702	0.517	tINS	FF	5	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/F
3.140	0.438	tNET	FF	1	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/I1
3.710	0.570	tINS	FR	3	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/F
3.714	0.004	tNET	RR	1	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I3
4.269	0.555	tINS	RF	5	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F
4.696	0.426	tNET	FF	1	R18C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0/I0
5.251	0.555	tINS	FF	8	R18C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0/F
5.517	0.266	tNET	FF	1	R18C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3/I0
6.072	0.555	tINS	FF	5	R18C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3/F
6.498	0.427	tNET	FF	1	R17C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n687_s1/I1
7.047	0.549	tINS	FR	1	R17C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n687_s1/F
7.047	0.000	tNET	RR	1	R17C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R17C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0/CLK
13.999	-0.035	tSu		1	R17C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.818, 58.970%; route: 2.424, 37.447%; tC2Q: 0.232, 3.583%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack	7.011
Data Arrival Time	6.988
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK
0.805	0.232	tC2Q	RF	5	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q
1.241	0.436	tNET	FF	1	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/I0
1.758	0.517	tINS	FF	4	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/F
2.185	0.428	tNET	FF	1	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/I2
2.702	0.517	tINS	FF	5	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/F
3.140	0.438	tNET	FF	1	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/I1
3.710	0.570	tINS	FR	3	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/F
3.714	0.004	tNET	RR	1	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I3
4.269	0.555	tINS	RF	5	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F
4.696	0.426	tNET	FF	1	R18C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0/I0
5.251	0.555	tINS	FF	8	R18C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0/F
5.683	0.432	tNET	FF	1	R18C34[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n682_s1/I0
6.200	0.517	tINS	FF	2	R18C34[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n682_s1/F
6.617	0.418	tNET	FF	1	R17C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n688_s0/I2
6.988	0.371	tINS	FF	1	R17C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n688_s0/F
6.988	0.000	tNET	FF	1	R17C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R17C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0/CLK
13.999	-0.035	tSu		1	R17C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.602, 56.145%; route: 2.581, 40.238%; tC2Q: 0.232, 3.616%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack	7.037
Data Arrival Time	6.963
Data Required Time	13.999
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.573	0.243	tNET	RR	1	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK
0.805	0.232	tC2Q	RF	5	R21C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q
1.241	0.436	tNET	FF	1	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/I0
1.758	0.517	tINS	FF	4	R18C33[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5/F
2.185	0.428	tNET	FF	1	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/I2
2.702	0.517	tINS	FF	5	R21C33[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/F
3.140	0.438	tNET	FF	1	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/I1
3.710	0.570	tINS	FR	3	R20C34[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s18/F
3.714	0.004	tNET	RR	1	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I3
4.269	0.555	tINS	RF	5	R20C34[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F
4.696	0.426	tNET	FF	1	R18C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0/I0
5.251	0.555	tINS	FF	8	R18C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0/F
5.517	0.266	tNET	FF	1	R18C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3/I0
6.072	0.555	tINS	FF	5	R18C34[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3/F
6.501	0.429	tNET	FF	1	R17C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n686_s0/I1
6.963	0.462	tINS	FR	1	R17C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n686_s0/F
6.963	0.000	tNET	RR	1	R17C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.462	13.462					active clock edge time
13.462	0.000					u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
14.034	0.243	tNET	RR	1	R17C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0/CLK
13.999	-0.035	tSu		1	R17C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.462
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.731, 58.389%; route: 2.427, 37.980%; tC2Q: 0.232, 3.631%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.424
Data Arrival Time	0.949
Data Required Time	0.525
From	cnt_vs_2_s0
To	cnt_vs_2_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R17C39[1][A]	cnt_vs_2_s0/CLK
0.716	0.202	tC2Q	RR	1	R17C39[1][A]	cnt_vs_2_s0/Q
0.717	0.001	tNET	RR	2	R17C39[1][A]	n153_s/I1
0.949	0.232	tINS	RF	1	R17C39[1][A]	n153_s/SUM
0.949	0.000	tNET	FF	1	R17C39[1][A]	cnt_vs_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R17C39[1][A]	cnt_vs_2_s0/CLK
0.525	0.011	tHld		1	R17C39[1][A]	cnt_vs_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack	0.424
Data Arrival Time	0.949
Data Required Time	0.525
From	cnt_vs_6_s0
To	cnt_vs_6_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R17C40[0][A]	cnt_vs_6_s0/CLK
0.716	0.202	tC2Q	RR	1	R17C40[0][A]	cnt_vs_6_s0/Q
0.717	0.001	tNET	RR	2	R17C40[0][A]	n149_s/I1
0.949	0.232	tINS	RF	1	R17C40[0][A]	n149_s/SUM
0.949	0.000	tNET	FF	1	R17C40[0][A]	cnt_vs_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R17C40[0][A]	cnt_vs_6_s0/CLK
0.525	0.011	tHld		1	R17C40[0][A]	cnt_vs_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	run_cnt_2_s0
To	run_cnt_2_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C39[1][A]	run_cnt_2_s0/CLK
1.062	0.202	tC2Q	RR	3	R22C39[1][A]	run_cnt_2_s0/Q
1.064	0.002	tNET	RR	1	R22C39[1][A]	n70_s4/I0
1.296	0.232	tINS	RF	1	R22C39[1][A]	n70_s4/F
1.296	0.000	tNET	FF	1	R22C39[1][A]	run_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C39[1][A]	run_cnt_2_s0/CLK
0.871	0.011	tHld		1	R22C39[1][A]	run_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	run_cnt_5_s0
To	run_cnt_5_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C39[0][A]	run_cnt_5_s0/CLK
1.062	0.202	tC2Q	RR	4	R23C39[0][A]	run_cnt_5_s0/Q
1.064	0.002	tNET	RR	1	R23C39[0][A]	n67_s2/I2
1.296	0.232	tINS	RF	1	R23C39[0][A]	n67_s2/F
1.296	0.000	tNET	FF	1	R23C39[0][A]	run_cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C39[0][A]	run_cnt_5_s0/CLK
0.871	0.011	tHld		1	R23C39[0][A]	run_cnt_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	run_cnt_22_s0
To	run_cnt_22_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C40[0][A]	run_cnt_22_s0/CLK
1.062	0.202	tC2Q	RR	2	R24C40[0][A]	run_cnt_22_s0/Q
1.064	0.002	tNET	RR	1	R24C40[0][A]	n50_s2/I2
1.296	0.232	tINS	RF	1	R24C40[0][A]	n50_s2/F
1.296	0.000	tNET	FF	1	R24C40[0][A]	run_cnt_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C40[0][A]	run_cnt_22_s0/CLK
0.871	0.011	tHld		1	R24C40[0][A]	run_cnt_22_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	run_cnt_23_s0
To	run_cnt_23_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C39[1][A]	run_cnt_23_s0/CLK
1.062	0.202	tC2Q	RR	4	R24C39[1][A]	run_cnt_23_s0/Q
1.064	0.002	tNET	RR	1	R24C39[1][A]	n49_s2/I2
1.296	0.232	tINS	RF	1	R24C39[1][A]	n49_s2/F
1.296	0.000	tNET	FF	1	R24C39[1][A]	run_cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C39[1][A]	run_cnt_23_s0/CLK
0.871	0.011	tHld		1	R24C39[1][A]	run_cnt_23_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/Color_cnt_0_s3
To	testpattern_inst/Color_cnt_0_s3
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R30C29[1][A]	testpattern_inst/Color_cnt_0_s3/CLK
0.716	0.202	tC2Q	RR	5	R30C29[1][A]	testpattern_inst/Color_cnt_0_s3/Q
0.718	0.002	tNET	RR	1	R30C29[1][A]	testpattern_inst/n918_s4/I2
0.950	0.232	tINS	RF	1	R30C29[1][A]	testpattern_inst/n918_s4/F
0.950	0.000	tNET	FF	1	R30C29[1][A]	testpattern_inst/Color_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R30C29[1][A]	testpattern_inst/Color_cnt_0_s3/CLK
0.525	0.011	tHld		1	R30C29[1][A]	testpattern_inst/Color_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/V_cnt_15_s1
To	testpattern_inst/V_cnt_15_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R29C39[1][A]	testpattern_inst/V_cnt_15_s1/CLK
0.716	0.202	tC2Q	RR	2	R29C39[1][A]	testpattern_inst/V_cnt_15_s1/Q
0.718	0.002	tNET	RR	1	R29C39[1][A]	testpattern_inst/n79_s2/I1
0.950	0.232	tINS	RF	1	R29C39[1][A]	testpattern_inst/n79_s2/F
0.950	0.000	tNET	FF	1	R29C39[1][A]	testpattern_inst/V_cnt_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R29C39[1][A]	testpattern_inst/V_cnt_15_s1/CLK
0.525	0.011	tHld		1	R29C39[1][A]	testpattern_inst/V_cnt_15_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/Color_trig_num_15_s1
To	testpattern_inst/Color_trig_num_15_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R27C29[1][A]	testpattern_inst/Color_trig_num_15_s1/CLK
0.716	0.202	tC2Q	RR	3	R27C29[1][A]	testpattern_inst/Color_trig_num_15_s1/Q
0.718	0.002	tNET	RR	1	R27C29[1][A]	testpattern_inst/n816_s1/I2
0.950	0.232	tINS	RF	1	R27C29[1][A]	testpattern_inst/n816_s1/F
0.950	0.000	tNET	FF	1	R27C29[1][A]	testpattern_inst/Color_trig_num_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R27C29[1][A]	testpattern_inst/Color_trig_num_15_s1/CLK
0.525	0.011	tHld		1	R27C29[1][A]	testpattern_inst/Color_trig_num_15_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/De_cyc_vcnt_3_s1
To	testpattern_inst/De_cyc_vcnt_3_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R32C40[0][A]	testpattern_inst/De_cyc_vcnt_3_s1/CLK
0.716	0.202	tC2Q	RR	3	R32C40[0][A]	testpattern_inst/De_cyc_vcnt_3_s1/Q
0.718	0.002	tNET	RR	1	R32C40[0][A]	testpattern_inst/n756_s2/I2
0.950	0.232	tINS	RF	1	R32C40[0][A]	testpattern_inst/n756_s2/F
0.950	0.000	tNET	FF	1	R32C40[0][A]	testpattern_inst/De_cyc_vcnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R32C40[0][A]	testpattern_inst/De_cyc_vcnt_3_s1/CLK
0.525	0.011	tHld		1	R32C40[0][A]	testpattern_inst/De_cyc_vcnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path11

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/De_cyc_vcnt_15_s1
To	testpattern_inst/De_cyc_vcnt_15_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R31C39[1][A]	testpattern_inst/De_cyc_vcnt_15_s1/CLK
0.716	0.202	tC2Q	RR	2	R31C39[1][A]	testpattern_inst/De_cyc_vcnt_15_s1/Q
0.718	0.002	tNET	RR	1	R31C39[1][A]	testpattern_inst/n744_s2/I3
0.950	0.232	tINS	RF	1	R31C39[1][A]	testpattern_inst/n744_s2/F
0.950	0.000	tNET	FF	1	R31C39[1][A]	testpattern_inst/De_cyc_vcnt_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R31C39[1][A]	testpattern_inst/De_cyc_vcnt_15_s1/CLK
0.525	0.011	tHld		1	R31C39[1][A]	testpattern_inst/De_cyc_vcnt_15_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path12

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/De_cyc_hcnt_2_s1
To	testpattern_inst/De_cyc_hcnt_2_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R32C29[0][A]	testpattern_inst/De_cyc_hcnt_2_s1/CLK
0.716	0.202	tC2Q	RR	4	R32C29[0][A]	testpattern_inst/De_cyc_hcnt_2_s1/Q
0.718	0.002	tNET	RR	1	R32C29[0][A]	testpattern_inst/n637_s4/I0
0.950	0.232	tINS	RF	1	R32C29[0][A]	testpattern_inst/n637_s4/F
0.950	0.000	tNET	FF	1	R32C29[0][A]	testpattern_inst/De_cyc_hcnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R32C29[0][A]	testpattern_inst/De_cyc_hcnt_2_s1/CLK
0.525	0.011	tHld		1	R32C29[0][A]	testpattern_inst/De_cyc_hcnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path13

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/De_cyc_hcnt_11_s1
To	testpattern_inst/De_cyc_hcnt_11_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R31C29[1][A]	testpattern_inst/De_cyc_hcnt_11_s1/CLK
0.716	0.202	tC2Q	RR	3	R31C29[1][A]	testpattern_inst/De_cyc_hcnt_11_s1/Q
0.718	0.002	tNET	RR	1	R31C29[1][A]	testpattern_inst/n628_s2/I0
0.950	0.232	tINS	RF	1	R31C29[1][A]	testpattern_inst/n628_s2/F
0.950	0.000	tNET	FF	1	R31C29[1][A]	testpattern_inst/De_cyc_hcnt_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R31C29[1][A]	testpattern_inst/De_cyc_hcnt_11_s1/CLK
0.525	0.011	tHld		1	R31C29[1][A]	testpattern_inst/De_cyc_hcnt_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path14

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/De_cyc_hcnt_13_s1
To	testpattern_inst/De_cyc_hcnt_13_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R31C29[0][A]	testpattern_inst/De_cyc_hcnt_13_s1/CLK
0.716	0.202	tC2Q	RR	4	R31C29[0][A]	testpattern_inst/De_cyc_hcnt_13_s1/Q
0.718	0.002	tNET	RR	1	R31C29[0][A]	testpattern_inst/n626_s2/I3
0.950	0.232	tINS	RF	1	R31C29[0][A]	testpattern_inst/n626_s2/F
0.950	0.000	tNET	FF	1	R31C29[0][A]	testpattern_inst/De_cyc_hcnt_13_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R31C29[0][A]	testpattern_inst/De_cyc_hcnt_13_s1/CLK
0.525	0.011	tHld		1	R31C29[0][A]	testpattern_inst/De_cyc_hcnt_13_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path15

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/De_cyc_hcnt_14_s1
To	testpattern_inst/De_cyc_hcnt_14_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R32C30[1][A]	testpattern_inst/De_cyc_hcnt_14_s1/CLK
0.716	0.202	tC2Q	RR	3	R32C30[1][A]	testpattern_inst/De_cyc_hcnt_14_s1/Q
0.718	0.002	tNET	RR	1	R32C30[1][A]	testpattern_inst/n625_s2/I3
0.950	0.232	tINS	RF	1	R32C30[1][A]	testpattern_inst/n625_s2/F
0.950	0.000	tNET	FF	1	R32C30[1][A]	testpattern_inst/De_cyc_hcnt_14_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R32C30[1][A]	testpattern_inst/De_cyc_hcnt_14_s1/CLK
0.525	0.011	tHld		1	R32C30[1][A]	testpattern_inst/De_cyc_hcnt_14_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path16

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/De_vcnt_3_s1
To	testpattern_inst/De_vcnt_3_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R30C35[0][A]	testpattern_inst/De_vcnt_3_s1/CLK
0.716	0.202	tC2Q	RR	3	R30C35[0][A]	testpattern_inst/De_vcnt_3_s1/Q
0.718	0.002	tNET	RR	1	R30C35[0][A]	testpattern_inst/n516_s2/I3
0.950	0.232	tINS	RF	1	R30C35[0][A]	testpattern_inst/n516_s2/F
0.950	0.000	tNET	FF	1	R30C35[0][A]	testpattern_inst/De_vcnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R30C35[0][A]	testpattern_inst/De_vcnt_3_s1/CLK
0.525	0.011	tHld		1	R30C35[0][A]	testpattern_inst/De_vcnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/De_vcnt_7_s1
To	testpattern_inst/De_vcnt_7_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R29C36[1][A]	testpattern_inst/De_vcnt_7_s1/CLK
0.716	0.202	tC2Q	RR	3	R29C36[1][A]	testpattern_inst/De_vcnt_7_s1/Q
0.718	0.002	tNET	RR	1	R29C36[1][A]	testpattern_inst/n512_s2/I3
0.950	0.232	tINS	RF	1	R29C36[1][A]	testpattern_inst/n512_s2/F
0.950	0.000	tNET	FF	1	R29C36[1][A]	testpattern_inst/De_vcnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R29C36[1][A]	testpattern_inst/De_vcnt_7_s1/CLK
0.525	0.011	tHld		1	R29C36[1][A]	testpattern_inst/De_vcnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/V_cnt_10_s1
To	testpattern_inst/V_cnt_10_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R29C38[0][A]	testpattern_inst/V_cnt_10_s1/CLK
0.716	0.202	tC2Q	RR	4	R29C38[0][A]	testpattern_inst/V_cnt_10_s1/Q
0.718	0.002	tNET	RR	1	R29C38[0][A]	testpattern_inst/n84_s2/I3
0.950	0.232	tINS	RF	1	R29C38[0][A]	testpattern_inst/n84_s2/F
0.950	0.000	tNET	FF	1	R29C38[0][A]	testpattern_inst/V_cnt_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R29C38[0][A]	testpattern_inst/V_cnt_10_s1/CLK
0.525	0.011	tHld		1	R29C38[0][A]	testpattern_inst/V_cnt_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	testpattern_inst/H_cnt_8_s0
To	testpattern_inst/H_cnt_8_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R25C38[1][A]	testpattern_inst/H_cnt_8_s0/CLK
0.716	0.202	tC2Q	RR	4	R25C38[1][A]	testpattern_inst/H_cnt_8_s0/Q
0.718	0.002	tNET	RR	1	R25C38[1][A]	testpattern_inst/n172_s2/I3
0.950	0.232	tINS	RF	1	R25C38[1][A]	testpattern_inst/n172_s2/F
0.950	0.000	tNET	FF	1	R25C38[1][A]	testpattern_inst/H_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R25C38[1][A]	testpattern_inst/H_cnt_8_s0/CLK
0.525	0.011	tHld		1	R25C38[1][A]	testpattern_inst/H_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path20

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	cnt_vs_0_s1
To	cnt_vs_0_s1
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R18C39[0][A]	cnt_vs_0_s1/CLK
0.716	0.202	tC2Q	RR	2	R18C39[0][A]	cnt_vs_0_s1/Q
0.718	0.002	tNET	RR	1	R18C39[0][A]	n155_s3/I0
0.950	0.232	tINS	RF	1	R18C39[0][A]	n155_s3/F
0.950	0.000	tNET	FF	1	R18C39[0][A]	cnt_vs_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R18C39[0][A]	cnt_vs_0_s1/CLK
0.525	0.011	tHld		1	R18C39[0][A]	cnt_vs_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path21

Path Summary:

Slack	0.425
Data Arrival Time	0.950
Data Required Time	0.525
From	cnt_vs_8_s0
To	cnt_vs_8_s0
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R17C40[1][A]	cnt_vs_8_s0/CLK
0.716	0.202	tC2Q	RR	26	R17C40[1][A]	cnt_vs_8_s0/Q
0.718	0.002	tNET	RR	2	R17C40[1][A]	n147_s/I1
0.950	0.232	tINS	RF	1	R17C40[1][A]	n147_s/SUM
0.950	0.000	tNET	FF	1	R17C40[1][A]	cnt_vs_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R17C40[1][A]	cnt_vs_8_s0/CLK
0.525	0.011	tHld		1	R17C40[1][A]	cnt_vs_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path22

Path Summary:

Slack	0.427
Data Arrival Time	1.297
Data Required Time	0.871
From	run_cnt_0_s0
To	run_cnt_0_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C40[1][A]	run_cnt_0_s0/CLK
1.062	0.202	tC2Q	RR	5	R22C40[1][A]	run_cnt_0_s0/Q
1.065	0.004	tNET	RR	1	R22C40[1][A]	n72_s2/I0
1.297	0.232	tINS	RF	1	R22C40[1][A]	n72_s2/F
1.297	0.000	tNET	FF	1	R22C40[1][A]	run_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C40[1][A]	run_cnt_0_s0/CLK
0.871	0.011	tHld		1	R22C40[1][A]	run_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	0.427
Data Arrival Time	1.297
Data Required Time	0.871
From	run_cnt_20_s0
To	run_cnt_20_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C40[1][A]	run_cnt_20_s0/CLK
1.062	0.202	tC2Q	RR	4	R24C40[1][A]	run_cnt_20_s0/Q
1.065	0.004	tNET	RR	1	R24C40[1][A]	n52_s2/I0
1.297	0.232	tINS	RF	1	R24C40[1][A]	n52_s2/F
1.297	0.000	tNET	FF	1	R24C40[1][A]	run_cnt_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C40[1][A]	run_cnt_20_s0/CLK
0.871	0.011	tHld		1	R24C40[1][A]	run_cnt_20_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	0.427
Data Arrival Time	1.297
Data Required Time	0.871
From	run_cnt_25_s0
To	run_cnt_25_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C39[0][A]	run_cnt_25_s0/CLK
1.062	0.202	tC2Q	RR	4	R24C39[0][A]	run_cnt_25_s0/Q
1.065	0.004	tNET	RR	1	R24C39[0][A]	n47_s2/I2
1.297	0.232	tINS	RF	1	R24C39[0][A]	n47_s2/F
1.297	0.000	tNET	FF	1	R24C39[0][A]	run_cnt_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
0.675	0.675	tINS	RR	27	IOR27[A]	I_clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C39[0][A]	run_cnt_25_s0/CLK
0.871	0.011	tHld		1	R24C39[0][A]	run_cnt_25_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	0.427
Data Arrival Time	0.951
Data Required Time	0.525
From	testpattern_inst/Color_trig_num_12_s3
To	testpattern_inst/Color_trig_num_12_s3
Launch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R30C29[0][A]	testpattern_inst/Color_trig_num_12_s3/CLK
0.716	0.202	tC2Q	RR	6	R30C29[0][A]	testpattern_inst/Color_trig_num_12_s3/Q
0.719	0.004	tNET	RR	1	R30C29[0][A]	testpattern_inst/n819_s5/I1
0.951	0.232	tINS	RF	1	R30C29[0][A]	testpattern_inst/n819_s5/F
0.951	0.000	tNET	FF	1	R30C29[0][A]	testpattern_inst/Color_trig_num_12_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_clkdiv/CLKOUT.default_gen_clk
0.329	0.329	tCL	RR	258	TOPSIDE[0]	u_clkdiv/CLKOUT
0.514	0.184	tNET	RR	1	R30C29[0][A]	testpattern_inst/Color_trig_num_12_s3/CLK
0.525	0.011	tHld		1	R30C29[0][A]	testpattern_inst/Color_trig_num_12_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	5.654
Actual Width:	6.654
Required Width:	1.000
Type:	Low Pulse Width
Clock:	u_clkdiv/CLKOUT.default_gen_clk
Objects:	vs_r_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.731	0.000			active clock edge time
6.731	0.000			u_clkdiv/CLKOUT.default_gen_clk
7.060	0.329	tCL	FF	u_clkdiv/CLKOUT
7.322	0.261	tNET	FF	vs_r_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.462	0.000			active clock edge time
13.462	0.000			u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	u_clkdiv/CLKOUT
13.975	0.184	tNET	RR	vs_r_s0/CLK

MPW2

MPW Summary:

Slack:	5.654
Actual Width:	6.654
Required Width:	1.000
Type:	Low Pulse Width
Clock:	u_clkdiv/CLKOUT.default_gen_clk
Objects:	cnt_vs_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.731	0.000			active clock edge time
6.731	0.000			u_clkdiv/CLKOUT.default_gen_clk
7.060	0.329	tCL	FF	u_clkdiv/CLKOUT
7.322	0.261	tNET	FF	cnt_vs_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.462	0.000			active clock edge time
13.462	0.000			u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	u_clkdiv/CLKOUT
13.975	0.184	tNET	RR	cnt_vs_9_s0/CLK

MPW3

MPW Summary:

Slack:	5.654
Actual Width:	6.654
Required Width:	1.000
Type:	Low Pulse Width
Clock:	u_clkdiv/CLKOUT.default_gen_clk
Objects:	cnt_vs_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.731	0.000			active clock edge time
6.731	0.000			u_clkdiv/CLKOUT.default_gen_clk
7.060	0.329	tCL	FF	u_clkdiv/CLKOUT
7.322	0.261	tNET	FF	cnt_vs_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.462	0.000			active clock edge time
13.462	0.000			u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	u_clkdiv/CLKOUT
13.975	0.184	tNET	RR	cnt_vs_8_s0/CLK

MPW4

MPW Summary:

Slack:	5.654
Actual Width:	6.654
Required Width:	1.000
Type:	Low Pulse Width
Clock:	u_clkdiv/CLKOUT.default_gen_clk
Objects:	cnt_vs_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.731	0.000			active clock edge time
6.731	0.000			u_clkdiv/CLKOUT.default_gen_clk
7.060	0.329	tCL	FF	u_clkdiv/CLKOUT
7.322	0.261	tNET	FF	cnt_vs_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.462	0.000			active clock edge time
13.462	0.000			u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	u_clkdiv/CLKOUT
13.975	0.184	tNET	RR	cnt_vs_7_s0/CLK

MPW5

MPW Summary:

Slack:	5.654
Actual Width:	6.654
Required Width:	1.000
Type:	Low Pulse Width
Clock:	u_clkdiv/CLKOUT.default_gen_clk
Objects:	cnt_vs_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.731	0.000			active clock edge time
6.731	0.000			u_clkdiv/CLKOUT.default_gen_clk
7.060	0.329	tCL	FF	u_clkdiv/CLKOUT
7.322	0.261	tNET	FF	cnt_vs_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.462	0.000			active clock edge time
13.462	0.000			u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	u_clkdiv/CLKOUT
13.975	0.184	tNET	RR	cnt_vs_6_s0/CLK

MPW6

MPW Summary:

Slack:	5.654
Actual Width:	6.654
Required Width:	1.000
Type:	Low Pulse Width
Clock:	u_clkdiv/CLKOUT.default_gen_clk
Objects:	testpattern_inst/O_vs_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.731	0.000			active clock edge time
6.731	0.000			u_clkdiv/CLKOUT.default_gen_clk
7.060	0.329	tCL	FF	u_clkdiv/CLKOUT
7.322	0.261	tNET	FF	testpattern_inst/O_vs_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.462	0.000			active clock edge time
13.462	0.000			u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	u_clkdiv/CLKOUT
13.975	0.184	tNET	RR	testpattern_inst/O_vs_s0/CLK

MPW7

MPW Summary:

Slack:	5.654
Actual Width:	6.654
Required Width:	1.000
Type:	Low Pulse Width
Clock:	u_clkdiv/CLKOUT.default_gen_clk
Objects:	testpattern_inst/V_cnt_0_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.731	0.000			active clock edge time
6.731	0.000			u_clkdiv/CLKOUT.default_gen_clk
7.060	0.329	tCL	FF	u_clkdiv/CLKOUT
7.322	0.261	tNET	FF	testpattern_inst/V_cnt_0_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.462	0.000			active clock edge time
13.462	0.000			u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	u_clkdiv/CLKOUT
13.975	0.184	tNET	RR	testpattern_inst/V_cnt_0_s1/CLK

MPW8

MPW Summary:

Slack:	5.654
Actual Width:	6.654
Required Width:	1.000
Type:	Low Pulse Width
Clock:	u_clkdiv/CLKOUT.default_gen_clk
Objects:	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.731	0.000			active clock edge time
6.731	0.000			u_clkdiv/CLKOUT.default_gen_clk
7.060	0.329	tCL	FF	u_clkdiv/CLKOUT
7.322	0.261	tNET	FF	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.462	0.000			active clock edge time
13.462	0.000			u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	u_clkdiv/CLKOUT
13.975	0.184	tNET	RR	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0/CLK

MPW9

MPW Summary:

Slack:	5.654
Actual Width:	6.654
Required Width:	1.000
Type:	Low Pulse Width
Clock:	u_clkdiv/CLKOUT.default_gen_clk
Objects:	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.731	0.000			active clock edge time
6.731	0.000			u_clkdiv/CLKOUT.default_gen_clk
7.060	0.329	tCL	FF	u_clkdiv/CLKOUT
7.322	0.261	tNET	FF	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.462	0.000			active clock edge time
13.462	0.000			u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	u_clkdiv/CLKOUT
13.975	0.184	tNET	RR	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0/CLK

MPW10

MPW Summary:

Slack:	5.654
Actual Width:	6.654
Required Width:	1.000
Type:	Low Pulse Width
Clock:	u_clkdiv/CLKOUT.default_gen_clk
Objects:	testpattern_inst/V_cnt_1_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.731	0.000			active clock edge time
6.731	0.000			u_clkdiv/CLKOUT.default_gen_clk
7.060	0.329	tCL	FF	u_clkdiv/CLKOUT
7.322	0.261	tNET	FF	testpattern_inst/V_cnt_1_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.462	0.000			active clock edge time
13.462	0.000			u_clkdiv/CLKOUT.default_gen_clk
13.791	0.329	tCL	RR	u_clkdiv/CLKOUT
13.975	0.184	tNET	RR	testpattern_inst/V_cnt_1_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
258	pix_clk	5.666	0.261
42	de_d	10.648	1.998
32	De_vcnt_15_11	10.714	1.041
32	Pout_de_dn[1]	10.573	1.001
32	V_cnt_14_9	9.418	0.725
27	I_clk_d	15.288	0.261
26	n72_7	15.905	0.703
26	cnt_vs[9]	10.414	1.292
26	cnt_vs[8]	10.210	1.223
24	De_hcnt_15_16	11.110	1.219

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R29C35	87.50%
R25C37	81.94%
R26C29	80.56%
R29C29	80.56%
R27C39	75.00%
R31C32	75.00%
R30C34	73.61%
R22C39	69.44%
R26C33	69.44%
R26C34	69.44%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add