Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\DVI_RX\data\dvi_rx_top.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\DVI_RX\data\dvi2rgb.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW2A-LV18PG484C8/I7 |
| Device | GW2A-18 |
| Device Version | C |
| Created Time | Fri Dec 26 16:24:02 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DVI_RX_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.142s, Peak memory usage = 176.062MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 176.062MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 176.062MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 176.062MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 176.062MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 176.062MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 176.062MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 176.062MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 176.062MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 176.062MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 176.062MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 176.062MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 176.062MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.169s, Peak memory usage = 176.062MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 176.062MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 176.062MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 43 |
| I/O Buf | 39 |
| IBUF | 1 |
| OBUF | 34 |
| TLVDS_IBUF | 4 |
| Register | 394 |
| DFFC | 278 |
| DFFCE | 116 |
| LUT | 859 |
| LUT2 | 125 |
| LUT3 | 302 |
| LUT4 | 432 |
| ALU | 14 |
| ALU | 14 |
| INV | 3 |
| INV | 3 |
| IOLOGIC | 3 |
| IDES10 | 3 |
| CLOCK | 2 |
| CLKDIV | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 876(862 LUT, 14 ALU) / 20736 | 5% |
| Register | 394 / 16512 | 3% |
| --Register as Latch | 0 / 16512 | 0% |
| --Register as FF | 394 / 16512 | 3% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | I_tmds_clk_p | Base | 13.468 | 74.250 | 0.000 | 6.734 | dvi2rgb_inst/u_HDMI_CK/I | ||
| 2 | dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk | Generated | 2.694 | 371.250 | 0.000 | 1.347 | dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | dvi2rgb_inst/rPLL_inst/CLKOUT |
| 3 | dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk | Generated | 2.694 | 371.250 | 0.000 | 1.347 | dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | dvi2rgb_inst/rPLL_inst/CLKOUTP |
| 4 | dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk | Generated | 13.468 | 74.250 | 0.000 | 6.734 | dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | dvi2rgb_inst/rPLL_inst/CLKOUTD |
| 5 | dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk | Generated | 8.081 | 123.750 | 0.000 | 4.040 | dvi2rgb_inst/u_HDMI_CK/I | I_tmds_clk_p | dvi2rgb_inst/rPLL_inst/CLKOUTD3 |
| 6 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | Generated | 13.468 | 74.250 | 0.000 | 6.734 | dvi2rgb_inst/rPLL_inst/CLKOUTP | dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk | dvi2rgb_inst/u_clkdiv5/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_tmds_clk_p | 74.250(MHz) | 263.852(MHz) | 4 | TOP |
| 2 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | 74.250(MHz) | 101.665(MHz) | 11 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.632 |
| Data Arrival Time | 10.502 |
| Data Required Time | 14.134 |
| From | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0 |
| To | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1 |
| Launch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
| Latch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 385 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 5 | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/F |
| 2.436 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/I1 |
| 2.991 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/F |
| 3.465 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/I0 |
| 3.982 | 0.517 | tINS | FF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/F |
| 4.456 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/I1 |
| 5.011 | 0.555 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/F |
| 5.485 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I0 |
| 6.002 | 0.517 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F |
| 6.476 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/I1 |
| 7.031 | 0.555 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/F |
| 7.505 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/I0 |
| 8.022 | 0.517 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/F |
| 8.496 | 0.474 | tNET | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/I1 |
| 9.066 | 0.570 | tINS | FR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT |
| 9.066 | 0.000 | tNET | RR | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN |
| 9.101 | 0.035 | tINS | RF | 4 | dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT |
| 9.575 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n15_s0/I2 |
| 10.028 | 0.453 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n15_s0/F |
| 10.502 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.468 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
| 13.809 | 0.341 | tCL | RR | 385 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
| 14.169 | 0.360 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/CLK |
| 14.134 | -0.035 | tSu | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.468 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 4.829, 49.272%; route: 4.740, 48.361%; tC2Q: 0.232, 2.367% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | 3.714 |
| Data Arrival Time | 10.420 |
| Data Required Time | 14.134 |
| From | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0 |
| To | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1 |
| Launch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
| Latch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 385 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 5 | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/F |
| 2.436 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/I1 |
| 2.991 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/F |
| 3.465 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/I0 |
| 3.982 | 0.517 | tINS | FF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/F |
| 4.456 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/I1 |
| 5.011 | 0.555 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/F |
| 5.485 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I0 |
| 6.002 | 0.517 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F |
| 6.476 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/I1 |
| 7.031 | 0.555 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/F |
| 7.505 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/I0 |
| 8.022 | 0.517 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/F |
| 8.496 | 0.474 | tNET | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/I1 |
| 9.066 | 0.570 | tINS | FR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT |
| 9.066 | 0.000 | tNET | RR | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN |
| 9.101 | 0.035 | tINS | RF | 4 | dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT |
| 9.575 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n12_s0/I3 |
| 9.946 | 0.371 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n12_s0/F |
| 10.420 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.468 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
| 13.809 | 0.341 | tCL | RR | 385 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
| 14.169 | 0.360 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1/CLK |
| 14.134 | -0.035 | tSu | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.468 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 4.747, 48.844%; route: 4.740, 48.769%; tC2Q: 0.232, 2.387% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | 3.714 |
| Data Arrival Time | 10.420 |
| Data Required Time | 14.134 |
| From | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0 |
| To | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1 |
| Launch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
| Latch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 385 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 5 | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/F |
| 2.436 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/I1 |
| 2.991 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/F |
| 3.465 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/I0 |
| 3.982 | 0.517 | tINS | FF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/F |
| 4.456 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/I1 |
| 5.011 | 0.555 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/F |
| 5.485 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I0 |
| 6.002 | 0.517 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F |
| 6.476 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/I1 |
| 7.031 | 0.555 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/F |
| 7.505 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/I0 |
| 8.022 | 0.517 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/F |
| 8.496 | 0.474 | tNET | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/I1 |
| 9.066 | 0.570 | tINS | FR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT |
| 9.066 | 0.000 | tNET | RR | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN |
| 9.101 | 0.035 | tINS | RF | 4 | dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT |
| 9.575 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s0/I3 |
| 9.946 | 0.371 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s0/F |
| 10.420 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.468 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
| 13.809 | 0.341 | tCL | RR | 385 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
| 14.169 | 0.360 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/CLK |
| 14.134 | -0.035 | tSu | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.468 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 4.747, 48.844%; route: 4.740, 48.769%; tC2Q: 0.232, 2.387% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | 3.714 |
| Data Arrival Time | 10.420 |
| Data Required Time | 14.134 |
| From | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0 |
| To | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1 |
| Launch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
| Latch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 385 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 5 | dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/F |
| 2.436 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/I1 |
| 2.991 | 0.555 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/F |
| 3.465 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/I0 |
| 3.982 | 0.517 | tINS | FF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/F |
| 4.456 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/I1 |
| 5.011 | 0.555 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/F |
| 5.485 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I0 |
| 6.002 | 0.517 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F |
| 6.476 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/I1 |
| 7.031 | 0.555 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/F |
| 7.505 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/I0 |
| 8.022 | 0.517 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/F |
| 8.496 | 0.474 | tNET | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/I1 |
| 9.066 | 0.570 | tINS | FR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT |
| 9.066 | 0.000 | tNET | RR | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN |
| 9.101 | 0.035 | tINS | RF | 4 | dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT |
| 9.575 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s0/I3 |
| 9.946 | 0.371 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n13_s0/F |
| 10.420 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.468 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
| 13.809 | 0.341 | tCL | RR | 385 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
| 14.169 | 0.360 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1/CLK |
| 14.134 | -0.035 | tSu | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.468 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 4.747, 48.844%; route: 4.740, 48.769%; tC2Q: 0.232, 2.387% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | 5.676 |
| Data Arrival Time | 8.458 |
| Data Required Time | 14.134 |
| From | dvi2rgb_inst/u_Data_Aligning_Auto/Rali_4_s0 |
| To | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s1 |
| Launch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
| Latch Clk | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 385 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/Rali_4_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 6 | dvi2rgb_inst/u_Data_Aligning_Auto/Rali_4_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s56/I1 |
| 1.962 | 0.555 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s56/F |
| 2.436 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s134/I1 |
| 2.991 | 0.555 | tINS | FF | 2 | dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s134/F |
| 3.465 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1938_s11/I0 |
| 3.982 | 0.517 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1938_s11/F |
| 4.456 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1938_s8/I0 |
| 4.973 | 0.517 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1938_s8/F |
| 5.447 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1938_s4/I1 |
| 6.002 | 0.555 | tINS | FF | 3 | dvi2rgb_inst/u_Data_Aligning_Auto/n1938_s4/F |
| 6.476 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s3/I0 |
| 6.993 | 0.517 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s3/F |
| 7.467 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s2/I0 |
| 7.984 | 0.517 | tINS | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s2/F |
| 8.458 | 0.474 | tNET | FF | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.468 | 0.000 | dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk | |||
| 13.809 | 0.341 | tCL | RR | 385 | dvi2rgb_inst/u_clkdiv5/CLKOUT |
| 14.169 | 0.360 | tNET | RR | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s1/CLK |
| 14.134 | -0.035 | tSu | 1 | dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.468 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 3.733, 48.124%; route: 3.792, 48.885%; tC2Q: 0.232, 2.991% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |