Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\impl\gwsynthesis\csc_ref_design.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\csc_ref_design.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\csc_ref_design.sdc
Version	V1.9.9 Beta-6
Part Number	GW2A-LV18PG484C8/I7
Device	GW2A-18
Device Version	C
Created Time	Tue Oct 31 11:27:54 2023
Legal Announcement	Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	3977
Numbers of Endpoints Analyzed	2299
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
I_clk	Base	20.000	50.000	0.000	10.000			I_clk
Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	Generated	13.333	75.000	0.000	6.667	I_clk_ibuf/I	I_clk	Gowin_rPLL_inst/rpll_inst/CLKOUT
Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk	Generated	20.000	50.000	0.000	10.000	I_clk_ibuf/I	I_clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP
Gowin_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk	Generated	26.667	37.500	0.000	13.333	I_clk_ibuf/I	I_clk	Gowin_rPLL_inst/rpll_inst/CLKOUTD
Gowin_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk	Generated	40.000	25.000	0.000	20.000	I_clk_ibuf/I	I_clk	Gowin_rPLL_inst/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	75.000(MHz)	189.074(MHz)	7	TOP
2	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk	50.000(MHz)	197.871(MHz)	5	TOP

No timing paths to get frequency of I_clk!

No timing paths to get frequency of Gowin_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of Gowin_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
I_clk	Setup	0.000	0
I_clk	Hold	0.000	0
Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
Gowin_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
Gowin_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
Gowin_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
Gowin_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.150	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.234
2	2.150	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.234
3	2.150	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.234
4	2.150	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.234
5	2.150	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.234
6	2.150	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.234
7	2.150	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.234
8	2.150	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.234
9	2.150	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.234
10	2.163	key_debounceN_inst0/key_n_out1_s1/Q	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.221
11	2.163	key_debounceN_inst0/key_n_out1_s1/Q	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.221
12	2.163	key_debounceN_inst0/key_n_out1_s1/Q	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.221
13	2.163	key_debounceN_inst0/key_n_out1_s1/Q	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.221
14	2.163	key_debounceN_inst0/key_n_out1_s1/Q	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.221
15	2.163	key_debounceN_inst0/key_n_out1_s1/Q	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.221
16	2.163	key_debounceN_inst0/key_n_out1_s1/Q	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.221
17	2.163	key_debounceN_inst0/key_n_out1_s1/Q	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.221
18	2.163	key_debounceN_inst0/key_n_out1_s1/Q	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst/RESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.221
19	4.780	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0/CE	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	1.819
20	4.780	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0/CE	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	1.819
21	4.780	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0/CE	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	1.819
22	4.780	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0/CE	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	1.819
23	4.780	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0/CE	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	1.819
24	4.780	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_17_s0/CE	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	1.819
25	4.780	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_18_s0/CE	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	1.819

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.424	cnt_vs_3_s0/Q	cnt_vs_3_s0/D	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.435
2	0.425	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
3	0.425	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_10_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_10_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
4	0.425	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_12_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_12_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
5	0.425	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
6	0.425	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_1_s3/Q	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_1_s3/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
7	0.425	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_2_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
8	0.425	adv7513_iic_init_inst0/O_RADDR_2_s2/Q	adv7513_iic_init_inst0/O_RADDR_2_s2/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
9	0.425	adv7513_iic_init_inst0/O_WDATA_5_s1/Q	adv7513_iic_init_inst0/O_WDATA_5_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
10	0.425	adv7513_iic_init_inst0/O_WADDR_2_s1/Q	adv7513_iic_init_inst0/O_WADDR_2_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
11	0.425	adv7513_iic_init_inst0/mem_cnt_7_s1/Q	adv7513_iic_init_inst0/mem_cnt_7_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
12	0.425	adv7513_iic_init_inst0/mem_cnt_4_s1/Q	adv7513_iic_init_inst0/mem_cnt_4_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
13	0.425	testpattern_inst/Sqr_h_trig_s2/Q	testpattern_inst/Sqr_h_trig_s2/D	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.436
14	0.425	testpattern_inst/Color_trig_num_8_s1/Q	testpattern_inst/Color_trig_num_8_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.436
15	0.425	testpattern_inst/De_cyc_vcnt_5_s1/Q	testpattern_inst/De_cyc_vcnt_5_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.436
16	0.425	testpattern_inst/De_vcnt_14_s1/Q	testpattern_inst/De_vcnt_14_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.436
17	0.425	key_debounceN_inst0/cnt_3_s0/Q	key_debounceN_inst0/cnt_3_s0/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
18	0.425	run_cnt_2_s0/Q	run_cnt_2_s0/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
19	0.425	run_cnt_3_s0/Q	run_cnt_3_s0/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.436
20	0.427	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.438
21	0.427	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_13_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_13_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.438
22	0.427	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/Q	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.438
23	0.427	adv7513_iic_init_inst0/O_WDATA_2_s1/Q	adv7513_iic_init_inst0/O_WDATA_2_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.438
24	0.427	adv7513_iic_init_inst0/mem_cnt_6_s1/Q	adv7513_iic_init_inst0/mem_cnt_6_s1/D	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	0.438
25	0.427	testpattern_inst/Color_cnt_0_s3/Q	testpattern_inst/Color_cnt_0_s3/D	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.438

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_0_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
2	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_1_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
3	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_2_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
4	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_3_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
5	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_4_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
6	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_5_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
7	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_0_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
8	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_1_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
9	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_2_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
10	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_3_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
11	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_4_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
12	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_5_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
13	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_6_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
14	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_7_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
15	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_0_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
16	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_1_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
17	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_2_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
18	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_3_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
19	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_4_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
20	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_5_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
21	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_6_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
22	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_7_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
23	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_0_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
24	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_1_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406
25	2.194	key_debounceN_inst0/key_n_out1_s1/Q	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_2_s0/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]	6.667	-0.002	4.406

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
2	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/SDA_OEN_s1/PRESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
3	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/SCL_OEN_s1/PRESET	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
4	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_0_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
5	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_1_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
6	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_2_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
7	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
8	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_4_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
9	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_5_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
10	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_6_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
11	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_7_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
12	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_8_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
13	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_9_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
14	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_10_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
15	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_11_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
16	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_12_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
17	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_13_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
18	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_14_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
19	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_15_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
20	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_16_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
21	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
22	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_1_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
23	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
24	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_3_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234
25	1.223	key_debounceN_inst0/key_n_out2_s1/Q	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_4_s1/CLEAR	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]	0.000	0.000	1.234

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	5.590	6.590	1.000	Low Pulse Width	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	vs_r_s0
2	5.590	6.590	1.000	Low Pulse Width	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	cnt_vs_7_s0
3	5.590	6.590	1.000	Low Pulse Width	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	cnt_vs_3_s0
4	5.590	6.590	1.000	Low Pulse Width	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	vs_dn_6_s0
5	5.590	6.590	1.000	Low Pulse Width	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	hs_dn_2_s0
6	5.590	6.590	1.000	Low Pulse Width	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	testpattern_inst/Color_bar_15_s0
7	5.590	6.590	1.000	Low Pulse Width	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	testpattern_inst/De_hcnt_9_s1
8	5.590	6.590	1.000	Low Pulse Width	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/Dout1_sum_12_s0
9	5.590	6.590	1.000	Low Pulse Width	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/Dout1_sum_13_s0
10	5.590	6.590	1.000	Low Pulse Width	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk	testpattern_inst/De_hcnt_11_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.150
Data Arrival Time	25.464
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.464	1.413	tNET	RR	1	DSP_R37[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.463%; route: 3.432, 81.058%; tC2Q: 0.232, 5.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack	2.150
Data Arrival Time	25.464
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.464	1.413	tNET	RR	1	DSP_R37[3][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[3][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[3][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.463%; route: 3.432, 81.058%; tC2Q: 0.232, 5.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack	2.150
Data Arrival Time	25.464
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.464	1.413	tNET	RR	1	DSP_R37[4][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[4][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[4][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.463%; route: 3.432, 81.058%; tC2Q: 0.232, 5.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack	2.150
Data Arrival Time	25.464
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.464	1.413	tNET	RR	1	DSP_R37[4][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[4][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[4][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.463%; route: 3.432, 81.058%; tC2Q: 0.232, 5.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack	2.150
Data Arrival Time	25.464
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.464	1.413	tNET	RR	1	DSP_R37[3][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[3][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[3][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.463%; route: 3.432, 81.058%; tC2Q: 0.232, 5.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack	2.150
Data Arrival Time	25.464
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.464	1.413	tNET	RR	1	DSP_R37[4][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[4][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[4][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.463%; route: 3.432, 81.058%; tC2Q: 0.232, 5.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack	2.150
Data Arrival Time	25.464
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.464	1.413	tNET	RR	1	DSP_R37[4][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[4][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[4][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.463%; route: 3.432, 81.058%; tC2Q: 0.232, 5.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack	2.150
Data Arrival Time	25.464
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.464	1.413	tNET	RR	1	DSP_R37[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.463%; route: 3.432, 81.058%; tC2Q: 0.232, 5.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack	2.150
Data Arrival Time	25.464
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.464	1.413	tNET	RR	1	DSP_R37[5][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[5][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[5][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.463%; route: 3.432, 81.058%; tC2Q: 0.232, 5.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack	2.163
Data Arrival Time	25.451
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	352	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.451	1.400	tNET	RR	1	DSP_R37[5][B]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[5][B]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst/CLK
27.864	-0.035	tUnc				rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[5][B]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.502%; route: 3.419, 81.002%; tC2Q: 0.232, 5.496%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack	2.163
Data Arrival Time	25.451
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	352	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.451	1.400	tNET	RR	1	DSP_R19[4][B]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R19[4][B]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst/CLK
27.864	-0.035	tUnc				rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R19[4][B]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.502%; route: 3.419, 81.002%; tC2Q: 0.232, 5.496%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack	2.163
Data Arrival Time	25.451
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	352	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.451	1.400	tNET	RR	1	DSP_R19[5][B]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R19[5][B]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst/CLK
27.864	-0.035	tUnc				rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R19[5][B]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.502%; route: 3.419, 81.002%; tC2Q: 0.232, 5.496%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack	2.163
Data Arrival Time	25.451
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	352	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.451	1.400	tNET	RR	1	DSP_R37[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst/CLK
27.864	-0.035	tUnc				rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.502%; route: 3.419, 81.002%; tC2Q: 0.232, 5.496%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack	2.163
Data Arrival Time	25.451
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	352	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.451	1.400	tNET	RR	1	DSP_R19[4][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R19[4][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst/CLK
27.864	-0.035	tUnc				rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R19[4][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.502%; route: 3.419, 81.002%; tC2Q: 0.232, 5.496%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack	2.163
Data Arrival Time	25.451
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	352	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.451	1.400	tNET	RR	1	DSP_R19[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R19[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst/CLK
27.864	-0.035	tUnc				rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R19[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.502%; route: 3.419, 81.002%; tC2Q: 0.232, 5.496%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack	2.163
Data Arrival Time	25.451
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	352	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.451	1.400	tNET	RR	1	DSP_R37[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R37[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst/CLK
27.864	-0.035	tUnc				rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R37[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.502%; route: 3.419, 81.002%; tC2Q: 0.232, 5.496%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack	2.163
Data Arrival Time	25.451
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	352	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.451	1.400	tNET	RR	1	DSP_R19[4][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R19[4][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst/CLK
27.864	-0.035	tUnc				rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R19[4][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.502%; route: 3.419, 81.002%; tC2Q: 0.232, 5.496%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack	2.163
Data Arrival Time	25.451
Data Required Time	27.614
From	key_debounceN_inst0/key_n_out1_s1
To	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.051	0.570	tINS	FR	352	R32C45[2][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.451	1.400	tNET	RR	1	DSP_R19[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	DSP_R19[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst/CLK
27.864	-0.035	tUnc				rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst
27.614	-0.250	tSu		1	DSP_R19[5][A]	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/mult18x18_inst

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.570, 13.502%; route: 3.419, 81.002%; tC2Q: 0.232, 5.496%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack	4.780
Data Arrival Time	23.049
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.461	0.231	tC2Q	RR	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.049	1.588	tNET	RR	1	R44C50[0][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R44C50[0][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0
27.829	-0.035	tSu		1	R44C50[0][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 87.299%; tC2Q: 0.231, 12.701%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack	4.780
Data Arrival Time	23.049
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.461	0.231	tC2Q	RR	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.049	1.588	tNET	RR	1	R44C50[1][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R44C50[1][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0
27.829	-0.035	tSu		1	R44C50[1][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 87.299%; tC2Q: 0.231, 12.701%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack	4.780
Data Arrival Time	23.049
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.461	0.231	tC2Q	RR	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.049	1.588	tNET	RR	1	R44C50[1][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R44C50[1][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0
27.829	-0.035	tSu		1	R44C50[1][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 87.299%; tC2Q: 0.231, 12.701%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack	4.780
Data Arrival Time	23.049
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.461	0.231	tC2Q	RR	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.049	1.588	tNET	RR	1	R44C50[2][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R44C50[2][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0
27.829	-0.035	tSu		1	R44C50[2][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 87.299%; tC2Q: 0.231, 12.701%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack	4.780
Data Arrival Time	23.049
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.461	0.231	tC2Q	RR	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.049	1.588	tNET	RR	1	R44C50[2][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R44C50[2][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0
27.829	-0.035	tSu		1	R44C50[2][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 87.299%; tC2Q: 0.231, 12.701%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack	4.780
Data Arrival Time	23.049
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_17_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.461	0.231	tC2Q	RR	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.049	1.588	tNET	RR	1	R44C51[0][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_17_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R44C51[0][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_17_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_17_s0
27.829	-0.035	tSu		1	R44C51[0][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_17_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 87.299%; tC2Q: 0.231, 12.701%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack	4.780
Data Arrival Time	23.049
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_18_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.461	0.231	tC2Q	RR	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.049	1.588	tNET	RR	1	R44C51[0][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_18_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R44C51[0][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_18_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_18_s0
27.829	-0.035	tSu		1	R44C51[0][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_18_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 87.299%; tC2Q: 0.231, 12.701%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.424
Data Arrival Time	1.609
Data Required Time	1.184
From	cnt_vs_3_s0
To	cnt_vs_3_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R25C53[1][A]	cnt_vs_3_s0/CLK
1.375	0.202	tC2Q	RR	1	R25C53[1][A]	cnt_vs_3_s0/Q
1.377	0.001	tNET	RR	2	R25C53[1][A]	n156_s/I1
1.609	0.232	tINS	RF	1	R25C53[1][A]	n156_s/SUM
1.609	0.000	tNET	FF	1	R25C53[1][A]	cnt_vs_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R25C53[1][A]	cnt_vs_3_s0/CLK
1.184	0.011	tHld		1	R25C53[1][A]	cnt_vs_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R8C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/CLK
1.373	0.202	tC2Q	RR	2	R8C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/Q
1.375	0.002	tNET	RR	1	R8C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n231_s5/I1
1.607	0.232	tINS	RF	1	R8C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n231_s5/F
1.607	0.000	tNET	FF	1	R8C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R8C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/CLK
1.182	0.011	tHld		1	R8C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_10_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_10_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R12C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_10_s1/CLK
1.373	0.202	tC2Q	RR	4	R12C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_10_s1/Q
1.375	0.002	tNET	RR	1	R12C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n36_s0/I2
1.607	0.232	tINS	RF	1	R12C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n36_s0/F
1.607	0.000	tNET	FF	1	R12C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R12C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_10_s1/CLK
1.182	0.011	tHld		1	R12C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path4

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_12_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_12_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R12C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_12_s1/CLK
1.373	0.202	tC2Q	RR	2	R12C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_12_s1/Q
1.375	0.002	tNET	RR	1	R12C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n34_s0/I2
1.607	0.232	tINS	RF	1	R12C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n34_s0/F
1.607	0.000	tNET	FF	1	R12C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R12C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_12_s1/CLK
1.182	0.011	tHld		1	R12C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_12_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path5

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/CLK
1.373	0.202	tC2Q	RR	2	R13C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/Q
1.375	0.002	tNET	RR	1	R13C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n31_s0/I3
1.607	0.232	tINS	RF	1	R13C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n31_s0/F
1.607	0.000	tNET	FF	1	R13C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/CLK
1.182	0.011	tHld		1	R13C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path6

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_1_s3
To	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_1_s3
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R22C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_1_s3/CLK
1.373	0.202	tC2Q	RR	3	R22C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_1_s3/Q
1.375	0.002	tNET	RR	1	R22C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/n51_s3/I0
1.607	0.232	tINS	RF	1	R22C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/n51_s3/F
1.607	0.000	tNET	FF	1	R22C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R22C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_1_s3/CLK
1.182	0.011	tHld		1	R22C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path7

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_2_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R22C45[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_2_s1/CLK
1.373	0.202	tC2Q	RR	2	R22C45[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_2_s1/Q
1.375	0.002	tNET	RR	1	R22C45[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/n50_s1/I3
1.607	0.232	tINS	RF	1	R22C45[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/n50_s1/F
1.607	0.000	tNET	FF	1	R22C45[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R22C45[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_2_s1/CLK
1.182	0.011	tHld		1	R22C45[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/dcnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	adv7513_iic_init_inst0/O_RADDR_2_s2
To	adv7513_iic_init_inst0/O_RADDR_2_s2
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R16C49[0][A]	adv7513_iic_init_inst0/O_RADDR_2_s2/CLK
1.373	0.202	tC2Q	RR	3	R16C49[0][A]	adv7513_iic_init_inst0/O_RADDR_2_s2/Q
1.375	0.002	tNET	RR	1	R16C49[0][A]	adv7513_iic_init_inst0/n1051_s10/I2
1.607	0.232	tINS	RF	1	R16C49[0][A]	adv7513_iic_init_inst0/n1051_s10/F
1.607	0.000	tNET	FF	1	R16C49[0][A]	adv7513_iic_init_inst0/O_RADDR_2_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R16C49[0][A]	adv7513_iic_init_inst0/O_RADDR_2_s2/CLK
1.182	0.011	tHld		1	R16C49[0][A]	adv7513_iic_init_inst0/O_RADDR_2_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	adv7513_iic_init_inst0/O_WDATA_5_s1
To	adv7513_iic_init_inst0/O_WDATA_5_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R7C48[0][A]	adv7513_iic_init_inst0/O_WDATA_5_s1/CLK
1.373	0.202	tC2Q	RR	5	R7C48[0][A]	adv7513_iic_init_inst0/O_WDATA_5_s1/Q
1.375	0.002	tNET	RR	1	R7C48[0][A]	adv7513_iic_init_inst0/n1020_s14/I2
1.607	0.232	tINS	RF	1	R7C48[0][A]	adv7513_iic_init_inst0/n1020_s14/F
1.607	0.000	tNET	FF	1	R7C48[0][A]	adv7513_iic_init_inst0/O_WDATA_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R7C48[0][A]	adv7513_iic_init_inst0/O_WDATA_5_s1/CLK
1.182	0.011	tHld		1	R7C48[0][A]	adv7513_iic_init_inst0/O_WDATA_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	adv7513_iic_init_inst0/O_WADDR_2_s1
To	adv7513_iic_init_inst0/O_WADDR_2_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R7C49[0][A]	adv7513_iic_init_inst0/O_WADDR_2_s1/CLK
1.373	0.202	tC2Q	RR	6	R7C49[0][A]	adv7513_iic_init_inst0/O_WADDR_2_s1/Q
1.375	0.002	tNET	RR	1	R7C49[0][A]	adv7513_iic_init_inst0/n995_s8/I1
1.607	0.232	tINS	RF	1	R7C49[0][A]	adv7513_iic_init_inst0/n995_s8/F
1.607	0.000	tNET	FF	1	R7C49[0][A]	adv7513_iic_init_inst0/O_WADDR_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R7C49[0][A]	adv7513_iic_init_inst0/O_WADDR_2_s1/CLK
1.182	0.011	tHld		1	R7C49[0][A]	adv7513_iic_init_inst0/O_WADDR_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path11

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	adv7513_iic_init_inst0/mem_cnt_7_s1
To	adv7513_iic_init_inst0/mem_cnt_7_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R20C49[1][A]	adv7513_iic_init_inst0/mem_cnt_7_s1/CLK
1.373	0.202	tC2Q	RR	2	R20C49[1][A]	adv7513_iic_init_inst0/mem_cnt_7_s1/Q
1.375	0.002	tNET	RR	1	R20C49[1][A]	adv7513_iic_init_inst0/n265_s2/I2
1.607	0.232	tINS	RF	1	R20C49[1][A]	adv7513_iic_init_inst0/n265_s2/F
1.607	0.000	tNET	FF	1	R20C49[1][A]	adv7513_iic_init_inst0/mem_cnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R20C49[1][A]	adv7513_iic_init_inst0/mem_cnt_7_s1/CLK
1.182	0.011	tHld		1	R20C49[1][A]	adv7513_iic_init_inst0/mem_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path12

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	adv7513_iic_init_inst0/mem_cnt_4_s1
To	adv7513_iic_init_inst0/mem_cnt_4_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R20C48[0][A]	adv7513_iic_init_inst0/mem_cnt_4_s1/CLK
1.373	0.202	tC2Q	RR	3	R20C48[0][A]	adv7513_iic_init_inst0/mem_cnt_4_s1/Q
1.375	0.002	tNET	RR	1	R20C48[0][A]	adv7513_iic_init_inst0/n268_s2/I3
1.607	0.232	tINS	RF	1	R20C48[0][A]	adv7513_iic_init_inst0/n268_s2/F
1.607	0.000	tNET	FF	1	R20C48[0][A]	adv7513_iic_init_inst0/mem_cnt_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R20C48[0][A]	adv7513_iic_init_inst0/mem_cnt_4_s1/CLK
1.182	0.011	tHld		1	R20C48[0][A]	adv7513_iic_init_inst0/mem_cnt_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path13

Path Summary:

Slack	0.425
Data Arrival Time	1.610
Data Required Time	1.184
From	testpattern_inst/Sqr_h_trig_s2
To	testpattern_inst/Sqr_h_trig_s2
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R14C52[0][A]	testpattern_inst/Sqr_h_trig_s2/CLK
1.375	0.202	tC2Q	RR	2	R14C52[0][A]	testpattern_inst/Sqr_h_trig_s2/Q
1.378	0.002	tNET	RR	1	R14C52[0][A]	testpattern_inst/n1276_s14/I2
1.610	0.232	tINS	RF	1	R14C52[0][A]	testpattern_inst/n1276_s14/F
1.610	0.000	tNET	FF	1	R14C52[0][A]	testpattern_inst/Sqr_h_trig_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R14C52[0][A]	testpattern_inst/Sqr_h_trig_s2/CLK
1.184	0.011	tHld		1	R14C52[0][A]	testpattern_inst/Sqr_h_trig_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path14

Path Summary:

Slack	0.425
Data Arrival Time	1.610
Data Required Time	1.184
From	testpattern_inst/Color_trig_num_8_s1
To	testpattern_inst/Color_trig_num_8_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R15C51[1][A]	testpattern_inst/Color_trig_num_8_s1/CLK
1.375	0.202	tC2Q	RR	4	R15C51[1][A]	testpattern_inst/Color_trig_num_8_s1/Q
1.378	0.002	tNET	RR	1	R15C51[1][A]	testpattern_inst/n823_s1/I1
1.610	0.232	tINS	RF	1	R15C51[1][A]	testpattern_inst/n823_s1/F
1.610	0.000	tNET	FF	1	R15C51[1][A]	testpattern_inst/Color_trig_num_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R15C51[1][A]	testpattern_inst/Color_trig_num_8_s1/CLK
1.184	0.011	tHld		1	R15C51[1][A]	testpattern_inst/Color_trig_num_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path15

Path Summary:

Slack	0.425
Data Arrival Time	1.610
Data Required Time	1.184
From	testpattern_inst/De_cyc_vcnt_5_s1
To	testpattern_inst/De_cyc_vcnt_5_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R9C52[1][A]	testpattern_inst/De_cyc_vcnt_5_s1/CLK
1.375	0.202	tC2Q	RR	6	R9C52[1][A]	testpattern_inst/De_cyc_vcnt_5_s1/Q
1.378	0.002	tNET	RR	1	R9C52[1][A]	testpattern_inst/n754_s2/I0
1.610	0.232	tINS	RF	1	R9C52[1][A]	testpattern_inst/n754_s2/F
1.610	0.000	tNET	FF	1	R9C52[1][A]	testpattern_inst/De_cyc_vcnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R9C52[1][A]	testpattern_inst/De_cyc_vcnt_5_s1/CLK
1.184	0.011	tHld		1	R9C52[1][A]	testpattern_inst/De_cyc_vcnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path16

Path Summary:

Slack	0.425
Data Arrival Time	1.610
Data Required Time	1.184
From	testpattern_inst/De_vcnt_14_s1
To	testpattern_inst/De_vcnt_14_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R13C52[1][A]	testpattern_inst/De_vcnt_14_s1/CLK
1.375	0.202	tC2Q	RR	3	R13C52[1][A]	testpattern_inst/De_vcnt_14_s1/Q
1.378	0.002	tNET	RR	1	R13C52[1][A]	testpattern_inst/n505_s5/I2
1.610	0.232	tINS	RF	1	R13C52[1][A]	testpattern_inst/n505_s5/F
1.610	0.000	tNET	FF	1	R13C52[1][A]	testpattern_inst/De_vcnt_14_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R13C52[1][A]	testpattern_inst/De_vcnt_14_s1/CLK
1.184	0.011	tHld		1	R13C52[1][A]	testpattern_inst/De_vcnt_14_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	key_debounceN_inst0/cnt_3_s0
To	key_debounceN_inst0/cnt_3_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R44C46[1][A]	key_debounceN_inst0/cnt_3_s0/CLK
1.373	0.202	tC2Q	RR	3	R44C46[1][A]	key_debounceN_inst0/cnt_3_s0/Q
1.375	0.002	tNET	RR	1	R44C46[1][A]	key_debounceN_inst0/n110_s1/I1
1.607	0.232	tINS	RF	1	R44C46[1][A]	key_debounceN_inst0/n110_s1/F
1.607	0.000	tNET	FF	1	R44C46[1][A]	key_debounceN_inst0/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R44C46[1][A]	key_debounceN_inst0/cnt_3_s0/CLK
1.182	0.011	tHld		1	R44C46[1][A]	key_debounceN_inst0/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	run_cnt_2_s0
To	run_cnt_2_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R31C52[0][A]	run_cnt_2_s0/CLK
1.373	0.202	tC2Q	RR	3	R31C52[0][A]	run_cnt_2_s0/Q
1.375	0.002	tNET	RR	1	R31C52[0][A]	n74_s2/I2
1.607	0.232	tINS	RF	1	R31C52[0][A]	n74_s2/F
1.607	0.000	tNET	FF	1	R31C52[0][A]	run_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R31C52[0][A]	run_cnt_2_s0/CLK
1.182	0.011	tHld		1	R31C52[0][A]	run_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack	0.425
Data Arrival Time	1.607
Data Required Time	1.182
From	run_cnt_3_s0
To	run_cnt_3_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R34C52[0][A]	run_cnt_3_s0/CLK
1.373	0.202	tC2Q	RR	2	R34C52[0][A]	run_cnt_3_s0/Q
1.375	0.002	tNET	RR	1	R34C52[0][A]	n73_s2/I1
1.607	0.232	tINS	RF	1	R34C52[0][A]	n73_s2/F
1.607	0.000	tNET	FF	1	R34C52[0][A]	run_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R34C52[0][A]	run_cnt_3_s0/CLK
1.182	0.011	tHld		1	R34C52[0][A]	run_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path20

Path Summary:

Slack	0.427
Data Arrival Time	1.608
Data Required Time	1.182
From	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1/CLK
1.373	0.202	tC2Q	RR	5	R13C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1/Q
1.376	0.004	tNET	RR	1	R13C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n46_s0/I1
1.608	0.232	tINS	RF	1	R13C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n46_s0/F
1.608	0.000	tNET	FF	1	R13C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1/CLK
1.182	0.011	tHld		1	R13C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path21

Path Summary:

Slack	0.427
Data Arrival Time	1.608
Data Required Time	1.182
From	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_13_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_13_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_13_s1/CLK
1.373	0.202	tC2Q	RR	4	R13C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_13_s1/Q
1.376	0.004	tNET	RR	1	R13C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n33_s0/I1
1.608	0.232	tINS	RF	1	R13C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n33_s0/F
1.608	0.000	tNET	FF	1	R13C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_13_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_13_s1/CLK
1.182	0.011	tHld		1	R13C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_13_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path22

Path Summary:

Slack	0.427
Data Arrival Time	1.608
Data Required Time	1.182
From	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0
To	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R14C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/CLK
1.373	0.202	tC2Q	RR	5	R14C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/Q
1.376	0.004	tNET	RR	1	R14C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/n199_s2/I0
1.608	0.232	tINS	RF	1	R14C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/n199_s2/F
1.608	0.000	tNET	FF	1	R14C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R14C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/CLK
1.182	0.011	tHld		1	R14C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path23

Path Summary:

Slack	0.427
Data Arrival Time	1.608
Data Required Time	1.182
From	adv7513_iic_init_inst0/O_WDATA_2_s1
To	adv7513_iic_init_inst0/O_WDATA_2_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R23C49[0][A]	adv7513_iic_init_inst0/O_WDATA_2_s1/CLK
1.373	0.202	tC2Q	RR	4	R23C49[0][A]	adv7513_iic_init_inst0/O_WDATA_2_s1/Q
1.376	0.004	tNET	RR	1	R23C49[0][A]	adv7513_iic_init_inst0/n1033_s12/I2
1.608	0.232	tINS	RF	1	R23C49[0][A]	adv7513_iic_init_inst0/n1033_s12/F
1.608	0.000	tNET	FF	1	R23C49[0][A]	adv7513_iic_init_inst0/O_WDATA_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R23C49[0][A]	adv7513_iic_init_inst0/O_WDATA_2_s1/CLK
1.182	0.011	tHld		1	R23C49[0][A]	adv7513_iic_init_inst0/O_WDATA_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path24

Path Summary:

Slack	0.427
Data Arrival Time	1.608
Data Required Time	1.182
From	adv7513_iic_init_inst0/mem_cnt_6_s1
To	adv7513_iic_init_inst0/mem_cnt_6_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R20C48[1][A]	adv7513_iic_init_inst0/mem_cnt_6_s1/CLK
1.373	0.202	tC2Q	RR	3	R20C48[1][A]	adv7513_iic_init_inst0/mem_cnt_6_s1/Q
1.376	0.004	tNET	RR	1	R20C48[1][A]	adv7513_iic_init_inst0/n266_s2/I3
1.608	0.232	tINS	RF	1	R20C48[1][A]	adv7513_iic_init_inst0/n266_s2/F
1.608	0.000	tNET	FF	1	R20C48[1][A]	adv7513_iic_init_inst0/mem_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R20C48[1][A]	adv7513_iic_init_inst0/mem_cnt_6_s1/CLK
1.182	0.011	tHld		1	R20C48[1][A]	adv7513_iic_init_inst0/mem_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path25

Path Summary:

Slack	0.427
Data Arrival Time	1.611
Data Required Time	1.184
From	testpattern_inst/Color_cnt_0_s3
To	testpattern_inst/Color_cnt_0_s3
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R22C53[0][A]	testpattern_inst/Color_cnt_0_s3/CLK
1.375	0.202	tC2Q	RR	5	R22C53[0][A]	testpattern_inst/Color_cnt_0_s3/Q
1.379	0.004	tNET	RR	1	R22C53[0][A]	testpattern_inst/n918_s4/I2
1.611	0.232	tINS	RF	1	R22C53[0][A]	testpattern_inst/n918_s4/F
1.611	0.000	tNET	FF	1	R22C53[0][A]	testpattern_inst/Color_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
0.989	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
1.173	0.184	tNET	RR	1	R22C53[0][A]	testpattern_inst/Color_cnt_0_s3/CLK
1.184	0.011	tHld		1	R22C53[0][A]	testpattern_inst/Color_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_0_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	R35C52[2][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R35C52[2][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_0_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_0_s0
27.829	-0.035	tSu		1	R35C52[2][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_0_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_1_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	R35C52[2][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R35C52[2][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_1_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_1_s0
27.829	-0.035	tSu		1	R35C52[2][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_1_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_2_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	R35C52[1][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R35C52[1][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_2_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_2_s0
27.829	-0.035	tSu		1	R35C52[1][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_2_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_3_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	R35C52[1][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R35C52[1][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_3_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_3_s0
27.829	-0.035	tSu		1	R35C52[1][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_3_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_4_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	R35C52[0][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	R35C52[0][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_4_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_4_s0
27.829	-0.035	tSu		1	R35C52[0][B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_4_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_5_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR23[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR23[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_5_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_5_s0
27.829	-0.035	tSu		1	IOR23[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/dvalid_dn_5_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_0_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR9[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR9[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_0_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_0_s0
27.829	-0.035	tSu		1	IOR9[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_0_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_1_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR22[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR22[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_1_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_1_s0
27.829	-0.035	tSu		1	IOR22[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_1_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_2_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR20[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR20[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_2_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_2_s0
27.829	-0.035	tSu		1	IOR20[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_2_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_3_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR16[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR16[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_3_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_3_s0
27.829	-0.035	tSu		1	IOR16[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_3_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_4_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR9[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR9[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_4_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_4_s0
27.829	-0.035	tSu		1	IOR9[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_4_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_5_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR16[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR16[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_5_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_5_s0
27.829	-0.035	tSu		1	IOR16[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_5_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_6_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR20[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR20[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_6_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_6_s0
27.829	-0.035	tSu		1	IOR20[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_6_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_7_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR5[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR5[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_7_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_7_s0
27.829	-0.035	tSu		1	IOR5[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout2_7_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_0_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR5[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR5[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_0_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_0_s0
27.829	-0.035	tSu		1	IOR5[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_0_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_1_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR15[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR15[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_1_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_1_s0
27.829	-0.035	tSu		1	IOR15[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_1_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_2_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR4[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR4[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_2_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_2_s0
27.829	-0.035	tSu		1	IOR4[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_2_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_3_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR11[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR11[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_3_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_3_s0
27.829	-0.035	tSu		1	IOR11[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_3_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_4_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR11[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR11[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_4_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_4_s0
27.829	-0.035	tSu		1	IOR11[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_4_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_5_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR18[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR18[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_5_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_5_s0
27.829	-0.035	tSu		1	IOR18[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_5_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_6_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR2[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR2[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_6_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_6_s0
27.829	-0.035	tSu		1	IOR2[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_6_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_7_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR18[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR18[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_7_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_7_s0
27.829	-0.035	tSu		1	IOR18[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout1_7_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_0_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR2[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR2[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_0_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_0_s0
27.829	-0.035	tSu		1	IOR2[B]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_0_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_1_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR12[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR12[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_1_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_1_s0
27.829	-0.035	tSu		1	IOR12[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_1_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack	2.194
Data Arrival Time	25.635
Data Required Time	27.829
From	key_debounceN_inst0/key_n_out1_s1
To	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_2_s0
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
20.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.230	0.243	tNET	RR	1	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/CLK
21.462	0.232	tC2Q	RF	92	R36C45[1][B]	key_debounceN_inst0/key_n_out1_s1/Q
23.481	2.019	tNET	FF	1	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/I0
24.036	0.555	tINS	FF	87	R35C52[3][A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/n906_s2/F
25.635	1.599	tNET	FF	1	IOR17[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
26.667	26.667					active clock edge time
26.667	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.656	0.989	tCL	RR	466	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUT
27.899	0.243	tNET	RR	1	IOR17[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_2_s0/CLK
27.864	-0.035	tUnc				yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_2_s0
27.829	-0.035	tSu		1	IOR17[A]	yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/O_dout0_2_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	6.667
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.555, 12.598%; route: 3.619, 82.136%; tC2Q: 0.232, 5.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R8C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R8C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/CLK
1.182	0.011	tHld		1	R8C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/SDA_OEN_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R7C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/SDA_OEN_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R7C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/SDA_OEN_s1/CLK
1.182	0.011	tHld		1	R7C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/SDA_OEN_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/SCL_OEN_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R7C46[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/SCL_OEN_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R7C46[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/SCL_OEN_s1/CLK
1.182	0.011	tHld		1	R7C46[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/SCL_OEN_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path4

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_0_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R7C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R7C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_0_s1/CLK
1.182	0.011	tHld		1	R7C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path5

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_1_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R7C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R7C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_1_s1/CLK
1.182	0.011	tHld		1	R7C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path6

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_2_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R6C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R6C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_2_s1/CLK
1.182	0.011	tHld		1	R6C46[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path7

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R9C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R9C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1/CLK
1.182	0.011	tHld		1	R9C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_4_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R11C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R11C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_4_s1/CLK
1.182	0.011	tHld		1	R11C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_5_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R7C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R7C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_5_s1/CLK
1.182	0.011	tHld		1	R7C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_6_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R6C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R6C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_6_s1/CLK
1.182	0.011	tHld		1	R6C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path11

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_7_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R5C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R5C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_7_s1/CLK
1.182	0.011	tHld		1	R5C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path12

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_8_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R6C46[0][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R6C46[0][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_8_s1/CLK
1.182	0.011	tHld		1	R6C46[0][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path13

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_9_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R13C45[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C45[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_9_s1/CLK
1.182	0.011	tHld		1	R13C45[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path14

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_10_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R6C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R6C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_10_s1/CLK
1.182	0.011	tHld		1	R6C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path15

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_11_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R5C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R5C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_11_s1/CLK
1.182	0.011	tHld		1	R5C46[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path16

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_12_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R7C46[0][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R7C46[0][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_12_s1/CLK
1.182	0.011	tHld		1	R7C46[0][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_12_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_13_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R13C45[1][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C45[1][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_13_s1/CLK
1.182	0.011	tHld		1	R13C45[1][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_13_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_14_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R8C47[0][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_14_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R8C47[0][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_14_s1/CLK
1.182	0.011	tHld		1	R8C47[0][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_14_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_15_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R8C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R8C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_15_s1/CLK
1.182	0.011	tHld		1	R8C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_15_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path20

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_16_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R8C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_16_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R8C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_16_s1/CLK
1.182	0.011	tHld		1	R8C47[0][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_16_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path21

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R13C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1/CLK
1.182	0.011	tHld		1	R13C47[1][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path22

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_1_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R13C47[1][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C47[1][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_1_s1/CLK
1.182	0.011	tHld		1	R13C47[1][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path23

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R13C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1/CLK
1.182	0.011	tHld		1	R13C47[2][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path24

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_3_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R13C47[2][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R13C47[2][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_3_s1/CLK
1.182	0.011	tHld		1	R13C47[2][A]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path25

Path Summary:

Slack	1.223
Data Arrival Time	2.405
Data Required Time	1.182
From	key_debounceN_inst0/key_n_out2_s1
To	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_4_s1
Launch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]
Latch Clk	Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/CLK
1.373	0.202	tC2Q	RR	106	R36C45[0][A]	key_debounceN_inst0/key_n_out2_s1/Q
2.405	1.032	tNET	RR	1	R12C47[1][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
0.987	0.987	tCL	RR	203	PLL_R[0]	Gowin_rPLL_inst/rpll_inst/CLKOUTP
1.171	0.184	tNET	RR	1	R12C47[1][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_4_s1/CLK
1.182	0.011	tHld		1	R12C47[1][B]	I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.032, 83.634%; tC2Q: 0.202, 16.366%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	5.590
Actual Width:	6.590
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
Objects:	vs_r_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.667	0.000			active clock edge time
6.667	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
7.656	0.989	tCL	FF	Gowin_rPLL_inst/rpll_inst/CLKOUT
7.917	0.261	tNET	FF	vs_r_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.333	0.000			active clock edge time
13.333	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
14.322	0.989	tCL	RR	Gowin_rPLL_inst/rpll_inst/CLKOUT
14.507	0.184	tNET	RR	vs_r_s0/CLK

MPW2

MPW Summary:

Slack:	5.590
Actual Width:	6.590
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
Objects:	cnt_vs_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.667	0.000			active clock edge time
6.667	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
7.656	0.989	tCL	FF	Gowin_rPLL_inst/rpll_inst/CLKOUT
7.917	0.261	tNET	FF	cnt_vs_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.333	0.000			active clock edge time
13.333	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
14.322	0.989	tCL	RR	Gowin_rPLL_inst/rpll_inst/CLKOUT
14.507	0.184	tNET	RR	cnt_vs_7_s0/CLK

MPW3

MPW Summary:

Slack:	5.590
Actual Width:	6.590
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
Objects:	cnt_vs_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.667	0.000			active clock edge time
6.667	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
7.656	0.989	tCL	FF	Gowin_rPLL_inst/rpll_inst/CLKOUT
7.917	0.261	tNET	FF	cnt_vs_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.333	0.000			active clock edge time
13.333	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
14.322	0.989	tCL	RR	Gowin_rPLL_inst/rpll_inst/CLKOUT
14.507	0.184	tNET	RR	cnt_vs_3_s0/CLK

MPW4

MPW Summary:

Slack:	5.590
Actual Width:	6.590
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
Objects:	vs_dn_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.667	0.000			active clock edge time
6.667	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
7.656	0.989	tCL	FF	Gowin_rPLL_inst/rpll_inst/CLKOUT
7.917	0.261	tNET	FF	vs_dn_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.333	0.000			active clock edge time
13.333	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
14.322	0.989	tCL	RR	Gowin_rPLL_inst/rpll_inst/CLKOUT
14.507	0.184	tNET	RR	vs_dn_6_s0/CLK

MPW5

MPW Summary:

Slack:	5.590
Actual Width:	6.590
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
Objects:	hs_dn_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.667	0.000			active clock edge time
6.667	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
7.656	0.989	tCL	FF	Gowin_rPLL_inst/rpll_inst/CLKOUT
7.917	0.261	tNET	FF	hs_dn_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.333	0.000			active clock edge time
13.333	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
14.322	0.989	tCL	RR	Gowin_rPLL_inst/rpll_inst/CLKOUT
14.507	0.184	tNET	RR	hs_dn_2_s0/CLK

MPW6

MPW Summary:

Slack:	5.590
Actual Width:	6.590
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
Objects:	testpattern_inst/Color_bar_15_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.667	0.000			active clock edge time
6.667	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
7.656	0.989	tCL	FF	Gowin_rPLL_inst/rpll_inst/CLKOUT
7.917	0.261	tNET	FF	testpattern_inst/Color_bar_15_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.333	0.000			active clock edge time
13.333	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
14.322	0.989	tCL	RR	Gowin_rPLL_inst/rpll_inst/CLKOUT
14.507	0.184	tNET	RR	testpattern_inst/Color_bar_15_s0/CLK

MPW7

MPW Summary:

Slack:	5.590
Actual Width:	6.590
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
Objects:	testpattern_inst/De_hcnt_9_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.667	0.000			active clock edge time
6.667	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
7.656	0.989	tCL	FF	Gowin_rPLL_inst/rpll_inst/CLKOUT
7.917	0.261	tNET	FF	testpattern_inst/De_hcnt_9_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.333	0.000			active clock edge time
13.333	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
14.322	0.989	tCL	RR	Gowin_rPLL_inst/rpll_inst/CLKOUT
14.507	0.184	tNET	RR	testpattern_inst/De_hcnt_9_s1/CLK

MPW8

MPW Summary:

Slack:	5.590
Actual Width:	6.590
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
Objects:	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/Dout1_sum_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.667	0.000			active clock edge time
6.667	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
7.656	0.989	tCL	FF	Gowin_rPLL_inst/rpll_inst/CLKOUT
7.917	0.261	tNET	FF	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/Dout1_sum_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.333	0.000			active clock edge time
13.333	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
14.322	0.989	tCL	RR	Gowin_rPLL_inst/rpll_inst/CLKOUT
14.507	0.184	tNET	RR	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/Dout1_sum_12_s0/CLK

MPW9

MPW Summary:

Slack:	5.590
Actual Width:	6.590
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
Objects:	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/Dout1_sum_13_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.667	0.000			active clock edge time
6.667	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
7.656	0.989	tCL	FF	Gowin_rPLL_inst/rpll_inst/CLKOUT
7.917	0.261	tNET	FF	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/Dout1_sum_13_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.333	0.000			active clock edge time
13.333	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
14.322	0.989	tCL	RR	Gowin_rPLL_inst/rpll_inst/CLKOUT
14.507	0.184	tNET	RR	rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/Dout1_sum_13_s0/CLK

MPW10

MPW Summary:

Slack:	5.590
Actual Width:	6.590
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
Objects:	testpattern_inst/De_hcnt_11_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.667	0.000			active clock edge time
6.667	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
7.656	0.989	tCL	FF	Gowin_rPLL_inst/rpll_inst/CLKOUT
7.917	0.261	tNET	FF	testpattern_inst/De_hcnt_11_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.333	0.000			active clock edge time
13.333	0.000			Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
14.322	0.989	tCL	RR	Gowin_rPLL_inst/rpll_inst/CLKOUT
14.507	0.184	tNET	RR	testpattern_inst/De_hcnt_11_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
466	O_adv7513_clk_d	8.044	0.427
352	n906_7	2.163	1.523
203	sclk	2.150	0.261
106	O_led_d_0[3]	16.913	2.240
92	O_led_d_0[2]	2.150	2.169
87	n906_7	2.150	1.599
36	state[3]	15.285	0.906
34	state[0]	14.946	0.996
33	Pout_de_dn[1]	10.070	0.977
32	i2c_al	17.190	1.294

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R39C52	87.50%
R44C51	86.11%
R32C52	84.72%
R5C51	84.72%
R22C52	83.33%
R27C46	83.33%
R26C51	83.33%
R26C52	83.33%
R5C52	81.94%
R41C52	81.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add