Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\byte_to_pixel\byte_to_pixel.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\gowin_mipi_dphy\gowin_mipi_dphy.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\gowin_pll\gowin_pll.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\mipi_csi2_rx\csi2_rx.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\ov5647\bayer_to_rgb\bayer_rgb.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\ov5647\bayer_to_rgb\ram_line.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\ov5647\bayer_to_rgb\shift_line.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\ov5647\bayer_to_rgb\video_format_detect.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\ov5647\ov5647_init\I2C_Interface.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\ov5647\ov5647_init\OV5647_Controller.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\ov5647\ov5647_init\OV5647_Registers.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.02 |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Tue Mar 19 16:48:18 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | CSI_Demo_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.298s, Peak memory usage = 225.102MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 225.102MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 225.102MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 225.102MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 225.102MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 225.102MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 225.102MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 225.102MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 225.102MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 225.102MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 225.102MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 253.348MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 253.348MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 253.348MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 253.348MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 15 |
| I/O Buf | 9 |
| IBUF | 2 |
| OBUF | 7 |
| Register | 827 |
| DFFSE | 23 |
| DFFRE | 170 |
| DFFPE | 50 |
| DFFCE | 584 |
| LUT | 890 |
| LUT2 | 136 |
| LUT3 | 262 |
| LUT4 | 492 |
| ALU | 120 |
| ALU | 120 |
| INV | 14 |
| INV | 14 |
| BSRAM | 2 |
| SDPB | 2 |
| CLOCK | 1 |
| PLLA | 1 |
| MIPI_DPHY | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1024(904 LUT, 120 ALU) / 23040 | 5% |
| Register | 827 / 23685 | 4% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 827 / 23685 | 4% |
| BSRAM | 2 / 56 | 4% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| OSC_50M | Base | 10.000 | 100.0 | 0.000 | 5.000 | OSC_50M_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | OSC_50M | 100.000(MHz) | 214.420(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.336 |
| Data Arrival Time | 5.410 |
| Data Required Time | 10.746 |
| From | u_ov5647_ctrl/Regs/wait_cnt_5_s0 |
| To | u_ov5647_ctrl/Regs/wait_cnt_31_s0 |
| Launch Clk | OSC_50M[R] |
| Latch Clk | OSC_50M[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | OSC_50M | |||
| 0.000 | 0.000 | tCL | RR | 1 | OSC_50M_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 218 | OSC_50M_ibuf/O |
| 1.058 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/CLK |
| 1.440 | 0.382 | tC2Q | RR | 3 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/Q |
| 1.815 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/I0 |
| 2.341 | 0.526 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/F |
| 2.716 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s5/I0 |
| 3.242 | 0.526 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s5/F |
| 3.617 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/I1 |
| 4.134 | 0.516 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/F |
| 4.509 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/I0 |
| 5.035 | 0.526 | tINS | RR | 32 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/F |
| 5.410 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_31_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | OSC_50M | |||
| 10.000 | 0.000 | tCL | RR | 1 | OSC_50M_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 218 | OSC_50M_ibuf/O |
| 11.057 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_31_s0/CLK |
| 10.746 | -0.311 | tSu | 1 | u_ov5647_ctrl/Regs/wait_cnt_31_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
| Arrival Data Path Delay: | cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788% |
| Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 2
Path Summary:| Slack | 5.336 |
| Data Arrival Time | 5.410 |
| Data Required Time | 10.746 |
| From | u_ov5647_ctrl/Regs/wait_cnt_5_s0 |
| To | u_ov5647_ctrl/Regs/wait_cnt_0_s0 |
| Launch Clk | OSC_50M[R] |
| Latch Clk | OSC_50M[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | OSC_50M | |||
| 0.000 | 0.000 | tCL | RR | 1 | OSC_50M_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 218 | OSC_50M_ibuf/O |
| 1.058 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/CLK |
| 1.440 | 0.382 | tC2Q | RR | 3 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/Q |
| 1.815 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/I0 |
| 2.341 | 0.526 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/F |
| 2.716 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s5/I0 |
| 3.242 | 0.526 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s5/F |
| 3.617 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/I1 |
| 4.134 | 0.516 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/F |
| 4.509 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/I0 |
| 5.035 | 0.526 | tINS | RR | 32 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/F |
| 5.410 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_0_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | OSC_50M | |||
| 10.000 | 0.000 | tCL | RR | 1 | OSC_50M_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 218 | OSC_50M_ibuf/O |
| 11.057 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_0_s0/CLK |
| 10.746 | -0.311 | tSu | 1 | u_ov5647_ctrl/Regs/wait_cnt_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
| Arrival Data Path Delay: | cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788% |
| Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 3
Path Summary:| Slack | 5.336 |
| Data Arrival Time | 5.410 |
| Data Required Time | 10.746 |
| From | u_ov5647_ctrl/Regs/wait_cnt_5_s0 |
| To | u_ov5647_ctrl/Regs/wait_cnt_1_s0 |
| Launch Clk | OSC_50M[R] |
| Latch Clk | OSC_50M[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | OSC_50M | |||
| 0.000 | 0.000 | tCL | RR | 1 | OSC_50M_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 218 | OSC_50M_ibuf/O |
| 1.058 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/CLK |
| 1.440 | 0.382 | tC2Q | RR | 3 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/Q |
| 1.815 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/I0 |
| 2.341 | 0.526 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/F |
| 2.716 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s5/I0 |
| 3.242 | 0.526 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s5/F |
| 3.617 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/I1 |
| 4.134 | 0.516 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/F |
| 4.509 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/I0 |
| 5.035 | 0.526 | tINS | RR | 32 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/F |
| 5.410 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_1_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | OSC_50M | |||
| 10.000 | 0.000 | tCL | RR | 1 | OSC_50M_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 218 | OSC_50M_ibuf/O |
| 11.057 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_1_s0/CLK |
| 10.746 | -0.311 | tSu | 1 | u_ov5647_ctrl/Regs/wait_cnt_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
| Arrival Data Path Delay: | cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788% |
| Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 4
Path Summary:| Slack | 5.336 |
| Data Arrival Time | 5.410 |
| Data Required Time | 10.746 |
| From | u_ov5647_ctrl/Regs/wait_cnt_5_s0 |
| To | u_ov5647_ctrl/Regs/wait_cnt_2_s0 |
| Launch Clk | OSC_50M[R] |
| Latch Clk | OSC_50M[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | OSC_50M | |||
| 0.000 | 0.000 | tCL | RR | 1 | OSC_50M_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 218 | OSC_50M_ibuf/O |
| 1.058 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/CLK |
| 1.440 | 0.382 | tC2Q | RR | 3 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/Q |
| 1.815 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/I0 |
| 2.341 | 0.526 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/F |
| 2.716 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s5/I0 |
| 3.242 | 0.526 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s5/F |
| 3.617 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/I1 |
| 4.134 | 0.516 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/F |
| 4.509 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/I0 |
| 5.035 | 0.526 | tINS | RR | 32 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/F |
| 5.410 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_2_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | OSC_50M | |||
| 10.000 | 0.000 | tCL | RR | 1 | OSC_50M_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 218 | OSC_50M_ibuf/O |
| 11.057 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_2_s0/CLK |
| 10.746 | -0.311 | tSu | 1 | u_ov5647_ctrl/Regs/wait_cnt_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
| Arrival Data Path Delay: | cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788% |
| Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 5
Path Summary:| Slack | 5.336 |
| Data Arrival Time | 5.410 |
| Data Required Time | 10.746 |
| From | u_ov5647_ctrl/Regs/wait_cnt_5_s0 |
| To | u_ov5647_ctrl/Regs/wait_cnt_3_s0 |
| Launch Clk | OSC_50M[R] |
| Latch Clk | OSC_50M[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | OSC_50M | |||
| 0.000 | 0.000 | tCL | RR | 1 | OSC_50M_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 218 | OSC_50M_ibuf/O |
| 1.058 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/CLK |
| 1.440 | 0.382 | tC2Q | RR | 3 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/Q |
| 1.815 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/I0 |
| 2.341 | 0.526 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/F |
| 2.716 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s5/I0 |
| 3.242 | 0.526 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s5/F |
| 3.617 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/I1 |
| 4.134 | 0.516 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/F |
| 4.509 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/I0 |
| 5.035 | 0.526 | tINS | RR | 32 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/F |
| 5.410 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_3_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | OSC_50M | |||
| 10.000 | 0.000 | tCL | RR | 1 | OSC_50M_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 218 | OSC_50M_ibuf/O |
| 11.057 | 0.375 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_3_s0/CLK |
| 10.746 | -0.311 | tSu | 1 | u_ov5647_ctrl/Regs/wait_cnt_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
| Arrival Data Path Delay: | cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788% |
| Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |