Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\gw_jtag.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\csi_rx_demo_5a25\fpga_proj\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-6
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Oct 25 16:26:55 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.533s, Peak memory usage = 45.488MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 45.488MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 45.488MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 45.488MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 45.488MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 45.488MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 45.488MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 45.488MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 45.488MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 45.488MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 45.488MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 45.488MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 57.711MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 57.711MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 57.711MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 57.711MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 88
I/O Buf 88
    IBUF 87
    OBUF 1
Register 587
    DFFPE 36
    DFFCE 551
LUT 456
    LUT2 53
    LUT3 93
    LUT4 310
MUX 1
    MUX16 1
ALU 10
    ALU 10
INV 4
    INV 4
BSRAM 10
    SDPX9B 10
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 478(468 LUT, 10 ALU) / 23040 3%
Register 587 / 23685 3%
  --Register as Latch 0 / 23685 0%
  --Register as FF 587 / 23685 3%
BSRAM 10 / 56 18%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
byte_clk Base 10.000 100.0 0.000 5.000 byte_clk_ibuf/I
u_icon_top/n19_6 Base 10.000 100.0 0.000 5.000 u_icon_top/n19_s2/O
u_la0_top/n15_6 Base 10.000 100.0 0.000 5.000 u_la0_top/n15_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 byte_clk 100.0(MHz) 268.4(MHz) 5 TOP
2 u_icon_top/n19_6 100.0(MHz) 627.0(MHz) 2 TOP
3 u_la0_top/n15_6 100.0(MHz) 1577.9(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.274
Data Arrival Time 4.285
Data Required Time 10.559
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 242 byte_clk_ibuf/O
0.870 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.253 0.382 tC2Q RR 15 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.440 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s10/I0
1.966 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n569_s10/F
2.154 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s8/I0
2.680 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n569_s8/F
2.867 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s5/I1
3.384 0.516 tINS RR 12 u_la0_top/u_ao_mem_ctrl/n569_s5/F
3.571 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
4.097 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
4.285 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 242 byte_clk_ibuf/O
10.870 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.559 -0.311 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 2.095, 61.347%; route: 0.938, 27.452%; tC2Q: 0.382, 11.201%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 2

Path Summary:
Slack 6.538
Data Arrival Time 4.021
Data Required Time 10.559
From u_la0_top/u_ao_match_0/match_sep_s0
To u_la0_top/trigger_seq_start_s1
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 242 byte_clk_ibuf/O
0.870 0.188 tNET RR 1 u_la0_top/u_ao_match_0/match_sep_s0/CLK
1.253 0.382 tC2Q RR 1 u_la0_top/u_ao_match_0/match_sep_s0/Q
1.440 0.188 tNET RR 1 u_la0_top/triger_level_cnt_3_s5/I0
1.966 0.526 tINS RR 1 u_la0_top/triger_level_cnt_3_s5/F
2.154 0.188 tNET RR 1 u_la0_top/triger_level_cnt_3_s4/I0
2.680 0.526 tINS RR 4 u_la0_top/triger_level_cnt_3_s4/F
2.867 0.188 tNET RR 1 u_la0_top/n3552_s1/I1
3.384 0.516 tINS RR 1 u_la0_top/n3552_s1/F
3.571 0.188 tNET RR 1 u_la0_top/trigger_seq_start_s3/I3
3.834 0.262 tINS RR 1 u_la0_top/trigger_seq_start_s3/F
4.021 0.188 tNET RR 1 u_la0_top/trigger_seq_start_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 242 byte_clk_ibuf/O
10.870 0.188 tNET RR 1 u_la0_top/trigger_seq_start_s1/CLK
10.559 -0.311 tSu 1 u_la0_top/trigger_seq_start_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 1.831, 58.112%; route: 0.938, 29.750%; tC2Q: 0.382, 12.138%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 3

Path Summary:
Slack 6.586
Data Arrival Time 4.220
Data Required Time 10.806
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 242 byte_clk_ibuf/O
0.870 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.253 0.382 tC2Q RR 15 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.440 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s10/I0
1.966 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n569_s10/F
2.154 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s8/I0
2.680 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n569_s8/F
2.867 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s5/I1
3.384 0.516 tINS RR 12 u_la0_top/u_ao_mem_ctrl/n569_s5/F
3.571 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n579_s3/I2
4.032 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n579_s3/F
4.220 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 242 byte_clk_ibuf/O
10.870 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
10.806 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 2.030, 60.597%; route: 0.938, 27.985%; tC2Q: 0.382, 11.418%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 4

Path Summary:
Slack 6.586
Data Arrival Time 4.220
Data Required Time 10.806
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 242 byte_clk_ibuf/O
0.870 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.253 0.382 tC2Q RR 15 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.440 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s10/I0
1.966 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n569_s10/F
2.154 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s8/I0
2.680 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n569_s8/F
2.867 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s5/I1
3.384 0.516 tINS RR 12 u_la0_top/u_ao_mem_ctrl/n569_s5/F
3.571 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n578_s1/I2
4.032 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n578_s1/F
4.220 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 242 byte_clk_ibuf/O
10.870 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.806 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 2.030, 60.597%; route: 0.938, 27.985%; tC2Q: 0.382, 11.418%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 5

Path Summary:
Slack 6.586
Data Arrival Time 4.220
Data Required Time 10.806
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 242 byte_clk_ibuf/O
0.870 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.253 0.382 tC2Q RR 15 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.440 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s10/I0
1.966 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n569_s10/F
2.154 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s8/I0
2.680 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n569_s8/F
2.867 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n569_s5/I1
3.384 0.516 tINS RR 12 u_la0_top/u_ao_mem_ctrl/n569_s5/F
3.571 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n576_s1/I2
4.032 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n576_s1/F
4.220 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 242 byte_clk_ibuf/O
10.870 0.188 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.806 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 2.030, 60.597%; route: 0.938, 27.985%; tC2Q: 0.382, 11.418%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%