Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\MIPI_DSI_CSI2_RX\data\dsi_csi2_rx_wrap.v
D:\Programs\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\MIPI_DSI_CSI2_RX\data\dsi_csi2_rx.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW2A-LV18QN88C7/I6
Device GW2A-18
Device Version C
Created Time Thu Aug 10 11:27:10 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Dsi_Rx_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.17s, Peak memory usage = 34.297MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 34.297MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 34.297MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 34.297MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 34.297MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 34.297MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.297MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 34.297MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.297MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 34.297MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 34.297MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 34.297MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 50.121MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 50.121MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 50.121MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 50.121MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 113
I/O Buf 113
    IBUF 41
    OBUF 72
Register 227
    DFF 64
    DFFE 88
    DFFS 32
    DFFC 37
    DFFCE 6
LUT 264
    LUT2 10
    LUT3 135
    LUT4 119
ALU 9
    ALU 9
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 275(266 LUT, 9 ALU) / 20736 2%
Register 227 / 15750 2%
  --Register as Latch 0 / 15750 0%
  --Register as FF 227 / 15750 2%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_BYTE_CLK Base 10.000 100.0 0.000 5.000 I_BYTE_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_BYTE_CLK 100.0(MHz) 179.2(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.420
Data Arrival Time 6.614
Data Required Time 11.034
From u_dsi_csi2/rDataReg_9_s0
To u_dsi_csi2/rLpEn_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 227 I_BYTE_CLK_ibuf/O
1.078 0.225 tNET RR 1 u_dsi_csi2/rDataReg_9_s0/CLK
1.368 0.290 tC2Q RF 2 u_dsi_csi2/rDataReg_9_s0/Q
1.664 0.296 tNET FF 1 u_dsi_csi2/wHeader_1_s1/I1
2.358 0.694 tINS FF 1 u_dsi_csi2/wHeader_1_s1/F
2.654 0.296 tNET FF 1 u_dsi_csi2/wHeader_1_s0/I1
3.348 0.694 tINS FF 6 u_dsi_csi2/wHeader_1_s0/F
3.644 0.296 tNET FF 1 u_dsi_csi2/n1188_s5/I1
4.338 0.694 tINS FF 1 u_dsi_csi2/n1188_s5/F
4.634 0.296 tNET FF 1 u_dsi_csi2/n1188_s2/I1
5.328 0.694 tINS FF 3 u_dsi_csi2/n1188_s2/F
5.624 0.296 tNET FF 1 u_dsi_csi2/n1130_s2/I1
6.318 0.694 tINS FF 1 u_dsi_csi2/n1130_s2/F
6.614 0.296 tNET FF 1 u_dsi_csi2/rLpEn_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 227 I_BYTE_CLK_ibuf/O
11.078 0.225 tNET RR 1 u_dsi_csi2/rLpEn_s0/CLK
11.034 -0.044 tSu 1 u_dsi_csi2/rLpEn_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 3.469, 62.655%; route: 1.778, 32.107%; tC2Q: 0.290, 5.238%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 2

Path Summary:
Slack 4.468
Data Arrival Time 6.567
Data Required Time 11.034
From u_dsi_csi2/rDataReg_9_s0
To u_dsi_csi2/rSpEn_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 227 I_BYTE_CLK_ibuf/O
1.078 0.225 tNET RR 1 u_dsi_csi2/rDataReg_9_s0/CLK
1.368 0.290 tC2Q RF 2 u_dsi_csi2/rDataReg_9_s0/Q
1.664 0.296 tNET FF 1 u_dsi_csi2/wHeader_1_s1/I1
2.358 0.694 tINS FF 1 u_dsi_csi2/wHeader_1_s1/F
2.654 0.296 tNET FF 1 u_dsi_csi2/wHeader_1_s0/I1
3.348 0.694 tINS FF 6 u_dsi_csi2/wHeader_1_s0/F
3.644 0.296 tNET FF 1 u_dsi_csi2/n1188_s7/I1
4.338 0.694 tINS FF 1 u_dsi_csi2/n1188_s7/F
4.634 0.296 tNET FF 1 u_dsi_csi2/n1188_s3/I0
5.281 0.646 tINS FF 2 u_dsi_csi2/n1188_s3/F
5.577 0.296 tNET FF 1 u_dsi_csi2/n1118_s1/I1
6.271 0.694 tINS FF 1 u_dsi_csi2/n1118_s1/F
6.567 0.296 tNET FF 1 u_dsi_csi2/rSpEn_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 227 I_BYTE_CLK_ibuf/O
11.078 0.225 tNET RR 1 u_dsi_csi2/rSpEn_s0/CLK
11.034 -0.044 tSu 1 u_dsi_csi2/rSpEn_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 3.421, 62.332%; route: 1.778, 32.384%; tC2Q: 0.290, 5.284%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 3

Path Summary:
Slack 4.468
Data Arrival Time 6.567
Data Required Time 11.034
From u_dsi_csi2/rDataReg_9_s0
To u_dsi_csi2/rLpPeriod_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 227 I_BYTE_CLK_ibuf/O
1.078 0.225 tNET RR 1 u_dsi_csi2/rDataReg_9_s0/CLK
1.368 0.290 tC2Q RF 2 u_dsi_csi2/rDataReg_9_s0/Q
1.664 0.296 tNET FF 1 u_dsi_csi2/wHeader_1_s1/I1
2.358 0.694 tINS FF 1 u_dsi_csi2/wHeader_1_s1/F
2.654 0.296 tNET FF 1 u_dsi_csi2/wHeader_1_s0/I1
3.348 0.694 tINS FF 6 u_dsi_csi2/wHeader_1_s0/F
3.644 0.296 tNET FF 1 u_dsi_csi2/n1188_s5/I1
4.338 0.694 tINS FF 1 u_dsi_csi2/n1188_s5/F
4.634 0.296 tNET FF 1 u_dsi_csi2/n1188_s2/I1
5.328 0.694 tINS FF 3 u_dsi_csi2/n1188_s2/F
5.624 0.296 tNET FF 1 u_dsi_csi2/n820_s1/I0
6.271 0.646 tINS FF 1 u_dsi_csi2/n820_s1/F
6.567 0.296 tNET FF 1 u_dsi_csi2/rLpPeriod_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 227 I_BYTE_CLK_ibuf/O
11.078 0.225 tNET RR 1 u_dsi_csi2/rLpPeriod_s0/CLK
11.034 -0.044 tSu 1 u_dsi_csi2/rLpPeriod_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 3.421, 62.332%; route: 1.778, 32.384%; tC2Q: 0.290, 5.284%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 4

Path Summary:
Slack 4.499
Data Arrival Time 6.536
Data Required Time 11.034
From u_dsi_csi2/rDataReg_9_s0
To u_dsi_csi2/rHeader_0_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 227 I_BYTE_CLK_ibuf/O
1.078 0.225 tNET RR 1 u_dsi_csi2/rDataReg_9_s0/CLK
1.368 0.290 tC2Q RF 2 u_dsi_csi2/rDataReg_9_s0/Q
1.664 0.296 tNET FF 1 u_dsi_csi2/wHeader_1_s1/I1
2.358 0.694 tINS FF 1 u_dsi_csi2/wHeader_1_s1/F
2.654 0.296 tNET FF 1 u_dsi_csi2/wHeader_1_s0/I1
3.348 0.694 tINS FF 6 u_dsi_csi2/wHeader_1_s0/F
3.644 0.296 tNET FF 1 u_dsi_csi2/n1188_s5/I1
4.338 0.694 tINS FF 1 u_dsi_csi2/n1188_s5/F
4.634 0.296 tNET FF 1 u_dsi_csi2/n1188_s2/I1
5.328 0.694 tINS FF 3 u_dsi_csi2/n1188_s2/F
5.624 0.296 tNET FF 1 u_dsi_csi2/n1188_s1/I0
6.311 0.686 tINS FR 32 u_dsi_csi2/n1188_s1/F
6.536 0.225 tNET RR 1 u_dsi_csi2/rHeader_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 227 I_BYTE_CLK_ibuf/O
11.078 0.225 tNET RR 1 u_dsi_csi2/rHeader_0_s0/CLK
11.034 -0.044 tSu 1 u_dsi_csi2/rHeader_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 3.461, 63.422%; route: 1.706, 31.264%; tC2Q: 0.290, 5.314%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 5

Path Summary:
Slack 4.499
Data Arrival Time 6.536
Data Required Time 11.034
From u_dsi_csi2/rDataReg_9_s0
To u_dsi_csi2/rHeader_1_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 227 I_BYTE_CLK_ibuf/O
1.078 0.225 tNET RR 1 u_dsi_csi2/rDataReg_9_s0/CLK
1.368 0.290 tC2Q RF 2 u_dsi_csi2/rDataReg_9_s0/Q
1.664 0.296 tNET FF 1 u_dsi_csi2/wHeader_1_s1/I1
2.358 0.694 tINS FF 1 u_dsi_csi2/wHeader_1_s1/F
2.654 0.296 tNET FF 1 u_dsi_csi2/wHeader_1_s0/I1
3.348 0.694 tINS FF 6 u_dsi_csi2/wHeader_1_s0/F
3.644 0.296 tNET FF 1 u_dsi_csi2/n1188_s5/I1
4.338 0.694 tINS FF 1 u_dsi_csi2/n1188_s5/F
4.634 0.296 tNET FF 1 u_dsi_csi2/n1188_s2/I1
5.328 0.694 tINS FF 3 u_dsi_csi2/n1188_s2/F
5.624 0.296 tNET FF 1 u_dsi_csi2/n1188_s1/I0
6.311 0.686 tINS FR 32 u_dsi_csi2/n1188_s1/F
6.536 0.225 tNET RR 1 u_dsi_csi2/rHeader_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 227 I_BYTE_CLK_ibuf/O
11.078 0.225 tNET RR 1 u_dsi_csi2/rHeader_1_s0/CLK
11.034 -0.044 tSu 1 u_dsi_csi2/rHeader_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 3.461, 63.422%; route: 1.706, 31.264%; tC2Q: 0.290, 5.314%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%