Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\IP_verify\1.9.7\IP_web\Gowin_LVDS71_RX_LVDS41_TX_refDesign\project\src\bit_align_ctl.v E:\IP_verify\1.9.7\IP_web\Gowin_LVDS71_RX_LVDS41_TX_refDesign\project\src\bus_sync.v E:\IP_verify\1.9.7\IP_web\Gowin_LVDS71_RX_LVDS41_TX_refDesign\project\src\fifo48b_24b.v E:\IP_verify\1.9.7\IP_web\Gowin_LVDS71_RX_LVDS41_TX_refDesign\project\src\lvds_7_to_1_rx.v E:\IP_verify\1.9.7\IP_web\Gowin_LVDS71_RX_LVDS41_TX_refDesign\project\src\LVDS41TX_1CLK6DATA.v E:\IP_verify\1.9.7\IP_web\Gowin_LVDS71_RX_LVDS41_TX_refDesign\project\src\lvds71_lvds41_top.v E:\IP_verify\1.9.7\IP_web\Gowin_LVDS71_RX_LVDS41_TX_refDesign\project\src\LVDS71RX_1CLK8DATA.v E:\IP_verify\1.9.7\IP_web\Gowin_LVDS71_RX_LVDS41_TX_refDesign\project\src\word_align_ctl.v |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Verision | GowinSynthesis V1.9.7Beta |
| Created Time | Thu Sep 24 15:21:19 2020 |
| Legal Announcement | Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved. |
Design Settings
| Top Level Module: | lvds71_lvds41_top |
| Part Number: | GW2A-LV18LQ144C8/I7 |
| Device: | GW2A-18 |
Resource
Resource Usage Summary
| I/O Port | 79 |
| I/O Buf | 42 |
| Input Buf | 10 |
| Output Buf | 32 |
| Inout Buf | 0 |
| Register | 683 |
| DFF | 10 |
| DFFE | 33 |
| DFFPE | 4 |
| DFFC | 45 |
| DFFCE | 591 |
| LUT | 1193 |
| LUT2 | 45 |
| LUT3 | 447 |
| LUT4 | 701 |
| ALU | 42 |
| ALU | 42 |
| INV | 10 |
| INV | 10 |
| IOLOGIC | 37 |
| IVIDEO | 9 |
| OSER4 | 28 |
| CLOCK | 7 |
| PLL | 1 |
| CLKDIV | 5 |
| rPLL | 1 |
Resource Utilization Summary
| Logic | 1245(1203 LUTs, 42 ALUs) / 20736 | 6% |
| Register | 683 / 15909 | 4% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| RCLK_in | Base | 9.259 | 108.0 | 0.000 | 4.630 | RCLK_in_ibuf/I | ||
| rx_inst/lvds_71_rx/pll_inst/CLKOUT.default_gen_clk | Generated | 2.646 | 378.0 | 0.000 | 1.323 | RCLK_in_ibuf/I | RCLK_in | rx_inst/lvds_71_rx/pll_inst/CLKOUT |
| rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk | Generated | 2.646 | 378.0 | 0.000 | 1.323 | RCLK_in_ibuf/I | RCLK_in | rx_inst/lvds_71_rx/pll_inst/CLKOUTP |
| rx_inst/lvds_71_rx/pll_inst/CLKOUTD.default_gen_clk | Generated | 5.291 | 189.0 | 0.000 | 2.646 | RCLK_in_ibuf/I | RCLK_in | rx_inst/lvds_71_rx/pll_inst/CLKOUTD |
| rx_inst/lvds_71_rx/pll_inst/CLKOUTD3.default_gen_clk | Generated | 7.937 | 126.0 | 0.000 | 3.968 | RCLK_in_ibuf/I | RCLK_in | rx_inst/lvds_71_rx/pll_inst/CLKOUTD3 |
| rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk | Generated | 32.407 | 30.9 | 0.000 | 16.204 | RCLK_in_ibuf/I | RCLK_in | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT |
| pll_inst/CLKOUT.default_gen_clk | Generated | 16.204 | 61.7 | 0.000 | 8.102 | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk | pll_inst/CLKOUT |
| pll_inst/CLKOUTP.default_gen_clk | Generated | 16.204 | 61.7 | 4.051 | 12.153 | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk | pll_inst/CLKOUTP |
| pll_inst/CLKOUTD.default_gen_clk | Generated | 32.407 | 30.9 | 0.000 | 16.204 | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk | pll_inst/CLKOUTD |
| pll_inst/CLKOUTD3.default_gen_clk | Generated | 48.611 | 20.6 | 0.000 | 24.306 | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk | pll_inst/CLKOUTD3 |
| U_TX3/Inst3_CLKDIVC/CLKOUT.default_gen_clk | Generated | 32.407 | 30.9 | 0.000 | 16.204 | pll_inst/CLKOUT | pll_inst/CLKOUT.default_gen_clk | U_TX3/Inst3_CLKDIVC/CLKOUT |
| U_TX2/Inst3_CLKDIVC/CLKOUT.default_gen_clk | Generated | 32.407 | 30.9 | 0.000 | 16.204 | pll_inst/CLKOUT | pll_inst/CLKOUT.default_gen_clk | U_TX2/Inst3_CLKDIVC/CLKOUT |
| U_TX1/Inst3_CLKDIVC/CLKOUT.default_gen_clk | Generated | 32.407 | 30.9 | 0.000 | 16.204 | pll_inst/CLKOUT | pll_inst/CLKOUT.default_gen_clk | U_TX1/Inst3_CLKDIVC/CLKOUT |
| U_TX0/Inst3_CLKDIVC/CLKOUT.default_gen_clk | Generated | 32.407 | 30.9 | 0.000 | 16.204 | pll_inst/CLKOUT | pll_inst/CLKOUT.default_gen_clk | U_TX0/Inst3_CLKDIVC/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | RCLK_in | 108.0 MHz | 272.9 MHz | 5 | TOP |
| 2 | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk | 30.9 MHz | 275.0 MHz | 5 | TOP |
| 3 | pll_inst/CLKOUT.default_gen_clk | 61.7 MHz | 184.7 MHz | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1 |
| Data Arrival Time | 6 |
| Data Required Time | 6 |
| From | rx_inst/lvds_71_rx/Inst8_IDDRX71A |
| To | rx_inst/lvds_71_rx/Inst8_IDDRX71A |
| Launch Clk | RCLK_in[R] |
| Latch Clk | rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk[F] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 4.629 | 0 | tCL | FF | 1 | RCLK_in_ibuf/I |
| 5.317 | 0.687 | tINS | FF | 151 | RCLK_in_ibuf/O |
| 5.554 | 0.237 | tNET | FF | 1 | rx_inst/lvds_71_rx/Inst8_IDDRX71A/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0 | 0 | tCL | RR | 1 | rx_inst/lvds_71_rx/pll_inst/CLKOUTP |
| 0.18 | 0.18 | tNET | RR | 1 | rx_inst/lvds_71_rx/eclko_s1/I1 |
| 0.75 | 0.57 | tINS | RR | 10 | rx_inst/lvds_71_rx/eclko_s1/F |
| 0.93 | 0.18 | tNET | RR | 1 | rx_inst/lvds_71_rx/Inst8_IDDRX71A/FCLK |
Path Statistic:
| Clock Skew: | 0 |
| Hold Relationship: | 1 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.688, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.237, 100.000% |
| Required Clock Path Delay: | cell: 0.570, 61.290%; route: 0.360, 38.710% |
Path 2
Path Summary:| Slack | 0.710 |
| Data Arrival Time | 14.813 |
| Data Required Time | 15.523 |
| From | rx_inst/lvds_71_rx/Inst8_IDDRX71A |
| To | rx_inst/lvds_71_rx/Inst8_IDDRX71A |
| Launch Clk | RCLK_in[F] |
| Latch Clk | rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk[F] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 4.629 | 0 | tCL | FF | 1 | RCLK_in_ibuf/I |
| 5.317 | 0.687 | tINS | FF | 151 | RCLK_in_ibuf/O |
| 5.554 | 0.237 | tNET | FF | 1 | rx_inst/lvds_71_rx/Inst8_IDDRX71A/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.322 | 0 | tCL | FF | 1 | rx_inst/lvds_71_rx/pll_inst/CLKOUTP |
| 1.559 | 0.237 | tNET | FF | 1 | rx_inst/lvds_71_rx/eclko_s1/I1 |
| 2.114 | 0.555 | tINS | FF | 10 | rx_inst/lvds_71_rx/eclko_s1/F |
| 2.351 | 0.237 | tNET | FF | 1 | rx_inst/lvds_71_rx/Inst8_IDDRX71A/FCLK |
Path Statistic:
| Clock Skew: | 0.584 |
| Hold Relationship: | 0.661 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 1.375, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.237, 100.000% |
| Required Clock Path Delay: | cell: 1.125, 57.427%; route: 0.834, 42.573% |
Path 3
Path Summary:| Slack | 0.737 |
| Data Arrival Time | 98.042 |
| Data Required Time | 98.779 |
| From | rx_inst/wd_aln_ctl_inst/slip_s1 |
| To | rx_inst/lvds_71_rx/Inst6_CLKDIVC |
| Launch Clk | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R] |
| Latch Clk | rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.170 | 0.170 | tCL | RR | 510 | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT |
| 0.350 | 0.18 | tNET | RR | 1 | rx_inst/wd_aln_ctl_inst/slip_s1/CLK |
| 0.582 | 0.232 | tC2Q | RF | 10 | rx_inst/wd_aln_ctl_inst/slip_s1/Q |
| 0.819 | 0.237 | tNET | FF | 1 | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CALIB |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0 | 0 | tCL | RR | 1 | rx_inst/lvds_71_rx/pll_inst/CLKOUTP |
| 0.18 | 0.18 | tNET | RR | 1 | rx_inst/lvds_71_rx/eclko_s1/I1 |
| 0.75 | 0.57 | tINS | RR | 10 | rx_inst/lvds_71_rx/eclko_s1/F |
| 0.93 | 0.18 | tNET | RR | 5 | rx_inst/lvds_71_rx/Inst6_CLKDIVC/HCLKIN |
Path Statistic:
| Clock Skew: | 1.164 |
| Hold Relationship: | 0.661 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 1.375, 88.424%; route: 0.180, 11.576% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 1.695, 58.671%; route: 1.194, 41.329% |
Path 4
Path Summary:| Slack | 0.737 |
| Data Arrival Time | 98.042 |
| Data Required Time | 98.779 |
| From | rx_inst/wd_aln_ctl_inst/slip_s1 |
| To | rx_inst/lvds_71_rx/Inst7_IDDRX71A0 |
| Launch Clk | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R] |
| Latch Clk | rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.170 | 0.170 | tCL | RR | 510 | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT |
| 0.350 | 0.18 | tNET | RR | 1 | rx_inst/wd_aln_ctl_inst/slip_s1/CLK |
| 0.582 | 0.232 | tC2Q | RF | 10 | rx_inst/wd_aln_ctl_inst/slip_s1/Q |
| 0.819 | 0.237 | tNET | FF | 1 | rx_inst/lvds_71_rx/Inst7_IDDRX71A0/CALIB |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0 | 0 | tCL | RR | 1 | rx_inst/lvds_71_rx/pll_inst/CLKOUTP |
| 0.18 | 0.18 | tNET | RR | 1 | rx_inst/lvds_71_rx/eclko_s1/I1 |
| 0.75 | 0.57 | tINS | RR | 10 | rx_inst/lvds_71_rx/eclko_s1/F |
| 0.93 | 0.18 | tNET | RR | 1 | rx_inst/lvds_71_rx/Inst7_IDDRX71A0/FCLK |
Path Statistic:
| Clock Skew: | 1.743 |
| Hold Relationship: | 0.661 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 1.375, 79.251%; route: 0.360, 20.749% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861% |
| Required Clock Path Delay: | cell: 2.265, 59.309%; route: 1.554, 40.691% |
Path 5
Path Summary:| Slack | 0.737 |
| Data Arrival Time | 98.042 |
| Data Required Time | 98.779 |
| From | rx_inst/wd_aln_ctl_inst/slip_s1 |
| To | rx_inst/lvds_71_rx/Inst7_IDDRX71A1 |
| Launch Clk | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R] |
| Latch Clk | rx_inst/lvds_71_rx/pll_inst/CLKOUTP.default_gen_clk[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.170 | 0.170 | tCL | RR | 510 | rx_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT |
| 0.350 | 0.18 | tNET | RR | 1 | rx_inst/wd_aln_ctl_inst/slip_s1/CLK |
| 0.582 | 0.232 | tC2Q | RF | 10 | rx_inst/wd_aln_ctl_inst/slip_s1/Q |
| 0.819 | 0.237 | tNET | FF | 1 | rx_inst/lvds_71_rx/Inst7_IDDRX71A1/CALIB |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0 | 0 | tCL | RR | 1 | rx_inst/lvds_71_rx/pll_inst/CLKOUTP |
| 0.18 | 0.18 | tNET | RR | 1 | rx_inst/lvds_71_rx/eclko_s1/I1 |
| 0.75 | 0.57 | tINS | RR | 10 | rx_inst/lvds_71_rx/eclko_s1/F |
| 0.93 | 0.18 | tNET | RR | 1 | rx_inst/lvds_71_rx/Inst7_IDDRX71A1/FCLK |
Path Statistic:
| Clock Skew: | 2.322 |
| Hold Relationship: | 0.661 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 1.375, 71.802%; route: 0.540, 28.198% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.711, 75.398%; tC2Q: 0.232, 24.602% |
| Required Clock Path Delay: | cell: 2.835, 59.697%; route: 1.914, 40.303% |
Summary
| Total Warnings: | 39 |
| Total Informations: | 35 |
Synthesis completed successfully!
Process took 0h:0m:7s realtime, 0h:0m:6s cputime
Memory peak: 329.8MB