________________________________________________________________________
	  Example LVDS71_RX_LVDS41_TX Design Read Me
-------------------------------------------------------------------------
Object device:GW2A-18-LQFP144
---------------------------------------------------------------------------
File List:
---------------------------------------------------------------------------
.
|-- doc
|   `-- LVDS71_RX_LVDS41_TX_readme.txt     -->  Read Me file (this file)
|-- tb 
|   `--tb.v                         -->  TestBench for Example
LVDS71_RX_LVDS41_TX design
|-- simulate_vo
|   |-- LVDS71_RX_LVDS41_TX.vo      -->  Verilog simulation File for tb
|   |-- vcs.sh						-->  Verilog simulation File
|   |-- verdi.sh						-->  Verilog simulation File
|-- project
|   `-- LVDS71_RX_LVDS41_TX.gprj        -->  GowinYunYuan Project File for Example Design
|   `-- LVDS71_RX_LVDS41_TX.gprj.user   -->  GowinYunYuan Project File for Example Design
|   |-- impl
|   |   `-- dualpin_config.ini
|   |   `-- synthesis_config.ini    -->  Synplify_Pro Config File for Example Design
|   |   |-- synthesize
|   |   |-- pnr
|   |-- src                          
|       |-- bit_align_ctl.v         -->  File for GowinYunYuan Project 
|       |-- bus_sync.v              -->  File for GowinYunYuan Project
|       |-- fifo48b_24b.v           -->  File for GowinYunYuan Project
|       |-- LVDS41TX_1CLK6DATA.v    -->  File for GowinYunYuan Project
|       |-- lvds71_lvds41_top.v     -->  File for GowinYunYuan Project
|       |-- LVDS71RX_1CLK8DATA.v    -->  File for GowinYunYuan Project
|       |-- lvds_7_to_1_rx.v        -->  File for GowinYunYuan Project
|       |-- word_align_ctl.v        -->  File for GowinYunYuan Project
|       |-- LVDS71_RX_LVDS41_TX.sdc -->  File for GowinYunYuan Project
|       |-- LVDS71_RX_LVDS41_TX.cst -->  File for GowinYunYuan Project

 

---------------------------------------------------------------------------------------------------------------
HOW TO OPEN A PROJECT IN GowinYunYuan:
---------------------------------------------------------------------------------------------------------------
1. Unzip the respective design files.
2. Launch GowinYunYuan and select "File -> Open -> Project"
3. In the Open Project dialog, enter the Project location -- "project",select select the project"LVDS71_RX_LVDS41_TX.gprj".
4. Click Finish. Now the project is successfully loaded. 

---------------------------------------------------------------------------------------------------------------
HOW TO RUN SYNTHESIZE, PLACE AND ROUTE, IP CORE GENERATION, AND TIMING ANALYSIS IN GowinYunYuan:
---------------------------------------------------------------------------------------------------------------

1. Click the Process tab in the process panel of the GowinYunYuan dashboard. 
   Double click on Synthsize(Synplify Pro). This will bring the design through synthesis.
2. Click the Process tab in the process panel of the GowinYunYuan dashboard. 
   Double click on Place & Route. This will bring the design through mapping, place and route.
3. Once Place & Route is done, user can double click on Timing Analysis Report to get 
   the timing analysis result.
4. Click on "Project -> Configuration -> Place & Route" to configurate the Post-Place File 
   and SDF File of the design.
----------------------------------------------------------------------------------------------------------------

HOW TO RUN SIMULATION
1. User can run functional simulation by software VCS. 
2. User can check waveform by software Verdi.
----------------------------------------------------------------------------------------------------------------


