Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.10\Gowin_FP_Sqrt_RefDesign\proj\impl\gwsynthesis\FP_Sqrt.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.10\Gowin_FP_Sqrt_RefDesign\proj\src\FP_Sqrt.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.10\Gowin_FP_Sqrt_RefDesign\proj\src\FP_Sqrt.sdc
Tool Version	V1.9.10 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Thu Jun 20 13:47:25 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	7286
Numbers of Endpoints Analyzed	7381
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	20.000	50.000	0.000	10.000			clk
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	72.916(MHz)	14	TOP
2	tck_pad_i	20.000(MHz)	126.908(MHz)	5	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.423	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.729	5.503
2	2.824	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.707	5.370
3	2.861	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.704	5.336
4	3.149	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.704	5.049
5	3.197	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.749	4.955
6	3.350	gw_gao_inst_0/u_la0_top/capture_windows_num_2_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.707	4.844
7	3.423	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.706	4.773
8	3.506	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.751	4.644
9	3.506	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.751	4.644
10	3.506	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.751	4.644
11	3.547	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.749	4.605
12	3.576	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.749	4.576
13	3.589	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.700	4.365
14	3.612	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.749	4.540
15	3.612	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.749	4.540
16	3.726	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.751	4.424
17	3.983	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_5_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.706	4.213
18	4.128	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.706	4.068
19	4.149	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.698	3.806
20	4.176	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.691	3.788
21	4.252	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.751	3.898
22	4.561	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.691	3.650
23	4.734	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.698	3.469
24	4.839	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.726	3.336
25	4.851	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_2_s0/RESET	tck_pad_i:[R]	clk:[R]	10.000	1.717	3.025

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.255	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_9_s0/Q	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[17]	clk:[R]	clk:[R]	0.000	0.009	0.283
2	0.275	gw_gao_inst_0/u_la0_top/word_count_5_s0/Q	gw_gao_inst_0/u_la0_top/word_count_5_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
3	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
4	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
5	0.275	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
6	0.275	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
7	0.275	gw_gao_inst_0/u_la0_top/word_count_13_s0/Q	gw_gao_inst_0/u_la0_top/word_count_13_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
8	0.278	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q	gw_gao_inst_0/u_la0_top/word_count_0_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.303
9	0.278	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.303
10	0.278	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.303
11	0.278	FP_Sqrt/FP_Sqrt_inst/ce_delay_9_s0/Q	FP_Sqrt/FP_Sqrt_inst/ce_delay_10_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.225
12	0.281	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.306
13	0.281	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.306
14	0.281	gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_4_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.306
15	0.287	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.312
16	0.297	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_11_s0/Q	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[19]	clk:[R]	clk:[R]	0.000	0.014	0.318
17	0.299	FP_Sqrt/FP_Sqrt_inst/sign_adelay_0_s0/Q	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[31]	clk:[R]	clk:[R]	0.000	0.001	0.333
18	0.299	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_17_s0/Q	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[25]	clk:[R]	clk:[R]	0.000	0.001	0.333
19	0.299	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_16_s0/Q	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[24]	clk:[R]	clk:[R]	0.000	0.001	0.333
20	0.303	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_21_s0/Q	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[29]	clk:[R]	clk:[R]	0.000	0.005	0.333
21	0.328	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_20_s0/Q	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[28]	clk:[R]	clk:[R]	0.000	0.005	0.358
22	0.328	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.353
23	0.328	gw_gao_inst_0/u_la0_top/word_count_4_s0/Q	gw_gao_inst_0/u_la0_top/word_count_4_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.353
24	0.328	gw_gao_inst_0/u_la0_top/word_count_11_s0/Q	gw_gao_inst_0/u_la0_top/word_count_11_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.353
25	0.331	gw_gao_inst_0/u_la0_top/bit_count_2_s1/Q	gw_gao_inst_0/u_la0_top/bit_count_2_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.356

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.953	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.002	3.697
2	5.953	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.002	3.697
3	5.953	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.002	3.697
4	6.173	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.001	3.479
5	6.356	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.001	3.296
6	6.356	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.001	3.296
7	6.356	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.001	3.296
8	6.356	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.001	3.296
9	6.564	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.002	3.086
10	6.564	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.002	3.086
11	6.863	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.020	2.810
12	6.863	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.020	2.810
13	7.389	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	10.000	-0.001	2.265
14	7.389	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	10.000	-0.001	2.265
15	7.391	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	10.000	0.014	2.247
16	7.391	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	10.000	0.014	2.247
17	7.391	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	10.000	0.014	2.247
18	7.398	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	10.000	-0.011	2.265
19	7.398	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.011	2.265
20	7.398	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	10.000	-0.011	2.265
21	7.411	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.011	2.253
22	7.411	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.011	2.253
23	7.411	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.011	2.253
24	7.411	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.011	2.253
25	7.411	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.011	2.253

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	10.617	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.003	0.567
2	10.617	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.003	0.567
3	10.617	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-10.000	-0.003	0.567
4	10.768	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	-0.017	0.732
5	10.820	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.007	0.761
6	10.829	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.001	0.775
7	10.868	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.025	0.840
8	10.868	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.025	0.840
9	10.868	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.025	0.840
10	10.868	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.025	0.840
11	10.868	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.025	0.840
12	10.870	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	-0.025	0.842
13	10.870	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	-0.025	0.842
14	10.874	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.021	0.842
15	10.874	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.021	0.842
16	10.874	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.021	0.842
17	10.906	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.002	0.855
18	10.906	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.002	0.855
19	10.906	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.002	0.855
20	10.910	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	-10.000	0.002	0.855
21	10.910	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.002	0.855
22	10.970	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-10.000	-0.021	0.938
23	10.970	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.021	0.938
24	11.018	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.006	0.971
25	11.018	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	-10.000	-0.006	0.971

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	7.751	8.751	1.000	Low Pulse Width	clk	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s
2	7.751	8.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
3	7.753	8.753	1.000	Low Pulse Width	clk	mem_data_1_mem_data_1_0_0_s
4	7.757	8.757	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
5	7.757	8.757	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
6	7.757	8.757	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
7	7.757	8.757	1.000	Low Pulse Width	clk	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s
8	7.762	8.762	1.000	High Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
9	7.762	8.762	1.000	High Pulse Width	clk	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s
10	7.762	8.762	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.423
Data Arrival Time	59.862
Data Required Time	62.284
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
58.257	0.461	tINS	RR	10	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
58.422	0.165	tNET	RR	1	R33C57[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
58.943	0.521	tINS	RR	1	R33C57[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
59.862	0.919	tNET	RR	1	R27C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.631	1.948	tNET	RR	1	R27C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
62.596	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
62.284	-0.311	tSu		1	R27C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-1.729
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.734, 31.508%; route: 3.386, 61.540%; tC2Q: 0.382, 6.951%
Required Clock Path Delay	cell: 0.683, 25.944%; route: 1.948, 74.056%

Path2

Path Summary:

Slack	2.824
Data Arrival Time	59.695
Data Required Time	62.519
From	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.325	2.960	tNET	RR	1	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/CLK
54.708	0.382	tC2Q	RR	5	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q
56.772	2.065	tNET	RR	1	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/I1
57.299	0.526	tINS	RR	8	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/F
57.651	0.352	tNET	RR	1	R34C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I2
58.149	0.498	tINS	RR	4	R34C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F
58.645	0.496	tNET	RR	1	R33C53[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/I3
59.166	0.521	tINS	RR	1	R33C53[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/F
59.169	0.003	tNET	RR	1	R33C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I2
59.695	0.526	tINS	RR	1	R33C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F
59.695	0.000	tNET	RR	1	R33C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.618	1.935	tNET	RR	1	R33C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK
62.583	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
62.519	-0.064	tSu		1	R33C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0

Path Statistics:

Clock Skew	-1.707
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.561%; route: 2.960, 68.439%
Arrival Data Path Delay	cell: 2.071, 38.571%; route: 2.916, 54.306%; tC2Q: 0.382, 7.123%
Required Clock Path Delay	cell: 0.683, 26.074%; route: 1.935, 73.925%

Path3

Path Summary:

Slack	2.861
Data Arrival Time	59.661
Data Required Time	62.522
From	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.325	2.960	tNET	RR	1	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/CLK
54.708	0.382	tC2Q	RR	5	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q
56.772	2.065	tNET	RR	1	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/I1
57.299	0.526	tINS	RR	8	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/F
57.651	0.352	tNET	RR	1	R34C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I2
58.149	0.498	tINS	RR	4	R34C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F
58.783	0.634	tNET	RR	1	R35C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s10/I1
59.198	0.415	tINS	RR	1	R35C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s10/F
59.200	0.003	tNET	RR	1	R35C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/I1
59.661	0.461	tINS	RR	1	R35C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/F
59.661	0.000	tNET	RR	1	R35C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.621	1.939	tNET	RR	1	R35C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/CLK
62.586	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0
62.522	-0.064	tSu		1	R35C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0

Path Statistics:

Clock Skew	-1.704
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.561%; route: 2.960, 68.439%
Arrival Data Path Delay	cell: 1.900, 35.606%; route: 3.054, 57.227%; tC2Q: 0.382, 7.168%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path4

Path Summary:

Slack	3.149
Data Arrival Time	59.374
Data Required Time	62.522
From	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.325	2.960	tNET	RR	1	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/CLK
54.708	0.382	tC2Q	RR	5	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q
56.772	2.065	tNET	RR	1	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/I1
57.299	0.526	tINS	RR	8	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/F
57.651	0.352	tNET	RR	1	R34C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I2
58.149	0.498	tINS	RR	4	R34C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F
58.647	0.499	tNET	RR	1	R35C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s10/I3
59.109	0.461	tINS	RR	1	R35C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s10/F
59.111	0.003	tNET	RR	1	R35C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/I2
59.374	0.262	tINS	RR	1	R35C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/F
59.374	0.000	tNET	RR	1	R35C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.621	1.939	tNET	RR	1	R35C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/CLK
62.586	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
62.522	-0.064	tSu		1	R35C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0

Path Statistics:

Clock Skew	-1.704
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.561%; route: 2.960, 68.439%
Arrival Data Path Delay	cell: 1.747, 34.613%; route: 2.919, 57.811%; tC2Q: 0.382, 7.576%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path5

Path Summary:

Slack	3.197
Data Arrival Time	59.314
Data Required Time	62.511
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
58.257	0.461	tINS	RR	10	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
58.788	0.531	tNET	RR	1	R34C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n579_s1/I3
59.314	0.526	tINS	RR	1	R34C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n579_s1/F
59.314	0.000	tNET	RR	1	R34C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.610	1.928	tNET	RR	1	R34C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
62.575	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
62.511	-0.064	tSu		1	R34C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-1.749
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.739, 35.091%; route: 2.834, 57.190%; tC2Q: 0.382, 7.719%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path6

Path Summary:

Slack	3.350
Data Arrival Time	59.174
Data Required Time	62.524
From	gw_gao_inst_0/u_la0_top/capture_windows_num_2_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.331	2.966	tNET	RR	1	R16C56[0][B]	gw_gao_inst_0/u_la0_top/capture_windows_num_2_s0/CLK
54.713	0.382	tC2Q	RR	5	R16C56[0][B]	gw_gao_inst_0/u_la0_top/capture_windows_num_2_s0/Q
55.734	1.021	tNET	RR	2	R20C58[1][A]	gw_gao_inst_0/u_la0_top/n2910_s22/I0
56.291	0.556	tINS	RF	1	R20C58[1][A]	gw_gao_inst_0/u_la0_top/n2910_s22/COUT
56.291	0.000	tNET	FF	2	R20C58[1][B]	gw_gao_inst_0/u_la0_top/n2910_s23/CIN
56.341	0.050	tINS	FR	1	R20C58[1][B]	gw_gao_inst_0/u_la0_top/n2910_s23/COUT
56.341	0.000	tNET	RR	2	R20C58[2][A]	gw_gao_inst_0/u_la0_top/n2910_s24/CIN
56.391	0.050	tINS	RR	1	R20C58[2][A]	gw_gao_inst_0/u_la0_top/n2910_s24/COUT
56.391	0.000	tNET	RR	2	R20C58[2][B]	gw_gao_inst_0/u_la0_top/n2910_s25/CIN
56.441	0.050	tINS	RR	1	R20C58[2][B]	gw_gao_inst_0/u_la0_top/n2910_s25/COUT
56.441	0.000	tNET	RR	2	R20C59[0][A]	gw_gao_inst_0/u_la0_top/n2910_s26/CIN
56.491	0.050	tINS	RR	1	R20C59[0][A]	gw_gao_inst_0/u_la0_top/n2910_s26/COUT
56.491	0.000	tNET	RR	2	R20C59[0][B]	gw_gao_inst_0/u_la0_top/n2910_s27/CIN
56.541	0.050	tINS	RR	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/n2910_s27/COUT
56.541	0.000	tNET	RR	2	R20C59[1][A]	gw_gao_inst_0/u_la0_top/n2910_s28/CIN
56.591	0.050	tINS	RR	2	R20C59[1][A]	gw_gao_inst_0/u_la0_top/n2910_s28/COUT
57.724	1.134	tNET	RR	1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/start_reg1_s1/I2
58.251	0.526	tINS	RR	1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/start_reg1_s1/F
58.658	0.407	tNET	RR	1	R18C53[1][A]	gw_gao_inst_0/u_la0_top/start_reg1_s0/I1
59.174	0.516	tINS	RR	1	R18C53[1][A]	gw_gao_inst_0/u_la0_top/start_reg1_s0/F
59.174	0.000	tNET	RR	1	R18C53[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.623	1.941	tNET	RR	1	R18C53[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
62.588	-0.035	tUnc				gw_gao_inst_0/u_la0_top/start_reg_s0
62.524	-0.064	tSu		1	R18C53[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-1.707
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.520%; route: 2.966, 68.480%
Arrival Data Path Delay	cell: 1.899, 39.200%; route: 2.563, 52.903%; tC2Q: 0.382, 7.897%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path7

Path Summary:

Slack	3.423
Data Arrival Time	59.097
Data Required Time	62.521
From	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.325	2.960	tNET	RR	1	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/CLK
54.708	0.382	tC2Q	RR	5	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q
56.772	2.065	tNET	RR	1	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/I1
57.299	0.526	tINS	RR	8	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/F
57.651	0.352	tNET	RR	1	R34C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I2
58.149	0.498	tINS	RR	4	R34C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F
58.154	0.005	tNET	RR	1	R34C57[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s8/I2
58.569	0.415	tINS	RR	1	R34C57[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s8/F
58.571	0.003	tNET	RR	1	R34C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s7/I2
59.097	0.526	tINS	RR	1	R34C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s7/F
59.097	0.000	tNET	RR	1	R34C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.619	1.937	tNET	RR	1	R34C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/CLK
62.584	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0
62.521	-0.064	tSu		1	R34C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0

Path Statistics:

Clock Skew	-1.706
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.561%; route: 2.960, 68.439%
Arrival Data Path Delay	cell: 1.965, 41.173%; route: 2.425, 50.812%; tC2Q: 0.382, 8.015%
Required Clock Path Delay	cell: 0.683, 26.056%; route: 1.937, 73.944%

Path8

Path Summary:

Slack	3.506
Data Arrival Time	59.003
Data Required Time	62.509
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
58.257	0.461	tINS	RR	10	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
58.487	0.230	tNET	RR	1	R33C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n577_s1/I3
59.003	0.516	tINS	RR	1	R33C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n577_s1/F
59.003	0.000	tNET	RR	1	R33C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.608	1.926	tNET	RR	1	R33C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
62.573	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
62.509	-0.064	tSu		1	R33C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-1.751
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.729, 37.227%; route: 2.533, 54.536%; tC2Q: 0.382, 8.237%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path9

Path Summary:

Slack	3.506
Data Arrival Time	59.003
Data Required Time	62.509
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
58.257	0.461	tINS	RR	10	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
58.487	0.230	tNET	RR	1	R33C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n576_s1/I2
59.003	0.516	tINS	RR	1	R33C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n576_s1/F
59.003	0.000	tNET	RR	1	R33C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.608	1.926	tNET	RR	1	R33C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
62.573	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
62.509	-0.064	tSu		1	R33C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-1.751
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.729, 37.227%; route: 2.533, 54.536%; tC2Q: 0.382, 8.237%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path10

Path Summary:

Slack	3.506
Data Arrival Time	59.003
Data Required Time	62.509
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
58.257	0.461	tINS	RR	10	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
58.487	0.230	tNET	RR	1	R33C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s2/I2
59.003	0.516	tINS	RR	1	R33C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s2/F
59.003	0.000	tNET	RR	1	R33C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.608	1.926	tNET	RR	1	R33C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
62.573	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
62.509	-0.064	tSu		1	R33C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-1.751
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.729, 37.227%; route: 2.533, 54.536%; tC2Q: 0.382, 8.237%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path11

Path Summary:

Slack	3.547
Data Arrival Time	58.964
Data Required Time	62.511
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
58.257	0.461	tINS	RR	10	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
58.438	0.181	tNET	RR	1	R34C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n583_s1/I2
58.964	0.526	tINS	RR	1	R34C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n583_s1/F
58.964	0.000	tNET	RR	1	R34C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.610	1.928	tNET	RR	1	R34C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
62.575	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
62.511	-0.064	tSu		1	R34C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-1.749
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.739, 37.758%; route: 2.484, 53.936%; tC2Q: 0.382, 8.306%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path12

Path Summary:

Slack	3.576
Data Arrival Time	58.936
Data Required Time	62.511
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
58.257	0.461	tINS	RR	10	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
58.438	0.181	tNET	RR	1	R34C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n580_s1/I3
58.936	0.498	tINS	RR	1	R34C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n580_s1/F
58.936	0.000	tNET	RR	1	R34C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.610	1.928	tNET	RR	1	R34C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
62.575	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
62.511	-0.064	tSu		1	R34C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-1.749
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.710, 37.367%; route: 2.484, 54.275%; tC2Q: 0.382, 8.358%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path13

Path Summary:

Slack	3.589
Data Arrival Time	58.677
Data Required Time	62.266
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.312	2.947	tNET	RR	1	R16C58[0][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/CLK
54.694	0.382	tC2Q	RR	2	R16C58[0][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q
56.176	1.481	tNET	RR	1	R22C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s11/I2
56.702	0.526	tINS	RR	1	R22C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s11/F
57.274	0.572	tNET	RR	1	R27C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I3
57.537	0.262	tINS	RR	3	R27C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
57.542	0.005	tNET	RR	1	R27C55[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/I0
58.039	0.498	tINS	RR	1	R27C55[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/F
58.042	0.003	tNET	RR	1	R27C55[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2
58.539	0.498	tINS	RR	1	R27C55[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
58.677	0.137	tNET	RR	1	R27C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.612	1.929	tNET	RR	1	R27C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
62.577	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
62.266	-0.311	tSu		1	R27C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-1.700
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.657%; route: 2.947, 68.343%
Arrival Data Path Delay	cell: 1.784, 40.865%; route: 2.199, 50.372%; tC2Q: 0.382, 8.763%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path14

Path Summary:

Slack	3.612
Data Arrival Time	58.899
Data Required Time	62.511
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
58.257	0.461	tINS	RR	10	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
58.438	0.181	tNET	RR	1	R34C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n582_s1/I3
58.899	0.461	tINS	RR	1	R34C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n582_s1/F
58.899	0.000	tNET	RR	1	R34C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.610	1.928	tNET	RR	1	R34C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
62.575	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
62.511	-0.064	tSu		1	R34C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-1.749
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.674, 36.867%; route: 2.484, 54.708%; tC2Q: 0.382, 8.425%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path15

Path Summary:

Slack	3.612
Data Arrival Time	58.899
Data Required Time	62.511
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
58.257	0.461	tINS	RR	10	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
58.438	0.181	tNET	RR	1	R34C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n578_s1/I2
58.899	0.461	tINS	RR	1	R34C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n578_s1/F
58.899	0.000	tNET	RR	1	R34C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.610	1.928	tNET	RR	1	R34C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
62.575	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
62.511	-0.064	tSu		1	R34C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-1.749
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.674, 36.867%; route: 2.484, 54.708%; tC2Q: 0.382, 8.425%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path16

Path Summary:

Slack	3.726
Data Arrival Time	58.783
Data Required Time	62.509
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
58.257	0.461	tINS	RR	10	R33C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
58.267	0.010	tNET	RR	1	R33C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n581_s1/I2
58.783	0.516	tINS	RR	1	R33C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n581_s1/F
58.783	0.000	tNET	RR	1	R33C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.608	1.926	tNET	RR	1	R33C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
62.573	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
62.509	-0.064	tSu		1	R33C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-1.751
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.729, 39.079%; route: 2.313, 52.275%; tC2Q: 0.382, 8.647%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path17

Path Summary:

Slack	3.983
Data Arrival Time	58.537
Data Required Time	62.521
From	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_5_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.325	2.960	tNET	RR	1	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/CLK
54.708	0.382	tC2Q	RR	5	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q
56.772	2.065	tNET	RR	1	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/I1
57.299	0.526	tINS	RR	8	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/F
58.011	0.712	tNET	RR	1	R34C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s6/I1
58.537	0.526	tINS	RR	1	R34C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s6/F
58.537	0.000	tNET	RR	1	R34C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.619	1.937	tNET	RR	1	R34C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_5_s0/CLK
62.584	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_5_s0
62.521	-0.064	tSu		1	R34C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_5_s0

Path Statistics:

Clock Skew	-1.706
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 1.365, 31.561%; route: 2.960, 68.439%
Arrival Data Path Delay	cell: 1.053, 24.985%; route: 2.778, 65.935%; tC2Q: 0.382, 9.080%
Required Clock Path Delay	cell: 0.683, 26.056%; route: 1.937, 73.944%

Path18

Path Summary:

Slack	4.128
Data Arrival Time	58.393
Data Required Time	62.521
From	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.325	2.960	tNET	RR	1	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/CLK
54.708	0.382	tC2Q	RR	5	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q
56.772	2.065	tNET	RR	1	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/I1
57.299	0.526	tINS	RR	8	R33C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_5_s8/F
57.876	0.577	tNET	RR	1	R34C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_4_s5/I1
58.393	0.516	tINS	RR	1	R34C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_4_s5/F
58.393	0.000	tNET	RR	1	R34C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.619	1.937	tNET	RR	1	R34C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0/CLK
62.584	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0
62.521	-0.064	tSu		1	R34C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0

Path Statistics:

Clock Skew	-1.706
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 1.365, 31.561%; route: 2.960, 68.439%
Arrival Data Path Delay	cell: 1.043, 25.630%; route: 2.642, 64.966%; tC2Q: 0.382, 9.404%
Required Clock Path Delay	cell: 0.683, 26.056%; route: 1.937, 73.944%

Path19

Path Summary:

Slack	4.149
Data Arrival Time	58.127
Data Required Time	62.277
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.321	2.956	tNET	RR	1	R16C57[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
54.704	0.382	tC2Q	RR	2	R16C57[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
55.089	0.385	tNET	RR	2	R17C58[0][A]	gw_gao_inst_0/u_la0_top/n2936_s0/I1
55.651	0.563	tINS	RF	1	R17C58[0][A]	gw_gao_inst_0/u_la0_top/n2936_s0/COUT
55.651	0.000	tNET	FF	2	R17C58[0][B]	gw_gao_inst_0/u_la0_top/n2937_s0/CIN
55.701	0.050	tINS	FR	1	R17C58[0][B]	gw_gao_inst_0/u_la0_top/n2937_s0/COUT
55.701	0.000	tNET	RR	2	R17C58[1][A]	gw_gao_inst_0/u_la0_top/n2938_s0/CIN
55.751	0.050	tINS	RR	1	R17C58[1][A]	gw_gao_inst_0/u_la0_top/n2938_s0/COUT
55.751	0.000	tNET	RR	2	R17C58[1][B]	gw_gao_inst_0/u_la0_top/n2939_s0/CIN
55.801	0.050	tINS	RR	6	R17C58[1][B]	gw_gao_inst_0/u_la0_top/n2939_s0/COUT
56.945	1.144	tNET	RR	1	R18C53[1][B]	gw_gao_inst_0/u_la0_top/n2980_s1/I0
57.471	0.526	tINS	RR	1	R18C53[1][B]	gw_gao_inst_0/u_la0_top/n2980_s1/F
57.474	0.003	tNET	RR	1	R18C53[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
57.990	0.516	tINS	RR	1	R18C53[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
58.128	0.137	tNET	RR	1	R18C53[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.623	1.941	tNET	RR	1	R18C53[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
62.588	-0.035	tUnc				gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
62.277	-0.311	tSu		1	R18C53[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-1.698
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.588%; route: 2.956, 68.412%
Arrival Data Path Delay	cell: 1.755, 46.108%; route: 1.669, 43.842%; tC2Q: 0.382, 10.049%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path20

Path Summary:

Slack	4.176
Data Arrival Time	58.099
Data Required Time	62.275
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.312	2.947	tNET	RR	1	R16C58[0][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/CLK
54.694	0.382	tC2Q	RR	2	R16C58[0][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q
56.176	1.481	tNET	RR	1	R22C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s11/I2
56.702	0.526	tINS	RR	1	R22C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s11/F
57.274	0.572	tNET	RR	1	R27C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I3
57.537	0.262	tINS	RR	3	R27C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
57.699	0.162	tNET	RR	1	R27C54[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/I1
57.962	0.262	tINS	RR	1	R27C54[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/F
58.099	0.137	tNET	RR	1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.621	1.939	tNET	RR	1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
62.586	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
62.275	-0.311	tSu		1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-1.691
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 31.657%; route: 2.947, 68.343%
Arrival Data Path Delay	cell: 1.051, 27.756%; route: 2.354, 62.145%; tC2Q: 0.382, 10.099%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path21

Path Summary:

Slack	4.252
Data Arrival Time	58.257
Data Required Time	62.509
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.359	2.994	tNET	RR	1	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
54.742	0.382	tC2Q	RR	2	R20C55[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
56.309	1.567	tNET	RR	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
56.599	0.290	tINS	RF	1	R26C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
56.604	0.005	tNET	FF	1	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
57.066	0.461	tINS	FR	2	R26C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
57.796	0.730	tNET	RR	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n584_s2/I2
58.257	0.461	tINS	RR	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n584_s2/F
58.257	0.000	tNET	RR	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.608	1.926	tNET	RR	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
62.573	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
62.509	-0.064	tSu		1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-1.751
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 31.312%; route: 2.994, 68.688%
Arrival Data Path Delay	cell: 1.212, 31.110%; route: 2.303, 59.076%; tC2Q: 0.382, 9.814%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path22

Path Summary:

Slack	4.561
Data Arrival Time	57.962
Data Required Time	62.522
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.312	2.947	tNET	RR	1	R16C58[0][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/CLK
54.694	0.382	tC2Q	RR	2	R16C58[0][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q
56.176	1.481	tNET	RR	1	R22C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s11/I2
56.702	0.526	tINS	RR	1	R22C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s11/F
57.274	0.572	tNET	RR	1	R27C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I3
57.537	0.262	tINS	RR	3	R27C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
57.699	0.162	tNET	RR	1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s3/I1
57.962	0.262	tINS	RR	1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s3/F
57.962	0.000	tNET	RR	1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.621	1.939	tNET	RR	1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
62.586	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
62.522	-0.064	tSu		1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-1.691
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 31.657%; route: 2.947, 68.343%
Arrival Data Path Delay	cell: 1.051, 28.801%; route: 2.216, 60.719%; tC2Q: 0.382, 10.479%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path23

Path Summary:

Slack	4.734
Data Arrival Time	57.790
Data Required Time	62.524
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.321	2.956	tNET	RR	1	R16C57[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
54.704	0.382	tC2Q	RR	2	R16C57[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
55.089	0.385	tNET	RR	2	R17C58[0][A]	gw_gao_inst_0/u_la0_top/n2936_s0/I1
55.651	0.563	tINS	RF	1	R17C58[0][A]	gw_gao_inst_0/u_la0_top/n2936_s0/COUT
55.651	0.000	tNET	FF	2	R17C58[0][B]	gw_gao_inst_0/u_la0_top/n2937_s0/CIN
55.701	0.050	tINS	FR	1	R17C58[0][B]	gw_gao_inst_0/u_la0_top/n2937_s0/COUT
55.701	0.000	tNET	RR	2	R17C58[1][A]	gw_gao_inst_0/u_la0_top/n2938_s0/CIN
55.751	0.050	tINS	RR	1	R17C58[1][A]	gw_gao_inst_0/u_la0_top/n2938_s0/COUT
55.751	0.000	tNET	RR	2	R17C58[1][B]	gw_gao_inst_0/u_la0_top/n2939_s0/CIN
55.801	0.050	tINS	RR	6	R17C58[1][B]	gw_gao_inst_0/u_la0_top/n2939_s0/COUT
56.810	1.009	tNET	RR	1	R18C53[0][B]	gw_gao_inst_0/u_la0_top/n2960_s2/I1
57.271	0.461	tINS	RR	1	R18C53[0][B]	gw_gao_inst_0/u_la0_top/n2960_s2/F
57.274	0.003	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/n2959_s1/I3
57.790	0.516	tINS	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/n2959_s1/F
57.790	0.000	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.623	1.941	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
62.588	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
62.524	-0.064	tSu		1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-1.698
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 31.588%; route: 2.956, 68.412%
Arrival Data Path Delay	cell: 1.690, 48.721%; route: 1.396, 40.252%; tC2Q: 0.382, 11.027%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path24

Path Summary:

Slack	4.839
Data Arrival Time	57.661
Data Required Time	62.500
From	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.325	2.960	tNET	RR	1	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/CLK
54.708	0.382	tC2Q	RR	5	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q
56.557	1.850	tNET	RR	1	R33C54[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_2_s1/I2
56.972	0.415	tINS	RR	8	R33C54[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_2_s1/F
57.135	0.162	tNET	RR	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_3_s5/I2
57.661	0.526	tINS	RR	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_3_s5/F
57.661	0.000	tNET	RR	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.599	1.916	tNET	RR	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0/CLK
62.564	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0
62.500	-0.064	tSu		1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0

Path Statistics:

Clock Skew	-1.726
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 1.365, 31.561%; route: 2.960, 68.439%
Arrival Data Path Delay	cell: 0.941, 28.213%; route: 2.013, 60.322%; tC2Q: 0.382, 11.465%
Required Clock Path Delay	cell: 0.683, 26.263%; route: 1.916, 73.737%

Path25

Path Summary:

Slack	4.851
Data Arrival Time	57.350
Data Required Time	62.201
From	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_2_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
54.325	2.960	tNET	RR	1	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/CLK
54.708	0.382	tC2Q	RR	5	R18C55[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q
56.557	1.850	tNET	RR	1	R33C54[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_2_s1/I2
56.972	0.415	tINS	RR	8	R33C54[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_2_s1/F
57.350	0.377	tNET	RR	1	R33C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
60.682	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
62.608	1.926	tNET	RR	1	R33C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_2_s0/CLK
62.573	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_2_s0
62.201	-0.373	tSu		1	R33C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_2_s0

Path Statistics:

Clock Skew	-1.717
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.365, 31.561%; route: 2.960, 68.439%
Arrival Data Path Delay	cell: 0.415, 13.719%; route: 2.227, 73.636%; tC2Q: 0.382, 12.645%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.255
Data Arrival Time	1.667
Data Required Time	1.411
From	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_9_s0
To	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.384	0.708	tNET	RR	1	R27C21[3][A]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_9_s0/CLK
1.528	0.144	tC2Q	RR	1	R27C21[3][A]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_9_s0/Q
1.667	0.139	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.825%; route: 0.708, 51.175%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.139, 49.117%; tC2Q: 0.144, 50.883%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path2

Path Summary:

Slack	0.275
Data Arrival Time	2.829
Data Required Time	2.554
From	gw_gao_inst_0/u_la0_top/word_count_5_s0
To	gw_gao_inst_0/u_la0_top/word_count_5_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.529	1.178	tNET	RR	1	R8C56[0][A]	gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK
2.670	0.141	tC2Q	RF	4	R8C56[0][A]	gw_gao_inst_0/u_la0_top/word_count_5_s0/Q
2.676	0.006	tNET	FF	1	R8C56[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_5_s0/I1
2.829	0.153	tINS	FF	1	R8C56[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_5_s0/F
2.829	0.000	tNET	FF	1	R8C56[0][A]	gw_gao_inst_0/u_la0_top/word_count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.529	1.178	tNET	RR	1	R8C56[0][A]	gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK
2.554	0.025	tHld		1	R8C56[0][A]	gw_gao_inst_0/u_la0_top/word_count_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 53.420%; route: 1.178, 46.580%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 53.420%; route: 1.178, 46.580%

Path3

Path Summary:

Slack	0.275
Data Arrival Time	1.676
Data Required Time	1.400
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
1.516	0.141	tC2Q	RF	3	R27C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q
1.523	0.006	tNET	FF	1	R27C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n486_s0/I1
1.676	0.153	tINS	FF	1	R27C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n486_s0/F
1.676	0.000	tNET	FF	1	R27C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
1.400	0.025	tHld		1	R27C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%

Path4

Path Summary:

Slack	0.275
Data Arrival Time	1.679
Data Required Time	1.404
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
1.520	0.141	tC2Q	RF	4	R27C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/Q
1.526	0.006	tNET	FF	1	R27C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n484_s0/I1
1.679	0.153	tINS	FF	1	R27C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n484_s0/F
1.679	0.000	tNET	FF	1	R27C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
1.404	0.025	tHld		1	R27C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%

Path5

Path Summary:

Slack	0.275
Data Arrival Time	1.698
Data Required Time	1.423
From	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.539	0.141	tC2Q	RF	3	R20C56[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q
1.545	0.006	tNET	FF	1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/n2999_s1/I2
1.698	0.153	tINS	FF	1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/n2999_s1/F
1.698	0.000	tNET	FF	1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.423	0.025	tHld		1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path6

Path Summary:

Slack	0.275
Data Arrival Time	1.680
Data Required Time	1.405
From	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.380	0.705	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
1.521	0.141	tC2Q	RF	4	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/Q
1.527	0.006	tNET	FF	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/n2959_s1/I2
1.680	0.153	tINS	FF	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/n2959_s1/F
1.680	0.000	tNET	FF	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.380	0.705	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
1.405	0.025	tHld		1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.940%; route: 0.705, 51.060%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 48.940%; route: 0.705, 51.060%

Path7

Path Summary:

Slack	0.275
Data Arrival Time	2.825
Data Required Time	2.550
From	gw_gao_inst_0/u_la0_top/word_count_13_s0
To	gw_gao_inst_0/u_la0_top/word_count_13_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.525	1.174	tNET	RR	1	R8C55[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
2.666	0.141	tC2Q	RF	5	R8C55[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/Q
2.672	0.006	tNET	FF	1	R8C55[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/I1
2.825	0.153	tINS	FF	1	R8C55[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/F
2.825	0.000	tNET	FF	1	R8C55[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.525	1.174	tNET	RR	1	R8C55[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
2.550	0.025	tHld		1	R8C55[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 53.505%; route: 1.174, 46.495%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 53.505%; route: 1.174, 46.495%

Path8

Path Summary:

Slack	0.278
Data Arrival Time	2.836
Data Required Time	2.558
From	gw_gao_inst_0/u_la0_top/word_count_0_s0
To	gw_gao_inst_0/u_la0_top/word_count_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.533	1.182	tNET	RR	1	R3C58[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.674	0.141	tC2Q	RF	5	R3C58[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q
2.683	0.009	tNET	FF	1	R3C58[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/I1
2.836	0.153	tINS	FF	1	R3C58[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/F
2.836	0.000	tNET	FF	1	R3C58[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.533	1.182	tNET	RR	1	R3C58[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.558	0.025	tHld		1	R3C58[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 53.336%; route: 1.182, 46.664%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 53.336%; route: 1.182, 46.664%

Path9

Path Summary:

Slack	0.278
Data Arrival Time	1.701
Data Required Time	1.423
From	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.539	0.141	tC2Q	RF	5	R20C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q
1.548	0.009	tNET	FF	1	R20C54[0][A]	gw_gao_inst_0/u_la0_top/n3002_s1/I0
1.701	0.153	tINS	FF	1	R20C54[0][A]	gw_gao_inst_0/u_la0_top/n3002_s1/F
1.701	0.000	tNET	FF	1	R20C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.423	0.025	tHld		1	R20C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path10

Path Summary:

Slack	0.278
Data Arrival Time	1.674
Data Required Time	1.396
From	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.371	0.696	tNET	RR	1	R17C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.512	0.141	tC2Q	RF	5	R17C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/Q
1.521	0.009	tNET	FF	1	R17C55[0][A]	gw_gao_inst_0/u_la0_top/n2960_s3/I1
1.674	0.153	tINS	FF	1	R17C55[0][A]	gw_gao_inst_0/u_la0_top/n2960_s3/F
1.674	0.000	tNET	FF	1	R17C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.371	0.696	tNET	RR	1	R17C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.396	0.025	tHld		1	R17C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.271%; route: 0.696, 50.729%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 49.271%; route: 0.696, 50.729%

Path11

Path Summary:

Slack	0.278
Data Arrival Time	1.597
Data Required Time	1.319
From	FP_Sqrt/FP_Sqrt_inst/ce_delay_9_s0
To	FP_Sqrt/FP_Sqrt_inst/ce_delay_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R33C34[3][A]	FP_Sqrt/FP_Sqrt_inst/ce_delay_9_s0/CLK
1.516	0.144	tC2Q	RR	2	R33C34[3][A]	FP_Sqrt/FP_Sqrt_inst/ce_delay_9_s0/Q
1.597	0.081	tNET	RR	1	R33C34[2][A]	FP_Sqrt/FP_Sqrt_inst/ce_delay_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R33C34[2][A]	FP_Sqrt/FP_Sqrt_inst/ce_delay_10_s0/CLK
1.319	-0.053	tHld		1	R33C34[2][A]	FP_Sqrt/FP_Sqrt_inst/ce_delay_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.081, 36.000%; tC2Q: 0.144, 64.000%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path12

Path Summary:

Slack	0.281
Data Arrival Time	1.678
Data Required Time	1.397
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.513	0.141	tC2Q	RF	11	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
1.525	0.012	tNET	FF	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n584_s2/I0
1.678	0.153	tINS	FF	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n584_s2/F
1.678	0.000	tNET	FF	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.397	0.025	tHld		1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path13

Path Summary:

Slack	0.281
Data Arrival Time	1.704
Data Required Time	1.423
From	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.539	0.141	tC2Q	RF	5	R20C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/Q
1.551	0.012	tNET	FF	1	R20C56[0][A]	gw_gao_inst_0/u_la0_top/n3001_s1/I0
1.704	0.153	tINS	FF	1	R20C56[0][A]	gw_gao_inst_0/u_la0_top/n3001_s1/F
1.704	0.000	tNET	FF	1	R20C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.423	0.025	tHld		1	R20C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path14

Path Summary:

Slack	0.281
Data Arrival Time	2.807
Data Required Time	2.526
From	gw_gao_inst_0/u_la0_top/address_counter_4_s0
To	gw_gao_inst_0/u_la0_top/address_counter_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.501	1.150	tNET	RR	1	R12C55[0][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.642	0.141	tC2Q	RF	9	R12C55[0][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q
2.654	0.012	tNET	FF	1	R12C55[0][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/I1
2.807	0.153	tINS	FF	1	R12C55[0][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/F
2.807	0.000	tNET	FF	1	R12C55[0][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.501	1.150	tNET	RR	1	R12C55[0][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.526	0.025	tHld		1	R12C55[0][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 54.018%; route: 1.150, 45.982%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 1.351, 54.018%; route: 1.150, 45.982%

Path15

Path Summary:

Slack	0.287
Data Arrival Time	1.714
Data Required Time	1.427
From	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.546	0.144	tC2Q	RR	9	R20C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/Q
1.561	0.015	tNET	RR	1	R20C53[0][A]	gw_gao_inst_0/u_la0_top/n3004_s1/I0
1.714	0.153	tINS	RF	1	R20C53[0][A]	gw_gao_inst_0/u_la0_top/n3004_s1/F
1.714	0.000	tNET	FF	1	R20C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.427	0.025	tHld		1	R20C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.153, 49.038%; route: 0.015, 4.808%; tC2Q: 0.144, 46.154%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path16

Path Summary:

Slack	0.297
Data Arrival Time	1.707
Data Required Time	1.410
From	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_11_s0
To	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.388	0.713	tNET	RR	1	R26C21[0][A]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_11_s0/CLK
1.533	0.144	tC2Q	RR	1	R26C21[0][A]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_11_s0/Q
1.707	0.174	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[19]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKA
1.410	0.035	tHld		1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s

Path Statistics:

Clock Skew	-0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.650%; route: 0.713, 51.350%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path17

Path Summary:

Slack	0.299
Data Arrival Time	1.709
Data Required Time	1.410
From	FP_Sqrt/FP_Sqrt_inst/sign_adelay_0_s0
To	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C23[1][B]	FP_Sqrt/FP_Sqrt_inst/sign_adelay_0_s0/CLK
1.520	0.144	tC2Q	RR	1	R27C23[1][B]	FP_Sqrt/FP_Sqrt_inst/sign_adelay_0_s0/Q
1.709	0.189	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[31]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKA
1.410	0.035	tHld		1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path18

Path Summary:

Slack	0.299
Data Arrival Time	1.709
Data Required Time	1.410
From	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_17_s0
To	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C23[2][A]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_17_s0/CLK
1.520	0.144	tC2Q	RR	1	R27C23[2][A]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_17_s0/Q
1.709	0.189	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[25]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKA
1.410	0.035	tHld		1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path19

Path Summary:

Slack	0.299
Data Arrival Time	1.709
Data Required Time	1.410
From	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_16_s0
To	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C23[1][A]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_16_s0/CLK
1.520	0.144	tC2Q	RR	1	R27C23[1][A]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_16_s0/Q
1.709	0.189	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[24]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKA
1.410	0.035	tHld		1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path20

Path Summary:

Slack	0.303
Data Arrival Time	1.712
Data Required Time	1.410
From	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_21_s0
To	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C24[0][B]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_21_s0/CLK
1.523	0.144	tC2Q	RR	1	R27C24[0][B]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_21_s0/Q
1.712	0.189	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[29]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKA
1.410	0.035	tHld		1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path21

Path Summary:

Slack	0.328
Data Arrival Time	1.737
Data Required Time	1.410
From	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_20_s0
To	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C22[3][A]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_20_s0/CLK
1.523	0.144	tC2Q	RR	1	R27C22[3][A]	FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_20_s0/Q
1.737	0.214	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/DI[28]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKA
1.410	0.035	tHld		1	BSRAM_R28[5]	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.214, 59.777%; tC2Q: 0.144, 40.223%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path22

Path Summary:

Slack	0.328
Data Arrival Time	1.732
Data Required Time	1.404
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.520	0.141	tC2Q	RF	4	R27C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q
1.526	0.006	tNET	FF	1	R27C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n487_s0/I1
1.732	0.206	tINS	FF	1	R27C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n487_s0/F
1.732	0.000	tNET	FF	1	R27C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.404	0.025	tHld		1	R27C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.206, 58.357%; route: 0.006, 1.700%; tC2Q: 0.141, 39.943%
Required Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%

Path23

Path Summary:

Slack	0.328
Data Arrival Time	2.878
Data Required Time	2.550
From	gw_gao_inst_0/u_la0_top/word_count_4_s0
To	gw_gao_inst_0/u_la0_top/word_count_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.525	1.174	tNET	RR	1	R8C55[2][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.666	0.141	tC2Q	RF	5	R8C55[2][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0/Q
2.672	0.006	tNET	FF	1	R8C55[2][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/I1
2.878	0.206	tINS	FF	1	R8C55[2][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/F
2.878	0.000	tNET	FF	1	R8C55[2][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.525	1.174	tNET	RR	1	R8C55[2][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.550	0.025	tHld		1	R8C55[2][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 53.505%; route: 1.174, 46.495%
Arrival Data Path Delay	cell: 0.206, 58.357%; route: 0.006, 1.700%; tC2Q: 0.141, 39.943%
Required Clock Path Delay	cell: 1.351, 53.505%; route: 1.174, 46.495%

Path24

Path Summary:

Slack	0.328
Data Arrival Time	2.873
Data Required Time	2.545
From	gw_gao_inst_0/u_la0_top/word_count_11_s0
To	gw_gao_inst_0/u_la0_top/word_count_11_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.520	1.169	tNET	RR	1	R9C55[2][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK
2.661	0.141	tC2Q	RF	2	R9C55[2][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0/Q
2.667	0.006	tNET	FF	1	R9C55[2][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_11_s0/I1
2.873	0.206	tINS	FF	1	R9C55[2][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_11_s0/F
2.873	0.000	tNET	FF	1	R9C55[2][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.520	1.169	tNET	RR	1	R9C55[2][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK
2.545	0.025	tHld		1	R9C55[2][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 53.611%; route: 1.169, 46.389%
Arrival Data Path Delay	cell: 0.206, 58.357%; route: 0.006, 1.700%; tC2Q: 0.141, 39.943%
Required Clock Path Delay	cell: 1.351, 53.611%; route: 1.169, 46.389%

Path25

Path Summary:

Slack	0.331
Data Arrival Time	2.877
Data Required Time	2.546
From	gw_gao_inst_0/u_la0_top/bit_count_2_s1
To	gw_gao_inst_0/u_la0_top/bit_count_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.521	1.170	tNET	RR	1	R8C54[2][A]	gw_gao_inst_0/u_la0_top/bit_count_2_s1/CLK
2.662	0.141	tC2Q	RF	4	R8C54[2][A]	gw_gao_inst_0/u_la0_top/bit_count_2_s1/Q
2.671	0.009	tNET	FF	1	R8C54[2][A]	gw_gao_inst_0/u_la0_top/n729_s4/I0
2.877	0.206	tINS	FF	1	R8C54[2][A]	gw_gao_inst_0/u_la0_top/n729_s4/F
2.877	0.000	tNET	FF	1	R8C54[2][A]	gw_gao_inst_0/u_la0_top/bit_count_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	330	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.521	1.170	tNET	RR	1	R8C54[2][A]	gw_gao_inst_0/u_la0_top/bit_count_2_s1/CLK
2.546	0.025	tHld		1	R8C54[2][A]	gw_gao_inst_0/u_la0_top/bit_count_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 53.590%; route: 1.170, 46.410%
Arrival Data Path Delay	cell: 0.206, 57.865%; route: 0.009, 2.528%; tC2Q: 0.141, 39.607%
Required Clock Path Delay	cell: 1.351, 53.590%; route: 1.170, 46.410%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.953
Data Arrival Time	16.308
Data Required Time	22.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.308	3.255	tNET	FF	1	R33C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.608	1.926	tNET	RR	1	R33C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
22.261	-0.347	tSu		1	R33C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.255, 88.032%; tC2Q: 0.442, 11.968%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path2

Path Summary:

Slack	5.953
Data Arrival Time	16.308
Data Required Time	22.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.308	3.255	tNET	FF	1	R33C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.608	1.926	tNET	RR	1	R33C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
22.261	-0.347	tSu		1	R33C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.255, 88.032%; tC2Q: 0.442, 11.968%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path3

Path Summary:

Slack	5.953
Data Arrival Time	16.308
Data Required Time	22.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.308	3.255	tNET	FF	1	R33C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.608	1.926	tNET	RR	1	R33C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
22.261	-0.347	tSu		1	R33C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.255, 88.032%; tC2Q: 0.442, 11.968%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path4

Path Summary:

Slack	6.173
Data Arrival Time	16.089
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.089	3.036	tNET	FF	1	R34C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R34C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
22.263	-0.347	tSu		1	R34C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.036, 87.280%; tC2Q: 0.442, 12.720%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path5

Path Summary:

Slack	6.356
Data Arrival Time	15.907
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.907	2.854	tNET	FF	1	R34C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R34C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
22.263	-0.347	tSu		1	R34C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.854, 86.576%; tC2Q: 0.442, 13.424%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path6

Path Summary:

Slack	6.356
Data Arrival Time	15.907
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.907	2.854	tNET	FF	1	R34C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R34C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
22.263	-0.347	tSu		1	R34C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.854, 86.576%; tC2Q: 0.442, 13.424%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path7

Path Summary:

Slack	6.356
Data Arrival Time	15.907
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.907	2.854	tNET	FF	1	R34C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R34C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
22.263	-0.347	tSu		1	R34C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.854, 86.576%; tC2Q: 0.442, 13.424%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path8

Path Summary:

Slack	6.356
Data Arrival Time	15.907
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.907	2.854	tNET	FF	1	R34C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R34C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
22.263	-0.347	tSu		1	R34C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.854, 86.576%; tC2Q: 0.442, 13.424%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path9

Path Summary:

Slack	6.564
Data Arrival Time	15.697
Data Required Time	22.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.697	2.644	tNET	FF	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.608	1.926	tNET	RR	1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
22.261	-0.347	tSu		1	R33C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.644, 85.662%; tC2Q: 0.442, 14.338%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path10

Path Summary:

Slack	6.564
Data Arrival Time	15.697
Data Required Time	22.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.697	2.644	tNET	FF	1	R33C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.608	1.926	tNET	RR	1	R33C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
22.261	-0.347	tSu		1	R33C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.644, 85.662%; tC2Q: 0.442, 14.338%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path11

Path Summary:

Slack	6.863
Data Arrival Time	15.421
Data Required Time	22.283
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.421	2.368	tNET	FF	1	R27C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.631	1.948	tNET	RR	1	R27C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
22.283	-0.347	tSu		1	R27C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	0.020
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.368, 84.253%; tC2Q: 0.442, 15.747%
Required Clock Path Delay	cell: 0.683, 25.944%; route: 1.948, 74.056%

Path12

Path Summary:

Slack	6.863
Data Arrival Time	15.421
Data Required Time	22.283
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.421	2.368	tNET	FF	1	R27C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.631	1.948	tNET	RR	1	R27C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
22.283	-0.347	tSu		1	R27C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	0.020
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.368, 84.253%; tC2Q: 0.442, 15.747%
Required Clock Path Delay	cell: 0.683, 25.944%; route: 1.948, 74.056%

Path13

Path Summary:

Slack	7.389
Data Arrival Time	14.876
Data Required Time	22.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.876	1.823	tNET	FF	1	R17C56[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R17C56[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
22.264	-0.347	tSu		1	R17C56[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.823, 80.464%; tC2Q: 0.442, 19.536%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path14

Path Summary:

Slack	7.389
Data Arrival Time	14.876
Data Required Time	22.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.876	1.823	tNET	FF	1	R17C56[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R17C56[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
22.264	-0.347	tSu		1	R17C56[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.823, 80.464%; tC2Q: 0.442, 19.536%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path15

Path Summary:

Slack	7.391
Data Arrival Time	14.858
Data Required Time	22.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.858	1.805	tNET	FF	1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.596	1.914	tNET	RR	1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
22.249	-0.347	tSu		1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.805, 80.311%; tC2Q: 0.442, 19.689%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path16

Path Summary:

Slack	7.391
Data Arrival Time	14.858
Data Required Time	22.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.858	1.805	tNET	FF	1	R13C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.596	1.914	tNET	RR	1	R13C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
22.249	-0.347	tSu		1	R13C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.805, 80.311%; tC2Q: 0.442, 19.689%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path17

Path Summary:

Slack	7.391
Data Arrival Time	14.858
Data Required Time	22.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.858	1.805	tNET	FF	1	R13C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.596	1.914	tNET	RR	1	R13C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
22.249	-0.347	tSu		1	R13C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.805, 80.311%; tC2Q: 0.442, 19.689%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path18

Path Summary:

Slack	7.398
Data Arrival Time	14.876
Data Required Time	22.274
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.876	1.823	tNET	FF	1	R17C57[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.621	1.939	tNET	RR	1	R17C57[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
22.274	-0.347	tSu		1	R17C57[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.823, 80.464%; tC2Q: 0.442, 19.536%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path19

Path Summary:

Slack	7.398
Data Arrival Time	14.876
Data Required Time	22.274
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.876	1.823	tNET	FF	1	R17C57[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.621	1.939	tNET	RR	1	R17C57[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
22.274	-0.347	tSu		1	R17C57[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.823, 80.464%; tC2Q: 0.442, 19.536%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path20

Path Summary:

Slack	7.398
Data Arrival Time	14.876
Data Required Time	22.274
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.876	1.823	tNET	FF	1	R17C57[1][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.621	1.939	tNET	RR	1	R17C57[1][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
22.274	-0.347	tSu		1	R17C57[1][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.823, 80.464%; tC2Q: 0.442, 19.536%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path21

Path Summary:

Slack	7.411
Data Arrival Time	14.863
Data Required Time	22.274
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.863	1.810	tNET	FF	1	R27C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.621	1.939	tNET	RR	1	R27C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
22.274	-0.347	tSu		1	R27C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.810, 80.355%; tC2Q: 0.442, 19.645%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path22

Path Summary:

Slack	7.411
Data Arrival Time	14.863
Data Required Time	22.274
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.863	1.810	tNET	FF	1	R27C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.621	1.939	tNET	RR	1	R27C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
22.274	-0.347	tSu		1	R27C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.810, 80.355%; tC2Q: 0.442, 19.645%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path23

Path Summary:

Slack	7.411
Data Arrival Time	14.863
Data Required Time	22.274
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.863	1.810	tNET	FF	1	R27C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.621	1.939	tNET	RR	1	R27C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
22.274	-0.347	tSu		1	R27C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.810, 80.355%; tC2Q: 0.442, 19.645%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path24

Path Summary:

Slack	7.411
Data Arrival Time	14.863
Data Required Time	22.274
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.863	1.810	tNET	FF	1	R27C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.621	1.939	tNET	RR	1	R27C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
22.274	-0.347	tSu		1	R27C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.810, 80.355%; tC2Q: 0.442, 19.645%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path25

Path Summary:

Slack	7.411
Data Arrival Time	14.863
Data Required Time	22.274
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2017	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.863	1.810	tNET	FF	1	R27C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	2017	IOB29[A]	clk_ibuf/O
22.621	1.939	tNET	RR	1	R27C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
22.274	-0.347	tSu		1	R27C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.810, 80.355%; tC2Q: 0.442, 19.645%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	10.617
Data Arrival Time	11.944
Data Required Time	1.327
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.944	0.409	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.380	0.705	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
1.327	-0.053	tHld		1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.409, 72.134%; tC2Q: 0.158, 27.866%
Required Clock Path Delay	cell: 0.675, 48.940%; route: 0.705, 51.060%

Path2

Path Summary:

Slack	10.617
Data Arrival Time	11.944
Data Required Time	1.327
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.944	0.409	tNET	RR	1	R18C53[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.380	0.705	tNET	RR	1	R18C53[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
1.327	-0.053	tHld		1	R18C53[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.409, 72.134%; tC2Q: 0.158, 27.866%
Required Clock Path Delay	cell: 0.675, 48.940%; route: 0.705, 51.060%

Path3

Path Summary:

Slack	10.617
Data Arrival Time	11.944
Data Required Time	1.327
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.944	0.409	tNET	RR	1	R18C53[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.380	0.705	tNET	RR	1	R18C53[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
1.327	-0.053	tHld		1	R18C53[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.409, 72.134%; tC2Q: 0.158, 27.866%
Required Clock Path Delay	cell: 0.675, 48.940%; route: 0.705, 51.060%

Path4

Path Summary:

Slack	10.768
Data Arrival Time	12.109
Data Required Time	1.341
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.109	0.574	tNET	RR	1	R20C55[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.394	0.719	tNET	RR	1	R20C55[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
1.341	-0.053	tHld		1	R20C55[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	0.017
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.574, 78.415%; tC2Q: 0.158, 21.585%
Required Clock Path Delay	cell: 0.675, 48.449%; route: 0.719, 51.551%

Path5

Path Summary:

Slack	10.820
Data Arrival Time	12.139
Data Required Time	1.318
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.138	0.603	tNET	RR	1	R17C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.371	0.696	tNET	RR	1	R17C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.318	-0.053	tHld		1	R17C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.007
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 79.238%; tC2Q: 0.158, 20.762%
Required Clock Path Delay	cell: 0.675, 49.271%; route: 0.696, 50.729%

Path6

Path Summary:

Slack	10.829
Data Arrival Time	12.152
Data Required Time	1.323
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.152	0.617	tNET	RR	1	R18C56[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.376	0.701	tNET	RR	1	R18C56[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
1.323	-0.053	tHld		1	R18C56[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.617, 79.613%; tC2Q: 0.158, 20.387%
Required Clock Path Delay	cell: 0.675, 49.083%; route: 0.701, 50.917%

Path7

Path Summary:

Slack	10.868
Data Arrival Time	12.218
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.217	0.682	tNET	RR	1	R20C53[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C53[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.349	-0.053	tHld		1	R20C53[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	0.025
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.682, 81.190%; tC2Q: 0.158, 18.810%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path8

Path Summary:

Slack	10.868
Data Arrival Time	12.218
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.217	0.682	tNET	RR	1	R20C53[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C53[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.349	-0.053	tHld		1	R20C53[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	0.025
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.682, 81.190%; tC2Q: 0.158, 18.810%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path9

Path Summary:

Slack	10.868
Data Arrival Time	12.218
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.217	0.682	tNET	RR	1	R20C53[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C53[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.349	-0.053	tHld		1	R20C53[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	0.025
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.682, 81.190%; tC2Q: 0.158, 18.810%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path10

Path Summary:

Slack	10.868
Data Arrival Time	12.218
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.217	0.682	tNET	RR	1	R20C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.349	-0.053	tHld		1	R20C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.025
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.682, 81.190%; tC2Q: 0.158, 18.810%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path11

Path Summary:

Slack	10.868
Data Arrival Time	12.218
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.217	0.682	tNET	RR	1	R20C53[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C53[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.349	-0.053	tHld		1	R20C53[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	0.025
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.682, 81.190%; tC2Q: 0.158, 18.810%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path12

Path Summary:

Slack	10.870
Data Arrival Time	12.219
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.219	0.684	tNET	RR	1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
1.349	-0.053	tHld		1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	0.025
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.684, 81.235%; tC2Q: 0.158, 18.765%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path13

Path Summary:

Slack	10.870
Data Arrival Time	12.219
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.219	0.684	tNET	RR	1	R20C57[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
1.349	-0.053	tHld		1	R20C57[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.025
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.684, 81.235%; tC2Q: 0.158, 18.765%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path14

Path Summary:

Slack	10.874
Data Arrival Time	12.219
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.219	0.684	tNET	RR	1	R20C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.345	-0.053	tHld		1	R20C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	0.021
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.684, 81.235%; tC2Q: 0.158, 18.765%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path15

Path Summary:

Slack	10.874
Data Arrival Time	12.219
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.219	0.684	tNET	RR	1	R20C56[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C56[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
1.345	-0.053	tHld		1	R20C56[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	0.021
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.684, 81.235%; tC2Q: 0.158, 18.765%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path16

Path Summary:

Slack	10.874
Data Arrival Time	12.219
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.219	0.684	tNET	RR	1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.345	-0.053	tHld		1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	0.021
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.684, 81.235%; tC2Q: 0.158, 18.765%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path17

Path Summary:

Slack	10.906
Data Arrival Time	12.233
Data Required Time	1.326
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.233	0.697	tNET	RR	1	R27C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
1.326	-0.053	tHld		1	R27C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	0.002
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.697, 81.520%; tC2Q: 0.158, 18.480%
Required Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%

Path18

Path Summary:

Slack	10.906
Data Arrival Time	12.233
Data Required Time	1.326
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.233	0.697	tNET	RR	1	R27C54[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C54[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.326	-0.053	tHld		1	R27C54[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.002
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.697, 81.520%; tC2Q: 0.158, 18.480%
Required Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%

Path19

Path Summary:

Slack	10.906
Data Arrival Time	12.233
Data Required Time	1.326
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.233	0.697	tNET	RR	1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
1.326	-0.053	tHld		1	R27C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	0.002
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.697, 81.520%; tC2Q: 0.158, 18.480%
Required Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%

Path20

Path Summary:

Slack	10.910
Data Arrival Time	12.233
Data Required Time	1.322
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.233	0.697	tNET	RR	1	R27C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
1.322	-0.053	tHld		1	R27C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.002
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.697, 81.520%; tC2Q: 0.158, 18.480%
Required Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%

Path21

Path Summary:

Slack	10.910
Data Arrival Time	12.233
Data Required Time	1.322
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.233	0.697	tNET	RR	1	R27C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.322	-0.053	tHld		1	R27C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.002
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.697, 81.520%; tC2Q: 0.158, 18.480%
Required Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%

Path22

Path Summary:

Slack	10.970
Data Arrival Time	12.316
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.315	0.780	tNET	RR	1	R20C54[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C54[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
1.345	-0.053	tHld		1	R20C54[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	0.021
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.780, 83.156%; tC2Q: 0.158, 16.844%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path23

Path Summary:

Slack	10.970
Data Arrival Time	12.316
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.315	0.780	tNET	RR	1	R20C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.345	-0.053	tHld		1	R20C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.021
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.780, 83.156%; tC2Q: 0.158, 16.844%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path24

Path Summary:

Slack	11.018
Data Arrival Time	12.348
Data Required Time	1.331
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.348	0.813	tNET	RR	1	R27C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.384	0.708	tNET	RR	1	R27C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
1.331	-0.053	tHld		1	R27C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.006
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.813, 83.728%; tC2Q: 0.158, 16.272%
Required Clock Path Delay	cell: 0.675, 48.825%; route: 0.708, 51.175%

Path25

Path Summary:

Slack	11.018
Data Arrival Time	12.348
Data Required Time	1.331
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2017	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	53	R15C56[3][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.348	0.813	tNET	RR	1	R27C57[2][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2017	IOB29[A]	clk_ibuf/O
1.384	0.708	tNET	RR	1	R27C57[2][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
1.331	-0.053	tHld		1	R27C57[2][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.813, 83.728%; tC2Q: 0.158, 16.272%
Required Clock Path Delay	cell: 0.675, 48.825%; route: 0.708, 51.175%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKB

MPW2

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW3

MPW Summary:

Slack:	7.753
Actual Width:	8.753
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mem_data_1_mem_data_1_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.618	1.930	tNET	FF	mem_data_1_mem_data_1_0_0_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.371	0.695	tNET	RR	mem_data_1_mem_data_1_0_0_s/CLK

MPW4

MPW Summary:

Slack:	7.757
Actual Width:	8.757
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.618	1.930	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.375	0.699	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW5

MPW Summary:

Slack:	7.757
Actual Width:	8.757
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.618	1.930	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.375	0.699	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW6

MPW Summary:

Slack:	7.757
Actual Width:	8.757
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.618	1.930	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.375	0.699	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

MPW7

MPW Summary:

Slack:	7.757
Actual Width:	8.757
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.618	1.930	tNET	FF	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.375	0.699	tNET	RR	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKA

MPW8

MPW Summary:

Slack:	7.762
Actual Width:	8.762
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.623	1.941	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.385	0.708	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW9

MPW Summary:

Slack:	7.762
Actual Width:	8.762
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk
Objects:	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.623	1.941	tNET	RR	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.385	0.708	tNET	FF	FP_Sqrt/FP_Sqrt_inst/exp_adelay[1]_exp_adelay[1]_0_0_s/CLKB

MPW10

MPW Summary:

Slack:	7.762
Actual Width:	8.762
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.608	1.921	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.371	0.695	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2017	clk_d	6.286	1.982
1669	n377_3	12.133	3.786
330	control0[0]	2.423	3.004
96	n20_3	46.626	0.894
79	n897_5	42.337	2.365
77	n621_4	15.010	1.081
76	data_out_shift_reg_73_7	44.247	2.661
73	n897_4	42.128	2.693
54	n621_5	15.498	0.993
54	n621_5	13.504	1.408

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R4C23	59.72%
R4C24	59.72%
R11C29	58.33%
R11C34	56.94%
R11C37	56.94%
R8C45	56.94%
R16C45	56.94%
R32C47	56.94%
R7C24	56.94%
R26C27	56.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]