Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\Color_Correction_Matrix\data\ccm_top.v C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\Color_Correction_Matrix\data\ccm_top_wrap.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-3 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Thu Aug 03 11:04:18 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Color_Correction_Matrix_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.203s, Peak memory usage = 36.961MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 36.961MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 36.961MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 36.961MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 36.961MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 36.961MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 36.961MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 36.961MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 36.961MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 36.961MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 36.961MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 36.961MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.263s, Peak memory usage = 50.469MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 50.469MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 50.469MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.635s, Elapsed time = 0h 0m 0.692s, Peak memory usage = 50.469MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 105 |
| I/O Buf | 97 |
| IBUF | 70 |
| OBUF | 27 |
| Register | 650 |
| DFFPE | 228 |
| DFFC | 217 |
| DFFCE | 205 |
| LUT | 90 |
| LUT2 | 7 |
| LUT3 | 56 |
| LUT4 | 27 |
| ALU | 216 |
| ALU | 216 |
| INV | 1 |
| INV | 1 |
| DSP | |
| MULT18X18 | 9 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 307(91 LUTs, 216 ALUs) / 20736 | 2% |
| Register | 650 / 16173 | 5% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 650 / 16173 | 5% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.0(MHz) | 391.3(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 7.445 |
| Data Arrival Time | 3.383 |
| Data Required Time | 10.828 |
| From | ccm_top/acc_B_2_0_s1 |
| To | ccm_top/acc_B_23_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 659 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | ccm_top/acc_B_2_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | ccm_top/acc_B_2_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | ccm_top/n2011_s/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | ccm_top/n2011_s/COUT |
| 1.901 | 0.000 | tNET | RR | 1 | ccm_top/n2010_s/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | ccm_top/n2010_s/COUT |
| 1.937 | 0.000 | tNET | FF | 1 | ccm_top/n2009_s/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | ccm_top/n2009_s/COUT |
| 1.972 | 0.000 | tNET | FF | 1 | ccm_top/n2008_s/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | ccm_top/n2008_s/COUT |
| 2.007 | 0.000 | tNET | FF | 1 | ccm_top/n2007_s/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | ccm_top/n2007_s/COUT |
| 2.042 | 0.000 | tNET | FF | 1 | ccm_top/n2006_s/CIN |
| 2.078 | 0.035 | tINS | FF | 1 | ccm_top/n2006_s/COUT |
| 2.078 | 0.000 | tNET | FF | 1 | ccm_top/n2005_s/CIN |
| 2.113 | 0.035 | tINS | FF | 1 | ccm_top/n2005_s/COUT |
| 2.113 | 0.000 | tNET | FF | 1 | ccm_top/n2004_s/CIN |
| 2.148 | 0.035 | tINS | FF | 1 | ccm_top/n2004_s/COUT |
| 2.148 | 0.000 | tNET | FF | 1 | ccm_top/n2003_s/CIN |
| 2.183 | 0.035 | tINS | FF | 1 | ccm_top/n2003_s/COUT |
| 2.183 | 0.000 | tNET | FF | 1 | ccm_top/n2002_s/CIN |
| 2.218 | 0.035 | tINS | FF | 1 | ccm_top/n2002_s/COUT |
| 2.218 | 0.000 | tNET | FF | 1 | ccm_top/n2001_s/CIN |
| 2.254 | 0.035 | tINS | FF | 1 | ccm_top/n2001_s/COUT |
| 2.254 | 0.000 | tNET | FF | 2 | ccm_top/n2000_s/CIN |
| 2.289 | 0.035 | tINS | FF | 1 | ccm_top/n2000_s/COUT |
| 2.289 | 0.000 | tNET | FF | 2 | ccm_top/n1999_s/CIN |
| 2.324 | 0.035 | tINS | FF | 1 | ccm_top/n1999_s/COUT |
| 2.324 | 0.000 | tNET | FF | 2 | ccm_top/n1998_s/CIN |
| 2.359 | 0.035 | tINS | FF | 1 | ccm_top/n1998_s/COUT |
| 2.359 | 0.000 | tNET | FF | 2 | ccm_top/n1997_s/CIN |
| 2.394 | 0.035 | tINS | FF | 1 | ccm_top/n1997_s/COUT |
| 2.394 | 0.000 | tNET | FF | 2 | ccm_top/n1996_s/CIN |
| 2.430 | 0.035 | tINS | FF | 1 | ccm_top/n1996_s/COUT |
| 2.430 | 0.000 | tNET | FF | 2 | ccm_top/n1995_s/CIN |
| 2.465 | 0.035 | tINS | FF | 1 | ccm_top/n1995_s/COUT |
| 2.465 | 0.000 | tNET | FF | 2 | ccm_top/n1994_s/CIN |
| 2.500 | 0.035 | tINS | FF | 1 | ccm_top/n1994_s/COUT |
| 2.500 | 0.000 | tNET | FF | 2 | ccm_top/n1993_s/CIN |
| 2.535 | 0.035 | tINS | FF | 1 | ccm_top/n1993_s/COUT |
| 2.535 | 0.000 | tNET | FF | 2 | ccm_top/n1992_s/CIN |
| 2.570 | 0.035 | tINS | FF | 1 | ccm_top/n1992_s/COUT |
| 2.570 | 0.000 | tNET | FF | 2 | ccm_top/n1991_s/CIN |
| 2.606 | 0.035 | tINS | FF | 1 | ccm_top/n1991_s/COUT |
| 2.606 | 0.000 | tNET | FF | 1 | ccm_top/n1990_s/CIN |
| 2.641 | 0.035 | tINS | FF | 1 | ccm_top/n1990_s/COUT |
| 2.641 | 0.000 | tNET | FF | 1 | ccm_top/n1989_s/CIN |
| 2.676 | 0.035 | tINS | FF | 1 | ccm_top/n1989_s/COUT |
| 2.676 | 0.000 | tNET | FF | 1 | ccm_top/n1988_s/CIN |
| 3.146 | 0.470 | tINS | FF | 1 | ccm_top/n1988_s/SUM |
| 3.383 | 0.237 | tNET | FF | 1 | ccm_top/acc_B_23_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 659 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | ccm_top/acc_B_23_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | ccm_top/acc_B_23_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.814, 71.988%; route: 0.474, 18.807%; tC2Q: 0.232, 9.205% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 7.445 |
| Data Arrival Time | 3.383 |
| Data Required Time | 10.828 |
| From | ccm_top/acc_G_2_0_s1 |
| To | ccm_top/acc_G_23_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 659 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | ccm_top/acc_G_2_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | ccm_top/acc_G_2_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | ccm_top/n1861_s/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | ccm_top/n1861_s/COUT |
| 1.901 | 0.000 | tNET | RR | 1 | ccm_top/n1860_s/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | ccm_top/n1860_s/COUT |
| 1.937 | 0.000 | tNET | FF | 1 | ccm_top/n1859_s/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | ccm_top/n1859_s/COUT |
| 1.972 | 0.000 | tNET | FF | 1 | ccm_top/n1858_s/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | ccm_top/n1858_s/COUT |
| 2.007 | 0.000 | tNET | FF | 1 | ccm_top/n1857_s/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | ccm_top/n1857_s/COUT |
| 2.042 | 0.000 | tNET | FF | 1 | ccm_top/n1856_s/CIN |
| 2.078 | 0.035 | tINS | FF | 1 | ccm_top/n1856_s/COUT |
| 2.078 | 0.000 | tNET | FF | 1 | ccm_top/n1855_s/CIN |
| 2.113 | 0.035 | tINS | FF | 1 | ccm_top/n1855_s/COUT |
| 2.113 | 0.000 | tNET | FF | 1 | ccm_top/n1854_s/CIN |
| 2.148 | 0.035 | tINS | FF | 1 | ccm_top/n1854_s/COUT |
| 2.148 | 0.000 | tNET | FF | 1 | ccm_top/n1853_s/CIN |
| 2.183 | 0.035 | tINS | FF | 1 | ccm_top/n1853_s/COUT |
| 2.183 | 0.000 | tNET | FF | 1 | ccm_top/n1852_s/CIN |
| 2.218 | 0.035 | tINS | FF | 1 | ccm_top/n1852_s/COUT |
| 2.218 | 0.000 | tNET | FF | 1 | ccm_top/n1851_s/CIN |
| 2.254 | 0.035 | tINS | FF | 1 | ccm_top/n1851_s/COUT |
| 2.254 | 0.000 | tNET | FF | 2 | ccm_top/n1850_s/CIN |
| 2.289 | 0.035 | tINS | FF | 1 | ccm_top/n1850_s/COUT |
| 2.289 | 0.000 | tNET | FF | 2 | ccm_top/n1849_s/CIN |
| 2.324 | 0.035 | tINS | FF | 1 | ccm_top/n1849_s/COUT |
| 2.324 | 0.000 | tNET | FF | 2 | ccm_top/n1848_s/CIN |
| 2.359 | 0.035 | tINS | FF | 1 | ccm_top/n1848_s/COUT |
| 2.359 | 0.000 | tNET | FF | 2 | ccm_top/n1847_s/CIN |
| 2.394 | 0.035 | tINS | FF | 1 | ccm_top/n1847_s/COUT |
| 2.394 | 0.000 | tNET | FF | 2 | ccm_top/n1846_s/CIN |
| 2.430 | 0.035 | tINS | FF | 1 | ccm_top/n1846_s/COUT |
| 2.430 | 0.000 | tNET | FF | 2 | ccm_top/n1845_s/CIN |
| 2.465 | 0.035 | tINS | FF | 1 | ccm_top/n1845_s/COUT |
| 2.465 | 0.000 | tNET | FF | 2 | ccm_top/n1844_s/CIN |
| 2.500 | 0.035 | tINS | FF | 1 | ccm_top/n1844_s/COUT |
| 2.500 | 0.000 | tNET | FF | 2 | ccm_top/n1843_s/CIN |
| 2.535 | 0.035 | tINS | FF | 1 | ccm_top/n1843_s/COUT |
| 2.535 | 0.000 | tNET | FF | 2 | ccm_top/n1842_s/CIN |
| 2.570 | 0.035 | tINS | FF | 1 | ccm_top/n1842_s/COUT |
| 2.570 | 0.000 | tNET | FF | 2 | ccm_top/n1841_s/CIN |
| 2.606 | 0.035 | tINS | FF | 1 | ccm_top/n1841_s/COUT |
| 2.606 | 0.000 | tNET | FF | 1 | ccm_top/n1840_s/CIN |
| 2.641 | 0.035 | tINS | FF | 1 | ccm_top/n1840_s/COUT |
| 2.641 | 0.000 | tNET | FF | 1 | ccm_top/n1839_s/CIN |
| 2.676 | 0.035 | tINS | FF | 1 | ccm_top/n1839_s/COUT |
| 2.676 | 0.000 | tNET | FF | 1 | ccm_top/n1838_s/CIN |
| 3.146 | 0.470 | tINS | FF | 1 | ccm_top/n1838_s/SUM |
| 3.383 | 0.237 | tNET | FF | 1 | ccm_top/acc_G_23_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 659 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | ccm_top/acc_G_23_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | ccm_top/acc_G_23_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.814, 71.988%; route: 0.474, 18.807%; tC2Q: 0.232, 9.205% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 7.445 |
| Data Arrival Time | 3.383 |
| Data Required Time | 10.828 |
| From | ccm_top/acc_R_2_0_s1 |
| To | ccm_top/acc_R_23_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 659 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | ccm_top/acc_R_2_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | ccm_top/acc_R_2_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | ccm_top/n1711_s/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | ccm_top/n1711_s/COUT |
| 1.901 | 0.000 | tNET | RR | 1 | ccm_top/n1710_s/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | ccm_top/n1710_s/COUT |
| 1.937 | 0.000 | tNET | FF | 1 | ccm_top/n1709_s/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | ccm_top/n1709_s/COUT |
| 1.972 | 0.000 | tNET | FF | 1 | ccm_top/n1708_s/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | ccm_top/n1708_s/COUT |
| 2.007 | 0.000 | tNET | FF | 1 | ccm_top/n1707_s/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | ccm_top/n1707_s/COUT |
| 2.042 | 0.000 | tNET | FF | 1 | ccm_top/n1706_s/CIN |
| 2.078 | 0.035 | tINS | FF | 1 | ccm_top/n1706_s/COUT |
| 2.078 | 0.000 | tNET | FF | 1 | ccm_top/n1705_s/CIN |
| 2.113 | 0.035 | tINS | FF | 1 | ccm_top/n1705_s/COUT |
| 2.113 | 0.000 | tNET | FF | 1 | ccm_top/n1704_s/CIN |
| 2.148 | 0.035 | tINS | FF | 1 | ccm_top/n1704_s/COUT |
| 2.148 | 0.000 | tNET | FF | 1 | ccm_top/n1703_s/CIN |
| 2.183 | 0.035 | tINS | FF | 1 | ccm_top/n1703_s/COUT |
| 2.183 | 0.000 | tNET | FF | 1 | ccm_top/n1702_s/CIN |
| 2.218 | 0.035 | tINS | FF | 1 | ccm_top/n1702_s/COUT |
| 2.218 | 0.000 | tNET | FF | 1 | ccm_top/n1701_s/CIN |
| 2.254 | 0.035 | tINS | FF | 1 | ccm_top/n1701_s/COUT |
| 2.254 | 0.000 | tNET | FF | 2 | ccm_top/n1700_s/CIN |
| 2.289 | 0.035 | tINS | FF | 1 | ccm_top/n1700_s/COUT |
| 2.289 | 0.000 | tNET | FF | 2 | ccm_top/n1699_s/CIN |
| 2.324 | 0.035 | tINS | FF | 1 | ccm_top/n1699_s/COUT |
| 2.324 | 0.000 | tNET | FF | 2 | ccm_top/n1698_s/CIN |
| 2.359 | 0.035 | tINS | FF | 1 | ccm_top/n1698_s/COUT |
| 2.359 | 0.000 | tNET | FF | 2 | ccm_top/n1697_s/CIN |
| 2.394 | 0.035 | tINS | FF | 1 | ccm_top/n1697_s/COUT |
| 2.394 | 0.000 | tNET | FF | 2 | ccm_top/n1696_s/CIN |
| 2.430 | 0.035 | tINS | FF | 1 | ccm_top/n1696_s/COUT |
| 2.430 | 0.000 | tNET | FF | 2 | ccm_top/n1695_s/CIN |
| 2.465 | 0.035 | tINS | FF | 1 | ccm_top/n1695_s/COUT |
| 2.465 | 0.000 | tNET | FF | 2 | ccm_top/n1694_s/CIN |
| 2.500 | 0.035 | tINS | FF | 1 | ccm_top/n1694_s/COUT |
| 2.500 | 0.000 | tNET | FF | 2 | ccm_top/n1693_s/CIN |
| 2.535 | 0.035 | tINS | FF | 1 | ccm_top/n1693_s/COUT |
| 2.535 | 0.000 | tNET | FF | 2 | ccm_top/n1692_s/CIN |
| 2.570 | 0.035 | tINS | FF | 1 | ccm_top/n1692_s/COUT |
| 2.570 | 0.000 | tNET | FF | 2 | ccm_top/n1691_s/CIN |
| 2.606 | 0.035 | tINS | FF | 1 | ccm_top/n1691_s/COUT |
| 2.606 | 0.000 | tNET | FF | 1 | ccm_top/n1690_s/CIN |
| 2.641 | 0.035 | tINS | FF | 1 | ccm_top/n1690_s/COUT |
| 2.641 | 0.000 | tNET | FF | 1 | ccm_top/n1689_s/CIN |
| 2.676 | 0.035 | tINS | FF | 1 | ccm_top/n1689_s/COUT |
| 2.676 | 0.000 | tNET | FF | 1 | ccm_top/n1688_s/CIN |
| 3.146 | 0.470 | tINS | FF | 1 | ccm_top/n1688_s/SUM |
| 3.383 | 0.237 | tNET | FF | 1 | ccm_top/acc_R_23_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 659 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | ccm_top/acc_R_23_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | ccm_top/acc_R_23_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.814, 71.988%; route: 0.474, 18.807%; tC2Q: 0.232, 9.205% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 7.454 |
| Data Arrival Time | 3.374 |
| Data Required Time | 10.828 |
| From | ccm_top/mult_1200_s2 |
| To | ccm_top/acc_B_2_23_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 659 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 24 | ccm_top/mult_1200_s2/CLK |
| 1.085 | 0.223 | tC2Q | RF | 1 | ccm_top/mult_1200_s2/DOUT[0] |
| 1.322 | 0.237 | tNET | FF | 2 | ccm_top/n1986_s/I1 |
| 1.892 | 0.570 | tINS | FR | 1 | ccm_top/n1986_s/COUT |
| 1.892 | 0.000 | tNET | RR | 2 | ccm_top/n1985_s/CIN |
| 1.927 | 0.035 | tINS | RF | 1 | ccm_top/n1985_s/COUT |
| 1.927 | 0.000 | tNET | FF | 2 | ccm_top/n1984_s/CIN |
| 1.963 | 0.035 | tINS | FF | 1 | ccm_top/n1984_s/COUT |
| 1.963 | 0.000 | tNET | FF | 2 | ccm_top/n1983_s/CIN |
| 1.998 | 0.035 | tINS | FF | 1 | ccm_top/n1983_s/COUT |
| 1.998 | 0.000 | tNET | FF | 2 | ccm_top/n1982_s/CIN |
| 2.033 | 0.035 | tINS | FF | 1 | ccm_top/n1982_s/COUT |
| 2.033 | 0.000 | tNET | FF | 2 | ccm_top/n1981_s/CIN |
| 2.068 | 0.035 | tINS | FF | 1 | ccm_top/n1981_s/COUT |
| 2.068 | 0.000 | tNET | FF | 2 | ccm_top/n1980_s/CIN |
| 2.103 | 0.035 | tINS | FF | 1 | ccm_top/n1980_s/COUT |
| 2.103 | 0.000 | tNET | FF | 2 | ccm_top/n1979_s/CIN |
| 2.139 | 0.035 | tINS | FF | 1 | ccm_top/n1979_s/COUT |
| 2.139 | 0.000 | tNET | FF | 2 | ccm_top/n1978_s/CIN |
| 2.174 | 0.035 | tINS | FF | 1 | ccm_top/n1978_s/COUT |
| 2.174 | 0.000 | tNET | FF | 2 | ccm_top/n1977_s/CIN |
| 2.209 | 0.035 | tINS | FF | 1 | ccm_top/n1977_s/COUT |
| 2.209 | 0.000 | tNET | FF | 2 | ccm_top/n1976_s/CIN |
| 2.244 | 0.035 | tINS | FF | 1 | ccm_top/n1976_s/COUT |
| 2.244 | 0.000 | tNET | FF | 2 | ccm_top/n1975_s/CIN |
| 2.279 | 0.035 | tINS | FF | 1 | ccm_top/n1975_s/COUT |
| 2.279 | 0.000 | tNET | FF | 2 | ccm_top/n1974_s/CIN |
| 2.315 | 0.035 | tINS | FF | 1 | ccm_top/n1974_s/COUT |
| 2.315 | 0.000 | tNET | FF | 2 | ccm_top/n1973_s/CIN |
| 2.350 | 0.035 | tINS | FF | 1 | ccm_top/n1973_s/COUT |
| 2.350 | 0.000 | tNET | FF | 2 | ccm_top/n1972_s/CIN |
| 2.385 | 0.035 | tINS | FF | 1 | ccm_top/n1972_s/COUT |
| 2.385 | 0.000 | tNET | FF | 2 | ccm_top/n1971_s/CIN |
| 2.420 | 0.035 | tINS | FF | 1 | ccm_top/n1971_s/COUT |
| 2.420 | 0.000 | tNET | FF | 2 | ccm_top/n1970_s/CIN |
| 2.455 | 0.035 | tINS | FF | 1 | ccm_top/n1970_s/COUT |
| 2.455 | 0.000 | tNET | FF | 2 | ccm_top/n1969_s/CIN |
| 2.491 | 0.035 | tINS | FF | 1 | ccm_top/n1969_s/COUT |
| 2.491 | 0.000 | tNET | FF | 2 | ccm_top/n1968_s/CIN |
| 2.526 | 0.035 | tINS | FF | 1 | ccm_top/n1968_s/COUT |
| 2.526 | 0.000 | tNET | FF | 2 | ccm_top/n1967_s/CIN |
| 2.561 | 0.035 | tINS | FF | 1 | ccm_top/n1967_s/COUT |
| 2.561 | 0.000 | tNET | FF | 2 | ccm_top/n1966_s/CIN |
| 2.596 | 0.035 | tINS | FF | 1 | ccm_top/n1966_s/COUT |
| 2.596 | 0.000 | tNET | FF | 2 | ccm_top/n1965_s/CIN |
| 2.631 | 0.035 | tINS | FF | 1 | ccm_top/n1965_s/COUT |
| 2.631 | 0.000 | tNET | FF | 2 | ccm_top/n1964_s/CIN |
| 2.667 | 0.035 | tINS | FF | 1 | ccm_top/n1964_s/COUT |
| 2.667 | 0.000 | tNET | FF | 1 | ccm_top/n1963_s/CIN |
| 3.137 | 0.470 | tINS | FF | 1 | ccm_top/n1963_s/SUM |
| 3.374 | 0.237 | tNET | FF | 1 | ccm_top/acc_B_2_23_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 659 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | ccm_top/acc_B_2_23_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | ccm_top/acc_B_2_23_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.814, 72.257%; route: 0.474, 18.876%; tC2Q: 0.223, 8.867% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 7.454 |
| Data Arrival Time | 3.374 |
| Data Required Time | 10.828 |
| From | ccm_top/mult_1198_s2 |
| To | ccm_top/acc_B_1_23_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 659 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 24 | ccm_top/mult_1198_s2/CLK |
| 1.085 | 0.223 | tC2Q | RF | 1 | ccm_top/mult_1198_s2/DOUT[0] |
| 1.322 | 0.237 | tNET | FF | 2 | ccm_top/n1961_s/I1 |
| 1.892 | 0.570 | tINS | FR | 1 | ccm_top/n1961_s/COUT |
| 1.892 | 0.000 | tNET | RR | 2 | ccm_top/n1960_s/CIN |
| 1.927 | 0.035 | tINS | RF | 1 | ccm_top/n1960_s/COUT |
| 1.927 | 0.000 | tNET | FF | 2 | ccm_top/n1959_s/CIN |
| 1.963 | 0.035 | tINS | FF | 1 | ccm_top/n1959_s/COUT |
| 1.963 | 0.000 | tNET | FF | 2 | ccm_top/n1958_s/CIN |
| 1.998 | 0.035 | tINS | FF | 1 | ccm_top/n1958_s/COUT |
| 1.998 | 0.000 | tNET | FF | 2 | ccm_top/n1957_s/CIN |
| 2.033 | 0.035 | tINS | FF | 1 | ccm_top/n1957_s/COUT |
| 2.033 | 0.000 | tNET | FF | 2 | ccm_top/n1956_s/CIN |
| 2.068 | 0.035 | tINS | FF | 1 | ccm_top/n1956_s/COUT |
| 2.068 | 0.000 | tNET | FF | 2 | ccm_top/n1955_s/CIN |
| 2.103 | 0.035 | tINS | FF | 1 | ccm_top/n1955_s/COUT |
| 2.103 | 0.000 | tNET | FF | 2 | ccm_top/n1954_s/CIN |
| 2.139 | 0.035 | tINS | FF | 1 | ccm_top/n1954_s/COUT |
| 2.139 | 0.000 | tNET | FF | 2 | ccm_top/n1953_s/CIN |
| 2.174 | 0.035 | tINS | FF | 1 | ccm_top/n1953_s/COUT |
| 2.174 | 0.000 | tNET | FF | 2 | ccm_top/n1952_s/CIN |
| 2.209 | 0.035 | tINS | FF | 1 | ccm_top/n1952_s/COUT |
| 2.209 | 0.000 | tNET | FF | 2 | ccm_top/n1951_s/CIN |
| 2.244 | 0.035 | tINS | FF | 1 | ccm_top/n1951_s/COUT |
| 2.244 | 0.000 | tNET | FF | 2 | ccm_top/n1950_s/CIN |
| 2.279 | 0.035 | tINS | FF | 1 | ccm_top/n1950_s/COUT |
| 2.279 | 0.000 | tNET | FF | 2 | ccm_top/n1949_s/CIN |
| 2.315 | 0.035 | tINS | FF | 1 | ccm_top/n1949_s/COUT |
| 2.315 | 0.000 | tNET | FF | 2 | ccm_top/n1948_s/CIN |
| 2.350 | 0.035 | tINS | FF | 1 | ccm_top/n1948_s/COUT |
| 2.350 | 0.000 | tNET | FF | 2 | ccm_top/n1947_s/CIN |
| 2.385 | 0.035 | tINS | FF | 1 | ccm_top/n1947_s/COUT |
| 2.385 | 0.000 | tNET | FF | 2 | ccm_top/n1946_s/CIN |
| 2.420 | 0.035 | tINS | FF | 1 | ccm_top/n1946_s/COUT |
| 2.420 | 0.000 | tNET | FF | 2 | ccm_top/n1945_s/CIN |
| 2.455 | 0.035 | tINS | FF | 1 | ccm_top/n1945_s/COUT |
| 2.455 | 0.000 | tNET | FF | 2 | ccm_top/n1944_s/CIN |
| 2.491 | 0.035 | tINS | FF | 1 | ccm_top/n1944_s/COUT |
| 2.491 | 0.000 | tNET | FF | 2 | ccm_top/n1943_s/CIN |
| 2.526 | 0.035 | tINS | FF | 1 | ccm_top/n1943_s/COUT |
| 2.526 | 0.000 | tNET | FF | 2 | ccm_top/n1942_s/CIN |
| 2.561 | 0.035 | tINS | FF | 1 | ccm_top/n1942_s/COUT |
| 2.561 | 0.000 | tNET | FF | 2 | ccm_top/n1941_s/CIN |
| 2.596 | 0.035 | tINS | FF | 1 | ccm_top/n1941_s/COUT |
| 2.596 | 0.000 | tNET | FF | 2 | ccm_top/n1940_s/CIN |
| 2.631 | 0.035 | tINS | FF | 1 | ccm_top/n1940_s/COUT |
| 2.631 | 0.000 | tNET | FF | 2 | ccm_top/n1939_s/CIN |
| 2.667 | 0.035 | tINS | FF | 1 | ccm_top/n1939_s/COUT |
| 2.667 | 0.000 | tNET | FF | 1 | ccm_top/n1938_s/CIN |
| 3.137 | 0.470 | tINS | FF | 1 | ccm_top/n1938_s/SUM |
| 3.374 | 0.237 | tNET | FF | 1 | ccm_top/acc_B_1_23_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 659 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | ccm_top/acc_B_1_23_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | ccm_top/acc_B_1_23_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.814, 72.257%; route: 0.474, 18.876%; tC2Q: 0.223, 8.867% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |