Synthesis Messages

Report Title GowinSynthesis Report
Design File /netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/Gamma_Correction/data/gamma_top.v
/netapp/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/Gamma_Correction/data/gamma_top_wrap.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Wed Mar 3 17:24:55 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gamma_Correction_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.24s, Elapsed time = 0h 0m 0.321s, Peak memory usage = 54.301MB
Running netlist conversion:
    CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 54.359MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 54.586MB
    Optimizing Phase 1: CPU time = 0h 0m 0.01s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 54.684MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 54.773MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.01s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 55.059MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 55.133MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 55.184MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 55.270MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.01s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 55.289MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 55.289MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 55.289MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.2s, Elapsed time = 0h 0m 0.271s, Peak memory usage = 80.133MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.01s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 80.133MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 80.133MB
Total Time and Memory Usage CPU time = 0h 0m 0.489s, Elapsed time = 0h 0m 0.636s, Peak memory usage = 80.133MB

Resource

Resource Usage Summary

I/O Port 105
I/O Buf 77
    IBUF 50
    OBUF 27
Register 80
    DFFC 20
    DFFCE 60
LUT 24
    LUT2 5
    LUT3 18
    LUT4 1
INV 1
    INV 1
BSRAM 1
    SDPB 1

Resource Utilization Summary

Logic 25(25 LUTs, 0 ALUs) / 20736 1%
Register 80 / 16173 1%
  --Register as Latch 0 / 16173 0%
  --Register as FF 80 / 16173 1%
BSRAM 1 / 46 2%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 476.6(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 7.902
Data Arrival Time 2.873
Data Required Time 10.776
From gamma_top/correction/gamma_controller/waddr_d1_3_s0
To gamma_top/correction/gamma_rom/mem_mem_0_0_s
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 82 clk_ibuf/O
0.863 0.180 tNET RR 1 gamma_top/correction/gamma_controller/waddr_d1_3_s0/CLK
1.095 0.232 tC2Q RF 1 gamma_top/correction/gamma_controller/waddr_d1_3_s0/Q
1.332 0.237 tNET FF 1 gamma_top/correction/gamma_rom/mem_s4/I1
1.887 0.555 tINS FF 1 gamma_top/correction/gamma_rom/mem_s4/F
2.124 0.237 tNET FF 1 gamma_top/correction/gamma_rom/mem_s3/I1
2.694 0.570 tINS FR 1 gamma_top/correction/gamma_rom/mem_s3/F
2.874 0.180 tNET RR 1 gamma_top/correction/gamma_rom/mem_mem_0_0_s/CEA
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 82 clk_ibuf/O
10.863 0.180 tNET RR 1 gamma_top/correction/gamma_rom/mem_mem_0_0_s/CLKA
10.776 -0.087 tSu 1 gamma_top/correction/gamma_rom/mem_mem_0_0_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.125, 55.942%; route: 0.654, 32.521%; tC2Q: 0.232, 11.537%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 8.014
Data Arrival Time 2.814
Data Required Time 10.828
From gamma_top/correction/gamma_controller/rd_cnt_0_s0
To gamma_top/correction/gamma_rom/rd_addr_0_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 82 clk_ibuf/O
0.863 0.180 tNET RR 1 gamma_top/correction/gamma_controller/rd_cnt_0_s0/CLK
1.095 0.232 tC2Q RF 14 gamma_top/correction/gamma_controller/rd_cnt_0_s0/Q
1.332 0.237 tNET FF 1 gamma_top/correction/gamma_rom/n45_s2/I2
1.785 0.453 tINS FF 1 gamma_top/correction/gamma_rom/n45_s2/F
2.022 0.237 tNET FF 1 gamma_top/correction/gamma_rom/n45_s1/I1
2.577 0.555 tINS FF 1 gamma_top/correction/gamma_rom/n45_s1/F
2.814 0.237 tNET FF 1 gamma_top/correction/gamma_rom/rd_addr_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 82 clk_ibuf/O
10.863 0.180 tNET RR 1 gamma_top/correction/gamma_rom/rd_addr_0_s1/CLK
10.828 -0.035 tSu 1 gamma_top/correction/gamma_rom/rd_addr_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.008, 51.666%; route: 0.711, 36.443%; tC2Q: 0.232, 11.891%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 8.014
Data Arrival Time 2.814
Data Required Time 10.828
From gamma_top/correction/gamma_controller/rd_cnt_0_s0
To gamma_top/correction/gamma_rom/rd_addr_1_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 82 clk_ibuf/O
0.863 0.180 tNET RR 1 gamma_top/correction/gamma_controller/rd_cnt_0_s0/CLK
1.095 0.232 tC2Q RF 14 gamma_top/correction/gamma_controller/rd_cnt_0_s0/Q
1.332 0.237 tNET FF 1 gamma_top/correction/gamma_rom/n44_s2/I2
1.785 0.453 tINS FF 1 gamma_top/correction/gamma_rom/n44_s2/F
2.022 0.237 tNET FF 1 gamma_top/correction/gamma_rom/n44_s1/I1
2.577 0.555 tINS FF 1 gamma_top/correction/gamma_rom/n44_s1/F
2.814 0.237 tNET FF 1 gamma_top/correction/gamma_rom/rd_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 82 clk_ibuf/O
10.863 0.180 tNET RR 1 gamma_top/correction/gamma_rom/rd_addr_1_s1/CLK
10.828 -0.035 tSu 1 gamma_top/correction/gamma_rom/rd_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.008, 51.666%; route: 0.711, 36.443%; tC2Q: 0.232, 11.891%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 8.014
Data Arrival Time 2.814
Data Required Time 10.828
From gamma_top/correction/gamma_controller/rd_cnt_0_s0
To gamma_top/correction/gamma_rom/rd_addr_2_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 82 clk_ibuf/O
0.863 0.180 tNET RR 1 gamma_top/correction/gamma_controller/rd_cnt_0_s0/CLK
1.095 0.232 tC2Q RF 14 gamma_top/correction/gamma_controller/rd_cnt_0_s0/Q
1.332 0.237 tNET FF 1 gamma_top/correction/gamma_rom/n43_s2/I2
1.785 0.453 tINS FF 1 gamma_top/correction/gamma_rom/n43_s2/F
2.022 0.237 tNET FF 1 gamma_top/correction/gamma_rom/n43_s1/I1
2.577 0.555 tINS FF 1 gamma_top/correction/gamma_rom/n43_s1/F
2.814 0.237 tNET FF 1 gamma_top/correction/gamma_rom/rd_addr_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 82 clk_ibuf/O
10.863 0.180 tNET RR 1 gamma_top/correction/gamma_rom/rd_addr_2_s1/CLK
10.828 -0.035 tSu 1 gamma_top/correction/gamma_rom/rd_addr_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.008, 51.666%; route: 0.711, 36.443%; tC2Q: 0.232, 11.891%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 8.014
Data Arrival Time 2.814
Data Required Time 10.828
From gamma_top/correction/gamma_controller/rd_cnt_0_s0
To gamma_top/correction/gamma_rom/rd_addr_3_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 82 clk_ibuf/O
0.863 0.180 tNET RR 1 gamma_top/correction/gamma_controller/rd_cnt_0_s0/CLK
1.095 0.232 tC2Q RF 14 gamma_top/correction/gamma_controller/rd_cnt_0_s0/Q
1.332 0.237 tNET FF 1 gamma_top/correction/gamma_rom/n42_s2/I2
1.785 0.453 tINS FF 1 gamma_top/correction/gamma_rom/n42_s2/F
2.022 0.237 tNET FF 1 gamma_top/correction/gamma_rom/n42_s1/I1
2.577 0.555 tINS FF 1 gamma_top/correction/gamma_rom/n42_s1/F
2.814 0.237 tNET FF 1 gamma_top/correction/gamma_rom/rd_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 82 clk_ibuf/O
10.863 0.180 tNET RR 1 gamma_top/correction/gamma_rom/rd_addr_3_s1/CLK
10.828 -0.035 tSu 1 gamma_top/correction/gamma_rom/rd_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.008, 51.666%; route: 0.711, 36.443%; tC2Q: 0.232, 11.891%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%