Timing Messages

Report Title	Timing Analysis Report
Design File	E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\src\fpga_project.cst
Timing Constraint File	E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\src\fpga_project.sdc
Version	V1.9.8.05
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Mon Mar 21 09:42:06 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	5586
Numbers of Endpoints Analyzed	4213
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
rgmii_rxc1	Base	8.000	125.000	0.000	4.000			rgmii_rxc
tck_pad_i	Base	20.000	50.000	0.000	10.000			tck_pad_i
clkin	Base	20.000	50.000	0.000	10.000			clk
gtx_clk	Generated	8.000	125.000	0.000	4.000	clk	clkin	u_GW_PLL/pll_inst/CLKOUT
u_GW_PLL/pll_inst/CLKOUTP.default_gen_clk	Generated	8.000	125.000	0.000	4.000	clk_ibuf/I	clkin	u_GW_PLL/pll_inst/CLKOUTP
u_GW_PLL/pll_inst/CLKOUTD.default_gen_clk	Generated	16.000	62.500	0.000	8.000	clk_ibuf/I	clkin	u_GW_PLL/pll_inst/CLKOUTD
u_GW_PLL/pll_inst/CLKOUTD3.default_gen_clk	Generated	24.000	41.667	0.000	12.000	clk_ibuf/I	clkin	u_GW_PLL/pll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	rgmii_rxc1	125.000(MHz)	215.657(MHz)	6	TOP
2	tck_pad_i	50.000(MHz)	153.160(MHz)	6	TOP
3	clkin	50.000(MHz)	199.275(MHz)	6	TOP
4	gtx_clk	125.000(MHz)	125.838(MHz)	8	TOP

No timing paths to get frequency of u_GW_PLL/pll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of u_GW_PLL/pll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of u_GW_PLL/pll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
rgmii_rxc1	Setup	0.000	0
rgmii_rxc1	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
clkin	Setup	0.000	0
clkin	Hold	0.000	0
gtx_clk	Setup	0.000	0
gtx_clk	Hold	0.000	0
u_GW_PLL/pll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
u_GW_PLL/pll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
u_GW_PLL/pll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
u_GW_PLL/pll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
u_GW_PLL/pll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
u_GW_PLL/pll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.053	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[14]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.912
2	0.530	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[12]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.435
3	0.596	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[27]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.369
4	0.647	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[7]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.318
5	0.691	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[13]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.274
6	0.712	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/frm_cnt_2_s0/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.253
7	0.712	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/frm_cnt_3_s0/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.253
8	0.712	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/frm_cnt_6_s0/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.253
9	0.712	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/frm_cnt_7_s0/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.253
10	0.734	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/frm_cnt_0_s0/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.231
11	0.734	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/frm_cnt_1_s0/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.231
12	0.734	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/frm_cnt_5_s0/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.231
13	0.740	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/frm_cnt_4_s0/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.225
14	0.855	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[6]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.110
15	0.908	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[26]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.057
16	0.912	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[8]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.053
17	0.912	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[11]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	7.053
18	1.065	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[10]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	6.900
19	1.171	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[9]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	6.794
20	1.220	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[18]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	6.745
21	1.234	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[28]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	6.731
22	1.264	u_user_mac_tx_ctrl/c_state_0_s0/Q	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[2]/D	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	6.701
23	1.291	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/shift_reg_67_s1/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	6.674
24	1.291	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/shift_reg_75_s1/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	6.674
25	1.291	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q	u_user_mac_tx_ctrl/shift_reg_74_s1/CE	gtx_clk:[R]	gtx_clk:[R]	8.000	0.000	6.674

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA	rgmii_rxc1:[R]	rgmii_rxc1:[R]	0.000	0.000	0.202
2	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9]	rgmii_rxc1:[R]	rgmii_rxc1:[R]	0.000	0.000	0.474
3	0.347	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]	rgmii_rxc1:[R]	rgmii_rxc1:[R]	0.000	0.000	0.596
4	0.360	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[10]	rgmii_rxc1:[R]	rgmii_rxc1:[R]	0.000	0.000	0.478
5	0.360	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[9]	rgmii_rxc1:[R]	rgmii_rxc1:[R]	0.000	0.000	0.478
6	0.425	u_send_start_mode/cnt_15_s0/Q	u_send_start_mode/cnt_15_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
7	0.425	u_send_start_mode/cnt_16_s0/Q	u_send_start_mode/cnt_16_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
8	0.425	u_send_start_mode/cnt_17_s0/Q	u_send_start_mode/cnt_17_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
9	0.425	u_set_tx_start/cnt_2_s0/Q	u_set_tx_start/cnt_2_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
10	0.425	u_set_tx_start/cnt_14_s0/Q	u_set_tx_start/cnt_14_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
11	0.425	u_set_rx_reset/cnt_0_s0/Q	u_set_rx_reset/cnt_0_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
12	0.425	u_set_phyic_mode/cnt_1_s0/Q	u_set_phyic_mode/cnt_1_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
13	0.425	u_set_phyic_mode/cnt_10_s0/Q	u_set_phyic_mode/cnt_10_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
14	0.425	u_set_phyic_mode/cnt_14_s0/Q	u_set_phyic_mode/cnt_14_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
15	0.425	u_duplex_status/cnt_10_s0/Q	u_duplex_status/cnt_10_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
16	0.425	u_speedis10/cnt_15_s0/Q	u_speedis10/cnt_15_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
17	0.425	u_speedis10/cnt_16_s0/Q	u_speedis10/cnt_16_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
18	0.425	u_speedis1000/cnt_6_s0/Q	u_speedis1000/cnt_6_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
19	0.425	u_speedis1000/cnt_18_s0/Q	u_speedis1000/cnt_18_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
20	0.425	u_miim_ctrl/op_cnt_6_s0/Q	u_miim_ctrl/op_cnt_6_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
21	0.425	u_miim_ctrl/start_cnt_2_s0/Q	u_miim_ctrl/start_cnt_2_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
22	0.425	u_miim_ctrl/start_cnt_6_s0/Q	u_miim_ctrl/start_cnt_6_s0/D	clkin:[R]	clkin:[R]	0.000	0.000	0.436
23	0.425	u_user_mac_rx_ctrl/frm_cnt_2_s0/Q	u_user_mac_rx_ctrl/frm_cnt_2_s0/D	rgmii_rxc1:[R]	rgmii_rxc1:[R]	0.000	0.000	0.436
24	0.425	u_user_mac_rx_ctrl/frm_cnt_6_s0/Q	u_user_mac_rx_ctrl/frm_cnt_6_s0/D	rgmii_rxc1:[R]	rgmii_rxc1:[R]	0.000	0.000	0.436
25	0.425	dut/u_triple_speed_mac/u_mac_rx_ctrl/vlan_reg_Z[7]/Q	dut/u_triple_speed_mac/u_mac_rx_ctrl/vlan_reg_Z[7]/D	rgmii_rxc1:[R]	rgmii_rxc1:[R]	0.000	0.000	0.436

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.950	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.884
2	1.950	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.884
3	1.950	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.884
4	1.950	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.884
5	2.064	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.770
6	2.064	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.770
7	2.064	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.770
8	2.072	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.762
9	2.204	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.630
10	2.204	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.630
11	2.204	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.630
12	2.204	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.630
13	2.204	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.630
14	2.299	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.535
15	2.299	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.535
16	2.299	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.535
17	2.553	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.281
18	2.553	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.281
19	2.553	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.281
20	2.553	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.281
21	2.553	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.281
22	2.553	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.281
23	2.553	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.281
24	2.553	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.281
25	2.553	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	rgmii_rxc1:[F]	rgmii_rxc1:[R]	4.000	0.131	1.281

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.158	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_wrdata_5_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.169
2	1.158	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_wrdata_6_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.169
3	1.158	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_wrdata_7_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.169
4	1.158	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_wrdata_8_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.169
5	1.265	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/start_cnt_6_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.276
6	1.265	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/start_cnt_7_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.276
7	1.270	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/wrdata_reg_6_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.281
8	1.270	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/wrdata_reg_7_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.281
9	1.270	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/wrdata_reg_8_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.281
10	1.270	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/wrdata_reg_15_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.281
11	1.277	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/op_cnt_0_s1/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.288
12	1.282	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/start_cnt_0_s1/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.293
13	1.282	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_wrdata_15_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.293
14	1.282	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_phyad_0_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.293
15	1.282	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_rden_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.293
16	1.282	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_wren_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.293
17	1.282	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/start_flag_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.293
18	1.283	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/start_cnt_1_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.294
19	1.283	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/start_cnt_2_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.294
20	1.283	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/start_cnt_3_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.294
21	1.283	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/start_cnt_4_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.294
22	1.283	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/start_cnt_5_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.294
23	1.286	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_wrdata_9_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.297
24	1.286	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_regad_0_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.297
25	1.286	u_set_phyic_mode/out_s0/Q	u_miim_ctrl/miim_regad_1_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.000	1.297

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.641	3.641	1.000	Low Pulse Width	rgmii_rxc1	gao_rx_frm_byte_cnt_15_s0
2	2.641	3.641	1.000	Low Pulse Width	rgmii_rxc1	dut/u_triple_speed_mac/u_mac_rx_if_block/u_mac_rx_if_mux/gmii_rxd_int_Z[1]
3	2.641	3.641	1.000	Low Pulse Width	rgmii_rxc1	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_statistics_valid_o_tmp_Z
4	2.641	3.641	1.000	Low Pulse Width	rgmii_rxc1	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_dv_reg_Z[0]
5	2.641	3.641	1.000	Low Pulse Width	rgmii_rxc1	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_er_reg_Z[6]
6	2.641	3.641	1.000	Low Pulse Width	rgmii_rxc1	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[20]
7	2.641	3.641	1.000	Low Pulse Width	rgmii_rxc1	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[16]
8	2.641	3.641	1.000	Low Pulse Width	rgmii_rxc1	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[14]
9	2.641	3.641	1.000	Low Pulse Width	rgmii_rxc1	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[13]
10	2.641	3.641	1.000	Low Pulse Width	rgmii_rxc1	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[15]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.053
Data Arrival Time	8.155
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[14]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/F
4.007	1.131	tNET	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/I0
4.562	0.555	tINS	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/F
4.975	0.413	tNET	FF	1	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/I1
5.428	0.453	tINS	FF	10	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/F
6.107	0.679	tNET	FF	1	R35C40[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[7]/I1
6.560	0.453	tINS	FF	4	R35C40[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[7]/F
7.234	0.674	tNET	FF	1	R34C37[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[14]/I1
7.783	0.549	tINS	FR	1	R34C37[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[14]/F
7.784	0.001	tNET	RR	1	R34C37[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[14]/I2
8.155	0.371	tINS	RF	1	R34C37[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[14]/F
8.155	0.000	tNET	FF	1	R34C37[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[14]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C37[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[14]/CLK
8.208	-0.035	tSu		1	R34C37[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[14]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.351, 42.355%; route: 4.329, 54.713%; tC2Q: 0.232, 2.932%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack	0.530
Data Arrival Time	7.678
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[12]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s1/I0
1.842	0.555	tINS	FF	8	R36C18[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s1/F
2.043	0.202	tNET	FF	1	R35C18[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_2_s/I3
2.560	0.517	tINS	FF	3	R35C18[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_2_s/F
3.452	0.892	tNET	FF	1	R34C35[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[2]/I0
4.007	0.555	tINS	FF	1	R34C35[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[2]/F
4.404	0.397	tNET	FF	1	R34C36[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[15]/I1
4.775	0.371	tINS	FF	11	R34C36[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[15]/F
5.522	0.747	tNET	FF	1	R34C37[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[27]/I1
5.893	0.371	tINS	FF	4	R34C37[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[27]/F
6.558	0.665	tNET	FF	1	R33C40[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[12]/I1
7.128	0.570	tINS	FR	1	R33C40[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[12]/F
7.129	0.001	tNET	RR	1	R33C40[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[12]/I2
7.678	0.549	tINS	RR	1	R33C40[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[12]/F
7.678	0.000	tNET	RR	1	R33C40[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[12]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R33C40[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[12]/CLK
8.208	-0.035	tSu		1	R33C40[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[12]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.488, 46.915%; route: 3.715, 49.964%; tC2Q: 0.232, 3.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack	0.596
Data Arrival Time	7.612
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[27]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s1/I0
1.842	0.555	tINS	FF	8	R36C18[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s1/F
2.043	0.202	tNET	FF	1	R35C18[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_2_s/I3
2.560	0.517	tINS	FF	3	R35C18[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_2_s/F
3.452	0.892	tNET	FF	1	R34C35[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[2]/I0
4.007	0.555	tINS	FF	1	R34C35[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[2]/F
4.404	0.397	tNET	FF	1	R34C36[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[15]/I1
4.775	0.371	tINS	FF	11	R34C36[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[15]/F
5.522	0.747	tNET	FF	1	R34C37[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[27]/I1
5.893	0.371	tINS	FF	4	R34C37[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[27]/F
6.321	0.428	tNET	FF	1	R33C38[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[27]/I1
6.870	0.549	tINS	FR	1	R33C38[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[27]/F
7.042	0.172	tNET	RR	1	R32C38[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[27]/I2
7.612	0.570	tINS	RR	1	R32C38[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[27]/F
7.612	0.000	tNET	RR	1	R32C38[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[27]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R32C38[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[27]/CLK
8.208	-0.035	tSu		1	R32C38[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[27]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.488, 47.335%; route: 3.649, 49.517%; tC2Q: 0.232, 3.148%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack	0.647
Data Arrival Time	7.561
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[7]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/F
4.007	1.131	tNET	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/I0
4.562	0.555	tINS	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/F
4.975	0.413	tNET	FF	1	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/I1
5.428	0.453	tINS	FF	10	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/F
6.107	0.679	tNET	FF	1	R35C40[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[7]/I1
6.560	0.453	tINS	FF	4	R35C40[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[7]/F
6.991	0.431	tNET	FF	1	R34C39[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[7]/I1
7.561	0.570	tINS	FR	1	R34C39[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[7]/F
7.561	0.000	tNET	RR	1	R34C39[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C39[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[7]/CLK
8.208	-0.035	tSu		1	R34C39[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.001, 41.010%; route: 4.085, 55.819%; tC2Q: 0.232, 3.170%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack	0.691
Data Arrival Time	7.517
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[13]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/F
4.007	1.131	tNET	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/I0
4.562	0.555	tINS	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/F
4.975	0.413	tNET	FF	1	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/I1
5.428	0.453	tINS	FF	10	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/F
5.868	0.440	tNET	FF	1	R34C39[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_3_cZ[13]/I0
6.417	0.549	tINS	FR	1	R34C39[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_3_cZ[13]/F
6.418	0.001	tNET	RR	1	R34C39[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[13]/I2
6.967	0.549	tINS	RR	1	R34C39[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[13]/F
6.968	0.001	tNET	RR	1	R34C39[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[13]/I2
7.517	0.549	tINS	RR	1	R34C39[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[13]/F
7.517	0.000	tNET	RR	1	R34C39[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[13]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C39[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[13]/CLK
8.208	-0.035	tSu		1	R34C39[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[13]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.625, 49.836%; route: 3.417, 46.975%; tC2Q: 0.232, 3.189%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack	0.712
Data Arrival Time	7.497
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/frm_cnt_2_s0
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/I0
3.970	0.371	tINS	FF	2	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/F
4.658	0.688	tNET	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/I2
5.213	0.555	tINS	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/F
5.626	0.413	tNET	FF	1	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/I1
6.181	0.555	tINS	FF	2	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/F
6.676	0.494	tNET	FF	1	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/I2
7.138	0.462	tINS	FR	8	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/F
7.497	0.359	tNET	RR	1	R33C25[2][B]	u_user_mac_tx_ctrl/frm_cnt_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R33C25[2][B]	u_user_mac_tx_ctrl/frm_cnt_2_s0/CLK
8.208	-0.035	tSu		1	R33C25[2][B]	u_user_mac_tx_ctrl/frm_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.863, 39.472%; route: 4.158, 57.329%; tC2Q: 0.232, 3.199%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack	0.712
Data Arrival Time	7.497
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/frm_cnt_3_s0
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/I0
3.970	0.371	tINS	FF	2	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/F
4.658	0.688	tNET	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/I2
5.213	0.555	tINS	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/F
5.626	0.413	tNET	FF	1	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/I1
6.181	0.555	tINS	FF	2	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/F
6.676	0.494	tNET	FF	1	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/I2
7.138	0.462	tINS	FR	8	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/F
7.497	0.359	tNET	RR	1	R33C25[2][A]	u_user_mac_tx_ctrl/frm_cnt_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R33C25[2][A]	u_user_mac_tx_ctrl/frm_cnt_3_s0/CLK
8.208	-0.035	tSu		1	R33C25[2][A]	u_user_mac_tx_ctrl/frm_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.863, 39.472%; route: 4.158, 57.329%; tC2Q: 0.232, 3.199%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack	0.712
Data Arrival Time	7.497
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/frm_cnt_6_s0
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/I0
3.970	0.371	tINS	FF	2	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/F
4.658	0.688	tNET	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/I2
5.213	0.555	tINS	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/F
5.626	0.413	tNET	FF	1	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/I1
6.181	0.555	tINS	FF	2	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/F
6.676	0.494	tNET	FF	1	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/I2
7.138	0.462	tINS	FR	8	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/F
7.497	0.359	tNET	RR	1	R36C27[2][A]	u_user_mac_tx_ctrl/frm_cnt_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R36C27[2][A]	u_user_mac_tx_ctrl/frm_cnt_6_s0/CLK
8.208	-0.035	tSu		1	R36C27[2][A]	u_user_mac_tx_ctrl/frm_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.863, 39.472%; route: 4.158, 57.329%; tC2Q: 0.232, 3.199%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack	0.712
Data Arrival Time	7.497
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/frm_cnt_7_s0
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/I0
3.970	0.371	tINS	FF	2	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/F
4.658	0.688	tNET	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/I2
5.213	0.555	tINS	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/F
5.626	0.413	tNET	FF	1	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/I1
6.181	0.555	tINS	FF	2	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/F
6.676	0.494	tNET	FF	1	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/I2
7.138	0.462	tINS	FR	8	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/F
7.497	0.359	tNET	RR	1	R36C27[2][B]	u_user_mac_tx_ctrl/frm_cnt_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R36C27[2][B]	u_user_mac_tx_ctrl/frm_cnt_7_s0/CLK
8.208	-0.035	tSu		1	R36C27[2][B]	u_user_mac_tx_ctrl/frm_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.863, 39.472%; route: 4.158, 57.329%; tC2Q: 0.232, 3.199%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack	0.734
Data Arrival Time	7.474
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/frm_cnt_0_s0
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/I0
3.970	0.371	tINS	FF	2	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/F
4.658	0.688	tNET	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/I2
5.213	0.555	tINS	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/F
5.626	0.413	tNET	FF	1	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/I1
6.181	0.555	tINS	FF	2	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/F
6.676	0.494	tNET	FF	1	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/I2
7.138	0.462	tINS	FR	8	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/F
7.474	0.336	tNET	RR	1	R34C25[2][A]	u_user_mac_tx_ctrl/frm_cnt_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C25[2][A]	u_user_mac_tx_ctrl/frm_cnt_0_s0/CLK
8.208	-0.035	tSu		1	R34C25[2][A]	u_user_mac_tx_ctrl/frm_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.863, 39.594%; route: 4.136, 57.197%; tC2Q: 0.232, 3.208%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack	0.734
Data Arrival Time	7.474
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/frm_cnt_1_s0
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/I0
3.970	0.371	tINS	FF	2	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/F
4.658	0.688	tNET	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/I2
5.213	0.555	tINS	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/F
5.626	0.413	tNET	FF	1	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/I1
6.181	0.555	tINS	FF	2	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/F
6.676	0.494	tNET	FF	1	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/I2
7.138	0.462	tINS	FR	8	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/F
7.474	0.336	tNET	RR	1	R34C25[2][B]	u_user_mac_tx_ctrl/frm_cnt_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C25[2][B]	u_user_mac_tx_ctrl/frm_cnt_1_s0/CLK
8.208	-0.035	tSu		1	R34C25[2][B]	u_user_mac_tx_ctrl/frm_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.863, 39.594%; route: 4.136, 57.197%; tC2Q: 0.232, 3.208%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack	0.734
Data Arrival Time	7.474
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/frm_cnt_5_s0
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/I0
3.970	0.371	tINS	FF	2	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/F
4.658	0.688	tNET	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/I2
5.213	0.555	tINS	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/F
5.626	0.413	tNET	FF	1	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/I1
6.181	0.555	tINS	FF	2	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/F
6.676	0.494	tNET	FF	1	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/I2
7.138	0.462	tINS	FR	8	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/F
7.474	0.336	tNET	RR	1	R34C25[1][B]	u_user_mac_tx_ctrl/frm_cnt_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C25[1][B]	u_user_mac_tx_ctrl/frm_cnt_5_s0/CLK
8.208	-0.035	tSu		1	R34C25[1][B]	u_user_mac_tx_ctrl/frm_cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.863, 39.594%; route: 4.136, 57.197%; tC2Q: 0.232, 3.208%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack	0.740
Data Arrival Time	7.468
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/frm_cnt_4_s0
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/I0
3.970	0.371	tINS	FF	2	R38C18[1][B]	u_user_mac_tx_ctrl/n_state_2_s18/F
4.658	0.688	tNET	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/I2
5.213	0.555	tINS	FF	1	R36C25[0][B]	u_user_mac_tx_ctrl/n652_s12/F
5.626	0.413	tNET	FF	1	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/I1
6.181	0.555	tINS	FF	2	R38C26[3][A]	u_user_mac_tx_ctrl/n652_s3/F
6.676	0.494	tNET	FF	1	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/I2
7.138	0.462	tINS	FR	8	R36C25[3][A]	u_user_mac_tx_ctrl/n652_s0/F
7.468	0.331	tNET	RR	1	R35C25[1][A]	u_user_mac_tx_ctrl/frm_cnt_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R35C25[1][A]	u_user_mac_tx_ctrl/frm_cnt_4_s0/CLK
8.208	-0.035	tSu		1	R35C25[1][A]	u_user_mac_tx_ctrl/frm_cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.863, 39.627%; route: 4.130, 57.162%; tC2Q: 0.232, 3.211%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack	0.855
Data Arrival Time	7.353
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[6]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/F
4.007	1.131	tNET	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/I0
4.562	0.555	tINS	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/F
4.975	0.413	tNET	FF	1	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/I1
5.428	0.453	tINS	FF	10	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/F
6.107	0.679	tNET	FF	1	R35C40[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[7]/I1
6.560	0.453	tINS	FF	4	R35C40[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[7]/F
6.982	0.422	tNET	FF	1	R35C37[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[6]/I1
7.353	0.371	tINS	FF	1	R35C37[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[6]/F
7.353	0.000	tNET	FF	1	R35C37[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R35C37[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[6]/CLK
8.208	-0.035	tSu		1	R35C37[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[6]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.802, 39.411%; route: 4.076, 57.325%; tC2Q: 0.232, 3.263%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack	0.908
Data Arrival Time	7.300
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[26]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s/F
3.841	0.965	tNET	FF	1	R34C35[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/crc_frm_data_1_0[7]/I0
4.411	0.570	tINS	FR	1	R34C35[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/crc_frm_data_1_0[7]/F
4.583	0.172	tNET	RR	1	R34C36[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_2_i_o2[0]/I1
5.100	0.517	tINS	RF	6	R34C36[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_2_i_o2[0]/F
5.363	0.263	tNET	FF	1	R34C38[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[0]/I0
5.816	0.453	tINS	FF	6	R34C38[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[0]/F
6.009	0.193	tNET	FF	1	R33C38[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[26]/I1
6.579	0.570	tINS	FR	1	R33C38[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[26]/F
6.751	0.172	tNET	RR	1	R33C37[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[26]/I2
7.300	0.549	tINS	RR	1	R33C37[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[26]/F
7.300	0.000	tNET	RR	1	R33C37[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[26]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R33C37[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[26]/CLK
8.208	-0.035	tSu		1	R33C37[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[26]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.629, 51.425%; route: 3.196, 45.288%; tC2Q: 0.232, 3.288%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack	0.912
Data Arrival Time	7.297
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[8]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s/F
3.841	0.965	tNET	FF	1	R34C35[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/crc_frm_data_1_0[7]/I0
4.411	0.570	tINS	FR	1	R34C35[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/crc_frm_data_1_0[7]/F
4.583	0.172	tNET	RR	1	R34C36[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_2_i_o2[0]/I1
5.100	0.517	tINS	RF	6	R34C36[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_2_i_o2[0]/F
5.363	0.263	tNET	FF	1	R34C38[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[11]/I0
5.825	0.462	tINS	FR	3	R34C38[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[11]/F
6.002	0.177	tNET	RR	1	R34C39[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[8]/I1
6.572	0.570	tINS	RR	2	R34C39[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[8]/F
6.748	0.176	tNET	RR	1	R34C38[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[8]/I2
7.297	0.549	tINS	RR	1	R34C38[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[8]/F
7.297	0.000	tNET	RR	1	R34C38[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[8]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C38[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[8]/CLK
8.208	-0.035	tSu		1	R34C38[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[8]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.638, 51.578%; route: 3.183, 45.133%; tC2Q: 0.232, 3.289%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack	0.912
Data Arrival Time	7.297
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[11]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s/F
3.841	0.965	tNET	FF	1	R34C35[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/crc_frm_data_1_0[7]/I0
4.411	0.570	tINS	FR	1	R34C35[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/crc_frm_data_1_0[7]/F
4.583	0.172	tNET	RR	1	R34C36[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_2_i_o2[0]/I1
5.100	0.517	tINS	RF	6	R34C36[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_2_i_o2[0]/F
5.363	0.263	tNET	FF	1	R34C38[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[11]/I0
5.825	0.462	tINS	FR	3	R34C38[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[11]/F
6.002	0.177	tNET	RR	1	R34C39[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[8]/I1
6.572	0.570	tINS	RR	2	R34C39[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[8]/F
6.748	0.176	tNET	RR	1	R34C38[1][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[11]/I2
7.297	0.549	tINS	RR	1	R34C38[1][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[11]/F
7.297	0.000	tNET	RR	1	R34C38[1][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[11]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C38[1][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[11]/CLK
8.208	-0.035	tSu		1	R34C38[1][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[11]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.638, 51.578%; route: 3.183, 45.133%; tC2Q: 0.232, 3.289%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack	1.065
Data Arrival Time	7.143
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[10]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][A]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s/F
3.841	0.965	tNET	FF	1	R34C35[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/crc_frm_data_1_0[7]/I0
4.411	0.570	tINS	FR	1	R34C35[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/crc_frm_data_1_0[7]/F
4.583	0.172	tNET	RR	1	R34C36[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_2_i_o2[0]/I1
5.100	0.517	tINS	RF	6	R34C36[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_2_i_o2[0]/F
5.363	0.263	tNET	FF	1	R34C38[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[11]/I0
5.825	0.462	tINS	FR	3	R34C38[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[11]/F
6.002	0.177	tNET	RR	1	R34C39[1][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[10]/I2
6.572	0.570	tINS	RR	1	R34C39[1][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[10]/F
6.573	0.001	tNET	RR	1	R34C39[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[10]/I2
7.143	0.570	tINS	RR	1	R34C39[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[10]/F
7.143	0.000	tNET	RR	1	R34C39[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[10]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C39[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[10]/CLK
8.208	-0.035	tSu		1	R34C39[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[10]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.659, 53.028%; route: 3.009, 43.609%; tC2Q: 0.232, 3.362%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack	1.171
Data Arrival Time	7.037
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[9]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/F
4.007	1.131	tNET	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/I0
4.562	0.555	tINS	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/F
4.975	0.413	tNET	FF	1	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/I1
5.428	0.453	tINS	FF	10	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/F
6.116	0.688	tNET	FF	1	R34C40[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[9]/I1
6.665	0.549	tINS	FR	1	R34C40[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_1[9]/F
6.666	0.001	tNET	RR	1	R34C40[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[9]/I2
7.037	0.371	tINS	RF	1	R34C40[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[9]/F
7.037	0.000	tNET	FF	1	R34C40[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[9]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C40[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[9]/CLK
8.208	-0.035	tSu		1	R34C40[2][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[9]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.898, 42.655%; route: 3.664, 53.930%; tC2Q: 0.232, 3.415%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack	1.220
Data Arrival Time	6.988
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[18]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/F
4.007	1.131	tNET	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/I0
4.562	0.555	tINS	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/F
4.975	0.413	tNET	FF	1	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/I1
5.428	0.453	tINS	FF	10	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/F
5.868	0.440	tNET	FF	1	R34C38[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[14]/I1
6.438	0.570	tINS	FR	1	R34C38[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[14]/F
6.439	0.001	tNET	RR	1	R34C38[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[18]/I0
6.988	0.549	tINS	RR	1	R34C38[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[18]/F
6.988	0.000	tNET	RR	1	R34C38[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[18]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R34C38[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[18]/CLK
8.208	-0.035	tSu		1	R34C38[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[18]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.097, 45.918%; route: 3.416, 50.642%; tC2Q: 0.232, 3.440%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack	1.234
Data Arrival Time	6.974
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[28]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/F
4.007	1.131	tNET	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/I0
4.562	0.555	tINS	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/F
4.975	0.413	tNET	FF	1	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/I1
5.428	0.453	tINS	FF	10	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/F
5.941	0.513	tNET	FF	1	R35C39[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[28]/I1
6.511	0.570	tINS	FR	1	R35C39[3][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2[28]/F
6.512	0.001	tNET	RR	1	R35C39[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[28]/I2
6.974	0.462	tINS	RR	1	R35C39[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[28]/F
6.974	0.000	tNET	RR	1	R35C39[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[28]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R35C39[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[28]/CLK
8.208	-0.035	tSu		1	R35C39[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[28]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.010, 44.719%; route: 3.489, 51.834%; tC2Q: 0.232, 3.447%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack	1.264
Data Arrival Time	6.944
Data Required Time	8.208
From	u_user_mac_tx_ctrl/c_state_0_s0
To	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[2]
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/CLK
0.475	0.232	tC2Q	RF	23	R38C24[2][A]	u_user_mac_tx_ctrl/c_state_0_s0/Q
1.287	0.811	tNET	FF	1	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/I3
1.804	0.517	tINS	FF	10	R36C18[1][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_7_s0/F
2.423	0.619	tNET	FF	1	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/I1
2.876	0.453	tINS	FF	3	R35C17[3][B]	u_user_mac_tx_ctrl/tx_mac_data_Z_5_s/F
4.007	1.131	tNET	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/I0
4.562	0.555	tINS	FF	1	R34C36[3][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_frm_data_1_0[5]/F
4.975	0.413	tNET	FF	1	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/I1
5.428	0.453	tINS	FF	10	R33C37[2][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[12]/F
6.107	0.679	tNET	FF	1	R35C40[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[7]/I1
6.560	0.453	tINS	FF	4	R35C40[0][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/NextCRC_3_0_a2_0[7]/F
6.573	0.013	tNET	FF	1	R35C40[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[2]/I0
6.944	0.371	tINS	FF	1	R35C40[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_4_cZ[2]/F
6.944	0.000	tNET	FF	1	R35C40[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R35C40[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[2]/CLK
8.208	-0.035	tSu		1	R35C40[1][A]	dut/u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_Z[2]

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.802, 41.816%; route: 3.667, 54.722%; tC2Q: 0.232, 3.462%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack	1.291
Data Arrival Time	6.917
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/shift_reg_67_s1
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][A]	u_user_mac_tx_ctrl/n1104_s5/I0
3.970	0.371	tINS	FF	36	R38C18[1][A]	u_user_mac_tx_ctrl/n1104_s5/F
4.666	0.696	tNET	FF	1	R31C16[3][A]	u_user_mac_tx_ctrl/n1295_s6/I1
5.183	0.517	tINS	FF	17	R31C16[3][A]	u_user_mac_tx_ctrl/n1295_s6/F
5.902	0.719	tNET	FF	1	R35C19[1][B]	u_user_mac_tx_ctrl/shift_reg_79_s4/I3
6.364	0.462	tINS	FR	16	R35C19[1][B]	u_user_mac_tx_ctrl/shift_reg_79_s4/F
6.917	0.553	tNET	RR	1	R31C20[2][A]	u_user_mac_tx_ctrl/shift_reg_67_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R31C20[2][A]	u_user_mac_tx_ctrl/shift_reg_67_s1/CLK
8.208	-0.035	tSu		1	R31C20[2][A]	u_user_mac_tx_ctrl/shift_reg_67_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.270, 34.013%; route: 4.172, 62.510%; tC2Q: 0.232, 3.476%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack	1.291
Data Arrival Time	6.917
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/shift_reg_75_s1
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][A]	u_user_mac_tx_ctrl/n1104_s5/I0
3.970	0.371	tINS	FF	36	R38C18[1][A]	u_user_mac_tx_ctrl/n1104_s5/F
4.666	0.696	tNET	FF	1	R31C16[3][A]	u_user_mac_tx_ctrl/n1295_s6/I1
5.183	0.517	tINS	FF	17	R31C16[3][A]	u_user_mac_tx_ctrl/n1295_s6/F
5.902	0.719	tNET	FF	1	R35C19[1][B]	u_user_mac_tx_ctrl/shift_reg_79_s4/I3
6.364	0.462	tINS	FR	16	R35C19[1][B]	u_user_mac_tx_ctrl/shift_reg_79_s4/F
6.917	0.553	tNET	RR	1	R31C20[2][B]	u_user_mac_tx_ctrl/shift_reg_75_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R31C20[2][B]	u_user_mac_tx_ctrl/shift_reg_75_s1/CLK
8.208	-0.035	tSu		1	R31C20[2][B]	u_user_mac_tx_ctrl/shift_reg_75_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.270, 34.013%; route: 4.172, 62.510%; tC2Q: 0.232, 3.476%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack	1.291
Data Arrival Time	6.917
Data Required Time	8.208
From	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o
To	u_user_mac_tx_ctrl/shift_reg_74_s1
Launch Clk	gtx_clk:[R]
Latch Clk	gtx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					gtx_clk
0.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/CLK
0.475	0.232	tC2Q	RF	26	R39C33[0][B]	dut/u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ready_o/Q
1.724	1.248	tNET	FF	1	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/I3
2.273	0.549	tINS	FR	2	R34C22[0][B]	u_user_mac_tx_ctrl/n1677_s5/F
2.448	0.176	tNET	RR	1	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/I2
2.819	0.371	tINS	RF	5	R35C22[3][A]	u_user_mac_tx_ctrl/n1677_s2/F
3.599	0.780	tNET	FF	1	R38C18[1][A]	u_user_mac_tx_ctrl/n1104_s5/I0
3.970	0.371	tINS	FF	36	R38C18[1][A]	u_user_mac_tx_ctrl/n1104_s5/F
4.666	0.696	tNET	FF	1	R31C16[3][A]	u_user_mac_tx_ctrl/n1295_s6/I1
5.183	0.517	tINS	FF	17	R31C16[3][A]	u_user_mac_tx_ctrl/n1295_s6/F
5.902	0.719	tNET	FF	1	R35C19[1][B]	u_user_mac_tx_ctrl/shift_reg_79_s4/I3
6.364	0.462	tINS	FR	16	R35C19[1][B]	u_user_mac_tx_ctrl/shift_reg_79_s4/F
6.917	0.553	tNET	RR	1	R36C17[0][A]	u_user_mac_tx_ctrl/shift_reg_74_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					gtx_clk
8.000	0.000	tCL	RR	645	PLL_L[0]	u_GW_PLL/pll_inst/CLKOUT
8.243	0.243	tNET	RR	1	R36C17[0][A]	u_user_mac_tx_ctrl/shift_reg_74_s1/CLK
8.208	-0.035	tSu		1	R36C17[0][A]	u_user_mac_tx_ctrl/shift_reg_74_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 2.270, 34.014%; route: 4.172, 62.510%; tC2Q: 0.232, 3.476%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.190
Data Arrival Time	1.470
Data Required Time	1.280
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rgmii_rxc1:[R]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R16C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.470	0.202	tC2Q	RR	8	R16C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.470	0.000	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.280	0.012	tHld		1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%

Path2

Path Summary:

Slack	0.225
Data Arrival Time	1.743
Data Required Time	1.517
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rgmii_rxc1:[R]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R20C18[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/CLK
1.470	0.202	tC2Q	RR	1	R20C18[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q
1.743	0.272	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.517	0.249	tHld		1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%

Path3

Path Summary:

Slack	0.347
Data Arrival Time	1.865
Data Required Time	1.517
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rgmii_rxc1:[R]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R20C16[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK
1.470	0.202	tC2Q	RR	1	R20C16[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q
1.865	0.394	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.517	0.249	tHld		1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%

Path4

Path Summary:

Slack	0.360
Data Arrival Time	1.746
Data Required Time	1.386
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rgmii_rxc1:[R]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R18C18[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.470	0.202	tC2Q	RR	4	R18C18[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
1.746	0.276	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.386	0.118	tHld		1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.276, 57.753%; tC2Q: 0.202, 42.247%
Required Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%

Path5

Path Summary:

Slack	0.360
Data Arrival Time	1.746
Data Required Time	1.386
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rgmii_rxc1:[R]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R18C18[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.470	0.202	tC2Q	RR	5	R18C18[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
1.746	0.276	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.386	0.118	tHld		1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.276, 57.753%; tC2Q: 0.202, 42.247%
Required Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%

Path6

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_send_start_mode/cnt_15_s0
To	u_send_start_mode/cnt_15_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C15[1][A]	u_send_start_mode/cnt_15_s0/CLK
1.062	0.202	tC2Q	RR	3	R25C15[1][A]	u_send_start_mode/cnt_15_s0/Q
1.064	0.002	tNET	RR	1	R25C15[1][A]	u_send_start_mode/n40_s3/I0
1.296	0.232	tINS	RF	1	R25C15[1][A]	u_send_start_mode/n40_s3/F
1.296	0.000	tNET	FF	1	R25C15[1][A]	u_send_start_mode/cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C15[1][A]	u_send_start_mode/cnt_15_s0/CLK
0.871	0.011	tHld		1	R25C15[1][A]	u_send_start_mode/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_send_start_mode/cnt_16_s0
To	u_send_start_mode/cnt_16_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C15[1][A]	u_send_start_mode/cnt_16_s0/CLK
1.062	0.202	tC2Q	RR	4	R26C15[1][A]	u_send_start_mode/cnt_16_s0/Q
1.064	0.002	tNET	RR	1	R26C15[1][A]	u_send_start_mode/n39_s4/I0
1.296	0.232	tINS	RF	1	R26C15[1][A]	u_send_start_mode/n39_s4/F
1.296	0.000	tNET	FF	1	R26C15[1][A]	u_send_start_mode/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C15[1][A]	u_send_start_mode/cnt_16_s0/CLK
0.871	0.011	tHld		1	R26C15[1][A]	u_send_start_mode/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_send_start_mode/cnt_17_s0
To	u_send_start_mode/cnt_17_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C15[1][A]	u_send_start_mode/cnt_17_s0/CLK
1.062	0.202	tC2Q	RR	3	R30C15[1][A]	u_send_start_mode/cnt_17_s0/Q
1.064	0.002	tNET	RR	1	R30C15[1][A]	u_send_start_mode/n38_s1/I2
1.296	0.232	tINS	RF	1	R30C15[1][A]	u_send_start_mode/n38_s1/F
1.296	0.000	tNET	FF	1	R30C15[1][A]	u_send_start_mode/cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C15[1][A]	u_send_start_mode/cnt_17_s0/CLK
0.871	0.011	tHld		1	R30C15[1][A]	u_send_start_mode/cnt_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_set_tx_start/cnt_2_s0
To	u_set_tx_start/cnt_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R35C28[1][A]	u_set_tx_start/cnt_2_s0/CLK
1.062	0.202	tC2Q	RR	4	R35C28[1][A]	u_set_tx_start/cnt_2_s0/Q
1.064	0.002	tNET	RR	1	R35C28[1][A]	u_set_tx_start/n53_s1/I2
1.296	0.232	tINS	RF	1	R35C28[1][A]	u_set_tx_start/n53_s1/F
1.296	0.000	tNET	FF	1	R35C28[1][A]	u_set_tx_start/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R35C28[1][A]	u_set_tx_start/cnt_2_s0/CLK
0.871	0.011	tHld		1	R35C28[1][A]	u_set_tx_start/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_set_tx_start/cnt_14_s0
To	u_set_tx_start/cnt_14_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C28[0][A]	u_set_tx_start/cnt_14_s0/CLK
1.062	0.202	tC2Q	RR	3	R34C28[0][A]	u_set_tx_start/cnt_14_s0/Q
1.064	0.002	tNET	RR	1	R34C28[0][A]	u_set_tx_start/n41_s1/I2
1.296	0.232	tINS	RF	1	R34C28[0][A]	u_set_tx_start/n41_s1/F
1.296	0.000	tNET	FF	1	R34C28[0][A]	u_set_tx_start/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C28[0][A]	u_set_tx_start/cnt_14_s0/CLK
0.871	0.011	tHld		1	R34C28[0][A]	u_set_tx_start/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_set_rx_reset/cnt_0_s0
To	u_set_rx_reset/cnt_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R40C40[0][A]	u_set_rx_reset/cnt_0_s0/CLK
1.062	0.202	tC2Q	RR	6	R40C40[0][A]	u_set_rx_reset/cnt_0_s0/Q
1.064	0.002	tNET	RR	1	R40C40[0][A]	u_set_rx_reset/n55_s3/I0
1.296	0.232	tINS	RF	1	R40C40[0][A]	u_set_rx_reset/n55_s3/F
1.296	0.000	tNET	FF	1	R40C40[0][A]	u_set_rx_reset/cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R40C40[0][A]	u_set_rx_reset/cnt_0_s0/CLK
0.871	0.011	tHld		1	R40C40[0][A]	u_set_rx_reset/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_set_phyic_mode/cnt_1_s0
To	u_set_phyic_mode/cnt_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[1][A]	u_set_phyic_mode/cnt_1_s0/CLK
1.062	0.202	tC2Q	RR	5	R30C25[1][A]	u_set_phyic_mode/cnt_1_s0/Q
1.064	0.002	tNET	RR	1	R30C25[1][A]	u_set_phyic_mode/n54_s2/I1
1.296	0.232	tINS	RF	1	R30C25[1][A]	u_set_phyic_mode/n54_s2/F
1.296	0.000	tNET	FF	1	R30C25[1][A]	u_set_phyic_mode/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[1][A]	u_set_phyic_mode/cnt_1_s0/CLK
0.871	0.011	tHld		1	R30C25[1][A]	u_set_phyic_mode/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_set_phyic_mode/cnt_10_s0
To	u_set_phyic_mode/cnt_10_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C28[1][A]	u_set_phyic_mode/cnt_10_s0/CLK
1.062	0.202	tC2Q	RR	4	R30C28[1][A]	u_set_phyic_mode/cnt_10_s0/Q
1.064	0.002	tNET	RR	1	R30C28[1][A]	u_set_phyic_mode/n45_s1/I2
1.296	0.232	tINS	RF	1	R30C28[1][A]	u_set_phyic_mode/n45_s1/F
1.296	0.000	tNET	FF	1	R30C28[1][A]	u_set_phyic_mode/cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C28[1][A]	u_set_phyic_mode/cnt_10_s0/CLK
0.871	0.011	tHld		1	R30C28[1][A]	u_set_phyic_mode/cnt_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_set_phyic_mode/cnt_14_s0
To	u_set_phyic_mode/cnt_14_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C28[0][A]	u_set_phyic_mode/cnt_14_s0/CLK
1.062	0.202	tC2Q	RR	4	R31C28[0][A]	u_set_phyic_mode/cnt_14_s0/Q
1.064	0.002	tNET	RR	1	R31C28[0][A]	u_set_phyic_mode/n41_s1/I2
1.296	0.232	tINS	RF	1	R31C28[0][A]	u_set_phyic_mode/n41_s1/F
1.296	0.000	tNET	FF	1	R31C28[0][A]	u_set_phyic_mode/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C28[0][A]	u_set_phyic_mode/cnt_14_s0/CLK
0.871	0.011	tHld		1	R31C28[0][A]	u_set_phyic_mode/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_duplex_status/cnt_10_s0
To	u_duplex_status/cnt_10_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C23[0][A]	u_duplex_status/cnt_10_s0/CLK
1.062	0.202	tC2Q	RR	4	R30C23[0][A]	u_duplex_status/cnt_10_s0/Q
1.064	0.002	tNET	RR	1	R30C23[0][A]	u_duplex_status/n45_s1/I2
1.296	0.232	tINS	RF	1	R30C23[0][A]	u_duplex_status/n45_s1/F
1.296	0.000	tNET	FF	1	R30C23[0][A]	u_duplex_status/cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C23[0][A]	u_duplex_status/cnt_10_s0/CLK
0.871	0.011	tHld		1	R30C23[0][A]	u_duplex_status/cnt_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_speedis10/cnt_15_s0
To	u_speedis10/cnt_15_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C17[0][A]	u_speedis10/cnt_15_s0/CLK
1.062	0.202	tC2Q	RR	3	R25C17[0][A]	u_speedis10/cnt_15_s0/Q
1.064	0.002	tNET	RR	1	R25C17[0][A]	u_speedis10/n40_s1/I1
1.296	0.232	tINS	RF	1	R25C17[0][A]	u_speedis10/n40_s1/F
1.296	0.000	tNET	FF	1	R25C17[0][A]	u_speedis10/cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C17[0][A]	u_speedis10/cnt_15_s0/CLK
0.871	0.011	tHld		1	R25C17[0][A]	u_speedis10/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_speedis10/cnt_16_s0
To	u_speedis10/cnt_16_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C16[1][A]	u_speedis10/cnt_16_s0/CLK
1.062	0.202	tC2Q	RR	4	R27C16[1][A]	u_speedis10/cnt_16_s0/Q
1.064	0.002	tNET	RR	1	R27C16[1][A]	u_speedis10/n39_s4/I0
1.296	0.232	tINS	RF	1	R27C16[1][A]	u_speedis10/n39_s4/F
1.296	0.000	tNET	FF	1	R27C16[1][A]	u_speedis10/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C16[1][A]	u_speedis10/cnt_16_s0/CLK
0.871	0.011	tHld		1	R27C16[1][A]	u_speedis10/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_speedis1000/cnt_6_s0
To	u_speedis1000/cnt_6_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C17[0][A]	u_speedis1000/cnt_6_s0/CLK
1.062	0.202	tC2Q	RR	3	R30C17[0][A]	u_speedis1000/cnt_6_s0/Q
1.064	0.002	tNET	RR	1	R30C17[0][A]	u_speedis1000/n49_s1/I2
1.296	0.232	tINS	RF	1	R30C17[0][A]	u_speedis1000/n49_s1/F
1.296	0.000	tNET	FF	1	R30C17[0][A]	u_speedis1000/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C17[0][A]	u_speedis1000/cnt_6_s0/CLK
0.871	0.011	tHld		1	R30C17[0][A]	u_speedis1000/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_speedis1000/cnt_18_s0
To	u_speedis1000/cnt_18_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C19[1][A]	u_speedis1000/cnt_18_s0/CLK
1.062	0.202	tC2Q	RR	2	R30C19[1][A]	u_speedis1000/cnt_18_s0/Q
1.064	0.002	tNET	RR	1	R30C19[1][A]	u_speedis1000/n37_s1/I2
1.296	0.232	tINS	RF	1	R30C19[1][A]	u_speedis1000/n37_s1/F
1.296	0.000	tNET	FF	1	R30C19[1][A]	u_speedis1000/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C19[1][A]	u_speedis1000/cnt_18_s0/CLK
0.871	0.011	tHld		1	R30C19[1][A]	u_speedis1000/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_miim_ctrl/op_cnt_6_s0
To	u_miim_ctrl/op_cnt_6_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C20[0][A]	u_miim_ctrl/op_cnt_6_s0/CLK
1.062	0.202	tC2Q	RR	2	R25C20[0][A]	u_miim_ctrl/op_cnt_6_s0/Q
1.064	0.002	tNET	RR	2	R25C20[0][A]	u_miim_ctrl/n507_s/I1
1.296	0.232	tINS	RF	1	R25C20[0][A]	u_miim_ctrl/n507_s/SUM
1.296	0.000	tNET	FF	1	R25C20[0][A]	u_miim_ctrl/op_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C20[0][A]	u_miim_ctrl/op_cnt_6_s0/CLK
0.871	0.011	tHld		1	R25C20[0][A]	u_miim_ctrl/op_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_miim_ctrl/start_cnt_2_s0
To	u_miim_ctrl/start_cnt_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[1][A]	u_miim_ctrl/start_cnt_2_s0/CLK
1.062	0.202	tC2Q	RR	2	R25C21[1][A]	u_miim_ctrl/start_cnt_2_s0/Q
1.064	0.002	tNET	RR	2	R25C21[1][A]	u_miim_ctrl/n381_s/I1
1.296	0.232	tINS	RF	1	R25C21[1][A]	u_miim_ctrl/n381_s/SUM
1.296	0.000	tNET	FF	1	R25C21[1][A]	u_miim_ctrl/start_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[1][A]	u_miim_ctrl/start_cnt_2_s0/CLK
0.871	0.011	tHld		1	R25C21[1][A]	u_miim_ctrl/start_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	u_miim_ctrl/start_cnt_6_s0
To	u_miim_ctrl/start_cnt_6_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C22[0][A]	u_miim_ctrl/start_cnt_6_s0/CLK
1.062	0.202	tC2Q	RR	2	R25C22[0][A]	u_miim_ctrl/start_cnt_6_s0/Q
1.064	0.002	tNET	RR	2	R25C22[0][A]	u_miim_ctrl/n377_s/I1
1.296	0.232	tINS	RF	1	R25C22[0][A]	u_miim_ctrl/n377_s/SUM
1.296	0.000	tNET	FF	1	R25C22[0][A]	u_miim_ctrl/start_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C22[0][A]	u_miim_ctrl/start_cnt_6_s0/CLK
0.871	0.011	tHld		1	R25C22[0][A]	u_miim_ctrl/start_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	0.425
Data Arrival Time	1.705
Data Required Time	1.279
From	u_user_mac_rx_ctrl/frm_cnt_2_s0
To	u_user_mac_rx_ctrl/frm_cnt_2_s0
Launch Clk	rgmii_rxc1:[R]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R17C41[1][A]	u_user_mac_rx_ctrl/frm_cnt_2_s0/CLK
1.470	0.202	tC2Q	RR	2	R17C41[1][A]	u_user_mac_rx_ctrl/frm_cnt_2_s0/Q
1.473	0.002	tNET	RR	2	R17C41[1][A]	u_user_mac_rx_ctrl/n45_s/I1
1.705	0.232	tINS	RF	1	R17C41[1][A]	u_user_mac_rx_ctrl/n45_s/SUM
1.705	0.000	tNET	FF	1	R17C41[1][A]	u_user_mac_rx_ctrl/frm_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R17C41[1][A]	u_user_mac_rx_ctrl/frm_cnt_2_s0/CLK
1.279	0.011	tHld		1	R17C41[1][A]	u_user_mac_rx_ctrl/frm_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%

Path24

Path Summary:

Slack	0.425
Data Arrival Time	1.705
Data Required Time	1.279
From	u_user_mac_rx_ctrl/frm_cnt_6_s0
To	u_user_mac_rx_ctrl/frm_cnt_6_s0
Launch Clk	rgmii_rxc1:[R]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R17C42[0][A]	u_user_mac_rx_ctrl/frm_cnt_6_s0/CLK
1.470	0.202	tC2Q	RR	2	R17C42[0][A]	u_user_mac_rx_ctrl/frm_cnt_6_s0/Q
1.473	0.002	tNET	RR	2	R17C42[0][A]	u_user_mac_rx_ctrl/n41_s/I1
1.705	0.232	tINS	RF	1	R17C42[0][A]	u_user_mac_rx_ctrl/n41_s/SUM
1.705	0.000	tNET	FF	1	R17C42[0][A]	u_user_mac_rx_ctrl/frm_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R17C42[0][A]	u_user_mac_rx_ctrl/frm_cnt_6_s0/CLK
1.279	0.011	tHld		1	R17C42[0][A]	u_user_mac_rx_ctrl/frm_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%

Path25

Path Summary:

Slack	0.425
Data Arrival Time	1.705
Data Required Time	1.279
From	dut/u_triple_speed_mac/u_mac_rx_ctrl/vlan_reg_Z[7]
To	dut/u_triple_speed_mac/u_mac_rx_ctrl/vlan_reg_Z[7]
Launch Clk	rgmii_rxc1:[R]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R22C31[0][A]	dut/u_triple_speed_mac/u_mac_rx_ctrl/vlan_reg_Z[7]/CLK
1.470	0.202	tC2Q	RR	2	R22C31[0][A]	dut/u_triple_speed_mac/u_mac_rx_ctrl/vlan_reg_Z[7]/Q
1.473	0.002	tNET	RR	1	R22C31[0][A]	dut/u_triple_speed_mac/u_mac_rx_ctrl/u_crc_chk/vlan_reg_6_cZ[7]/I3
1.705	0.232	tINS	RF	1	R22C31[0][A]	dut/u_triple_speed_mac/u_mac_rx_ctrl/u_crc_chk/vlan_reg_6_cZ[7]/F
1.705	0.000	tNET	FF	1	R22C31[0][A]	dut/u_triple_speed_mac/u_mac_rx_ctrl/vlan_reg_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgmii_rxc1
0.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
0.675	0.675	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
1.268	0.593	tNET	RR	1	R22C31[0][A]	dut/u_triple_speed_mac/u_mac_rx_ctrl/vlan_reg_Z[7]/CLK
1.279	0.011	tHld		1	R22C31[0][A]	dut/u_triple_speed_mac/u_mac_rx_ctrl/vlan_reg_Z[7]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 53.267%; route: 0.593, 46.733%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.950
Data Arrival Time	7.511
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.511	1.652	tNET	FF	1	R16C18[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R16C18[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
9.461	-0.035	tSu		1	R16C18[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.652, 87.685%; tC2Q: 0.232, 12.315%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path2

Path Summary:

Slack	1.950
Data Arrival Time	7.511
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.511	1.652	tNET	FF	1	R16C18[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R16C18[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
9.461	-0.035	tSu		1	R16C18[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.652, 87.685%; tC2Q: 0.232, 12.315%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path3

Path Summary:

Slack	1.950
Data Arrival Time	7.511
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.511	1.652	tNET	FF	1	R16C18[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R16C18[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
9.461	-0.035	tSu		1	R16C18[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.652, 87.685%; tC2Q: 0.232, 12.315%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path4

Path Summary:

Slack	1.950
Data Arrival Time	7.511
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.511	1.652	tNET	FF	1	R16C18[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R16C18[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
9.461	-0.035	tSu		1	R16C18[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.652, 87.685%; tC2Q: 0.232, 12.315%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path5

Path Summary:

Slack	2.064
Data Arrival Time	7.398
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.398	1.538	tNET	FF	1	R16C17[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R16C17[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
9.461	-0.035	tSu		1	R16C17[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.538, 86.894%; tC2Q: 0.232, 13.106%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path6

Path Summary:

Slack	2.064
Data Arrival Time	7.398
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.398	1.538	tNET	FF	1	R16C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R16C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
9.461	-0.035	tSu		1	R16C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.538, 86.894%; tC2Q: 0.232, 13.106%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path7

Path Summary:

Slack	2.064
Data Arrival Time	7.398
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.398	1.538	tNET	FF	1	R16C17[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R16C17[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
9.461	-0.035	tSu		1	R16C17[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.538, 86.894%; tC2Q: 0.232, 13.106%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path8

Path Summary:

Slack	2.072
Data Arrival Time	7.390
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.390	1.530	tNET	FF	1	R17C17[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R17C17[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
9.461	-0.035	tSu		1	R17C17[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.530, 86.836%; tC2Q: 0.232, 13.164%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path9

Path Summary:

Slack	2.204
Data Arrival Time	7.257
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.257	1.398	tNET	FF	1	R18C18[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C18[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
9.461	-0.035	tSu		1	R18C18[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.398, 85.764%; tC2Q: 0.232, 14.236%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path10

Path Summary:

Slack	2.204
Data Arrival Time	7.257
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.257	1.398	tNET	FF	1	R18C18[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C18[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
9.461	-0.035	tSu		1	R18C18[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.398, 85.764%; tC2Q: 0.232, 14.236%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path11

Path Summary:

Slack	2.204
Data Arrival Time	7.257
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.257	1.398	tNET	FF	1	R18C18[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C18[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
9.461	-0.035	tSu		1	R18C18[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.398, 85.764%; tC2Q: 0.232, 14.236%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path12

Path Summary:

Slack	2.204
Data Arrival Time	7.257
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.257	1.398	tNET	FF	1	R18C18[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C18[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
9.461	-0.035	tSu		1	R18C18[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.398, 85.764%; tC2Q: 0.232, 14.236%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path13

Path Summary:

Slack	2.204
Data Arrival Time	7.257
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.257	1.398	tNET	FF	1	R18C18[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C18[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
9.461	-0.035	tSu		1	R18C18[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.398, 85.764%; tC2Q: 0.232, 14.236%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path14

Path Summary:

Slack	2.299
Data Arrival Time	7.163
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.163	1.303	tNET	FF	1	R18C17[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C17[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
9.461	-0.035	tSu		1	R18C17[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.303, 84.889%; tC2Q: 0.232, 15.111%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path15

Path Summary:

Slack	2.299
Data Arrival Time	7.163
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.163	1.303	tNET	FF	1	R18C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
9.461	-0.035	tSu		1	R18C17[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.303, 84.889%; tC2Q: 0.232, 15.111%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path16

Path Summary:

Slack	2.299
Data Arrival Time	7.163
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.163	1.303	tNET	FF	1	R18C17[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C17[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
9.461	-0.035	tSu		1	R18C17[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.303, 84.889%; tC2Q: 0.232, 15.111%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path17

Path Summary:

Slack	2.553
Data Arrival Time	6.909
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.909	1.049	tNET	FF	1	R16C16[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R16C16[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
9.461	-0.035	tSu		1	R16C16[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.049, 81.891%; tC2Q: 0.232, 18.109%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path18

Path Summary:

Slack	2.553
Data Arrival Time	6.909
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.909	1.049	tNET	FF	1	R16C16[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R16C16[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
9.461	-0.035	tSu		1	R16C16[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.049, 81.891%; tC2Q: 0.232, 18.109%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path19

Path Summary:

Slack	2.553
Data Arrival Time	6.909
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.909	1.049	tNET	FF	1	R18C16[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C16[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
9.461	-0.035	tSu		1	R18C16[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.049, 81.891%; tC2Q: 0.232, 18.109%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path20

Path Summary:

Slack	2.553
Data Arrival Time	6.909
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.909	1.049	tNET	FF	1	R18C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
9.461	-0.035	tSu		1	R18C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.049, 81.891%; tC2Q: 0.232, 18.109%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path21

Path Summary:

Slack	2.553
Data Arrival Time	6.909
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.909	1.049	tNET	FF	1	R18C16[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C16[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
9.461	-0.035	tSu		1	R18C16[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.049, 81.891%; tC2Q: 0.232, 18.109%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path22

Path Summary:

Slack	2.553
Data Arrival Time	6.909
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.909	1.049	tNET	FF	1	R16C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R16C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
9.461	-0.035	tSu		1	R16C16[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.049, 81.891%; tC2Q: 0.232, 18.109%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path23

Path Summary:

Slack	2.553
Data Arrival Time	6.909
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.909	1.049	tNET	FF	1	R18C15[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C15[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
9.461	-0.035	tSu		1	R18C15[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.049, 81.891%; tC2Q: 0.232, 18.109%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path24

Path Summary:

Slack	2.553
Data Arrival Time	6.909
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.909	1.049	tNET	FF	1	R18C15[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R18C15[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
9.461	-0.035	tSu		1	R18C15[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.049, 81.891%; tC2Q: 0.232, 18.109%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Path25

Path Summary:

Slack	2.553
Data Arrival Time	6.909
Data Required Time	9.461
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	rgmii_rxc1:[F]
Latch Clk	rgmii_rxc1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					rgmii_rxc1
4.000	0.000	tCL	FF	1	IOR17[B]	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	460	IOR17[B]	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	1	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
5.859	0.232	tC2Q	FF	49	R15C22[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.909	1.049	tNET	FF	1	R17C15[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rgmii_rxc1
8.000	0.000	tCL	RR	1	IOR17[B]	rgmii_rxc_ibuf/I
8.682	0.683	tINS	RR	460	IOR17[B]	rgmii_rxc_ibuf/O
9.496	0.814	tNET	RR	1	R17C15[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
9.461	-0.035	tSu		1	R17C15[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.131
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 42.244%; route: 0.940, 57.756%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.049, 81.891%; tC2Q: 0.232, 18.109%
Required Clock Path Delay	cell: 0.683, 45.612%; route: 0.814, 54.388%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.158
Data Arrival Time	2.029
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_wrdata_5_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.029	0.275	tNET	RR	1	R29C20[0][A]	u_miim_ctrl/miim_wrdata_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C20[0][A]	u_miim_ctrl/miim_wrdata_5_s0/CLK
0.871	0.011	tHld		1	R29C20[0][A]	u_miim_ctrl/miim_wrdata_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 26.515%; route: 0.657, 56.207%; tC2Q: 0.202, 17.278%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	1.158
Data Arrival Time	2.029
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_wrdata_6_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.029	0.275	tNET	RR	1	R29C20[1][B]	u_miim_ctrl/miim_wrdata_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C20[1][B]	u_miim_ctrl/miim_wrdata_6_s0/CLK
0.871	0.011	tHld		1	R29C20[1][B]	u_miim_ctrl/miim_wrdata_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 26.515%; route: 0.657, 56.207%; tC2Q: 0.202, 17.278%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	1.158
Data Arrival Time	2.029
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_wrdata_7_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.029	0.275	tNET	RR	1	R29C20[1][A]	u_miim_ctrl/miim_wrdata_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C20[1][A]	u_miim_ctrl/miim_wrdata_7_s0/CLK
0.871	0.011	tHld		1	R29C20[1][A]	u_miim_ctrl/miim_wrdata_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 26.515%; route: 0.657, 56.207%; tC2Q: 0.202, 17.278%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	1.158
Data Arrival Time	2.029
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_wrdata_8_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.029	0.275	tNET	RR	1	R29C20[0][B]	u_miim_ctrl/miim_wrdata_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C20[0][B]	u_miim_ctrl/miim_wrdata_8_s0/CLK
0.871	0.011	tHld		1	R29C20[0][B]	u_miim_ctrl/miim_wrdata_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 26.515%; route: 0.657, 56.207%; tC2Q: 0.202, 17.278%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	1.265
Data Arrival Time	2.136
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/start_cnt_6_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.136	0.381	tNET	RR	1	R25C22[0][A]	u_miim_ctrl/start_cnt_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C22[0][A]	u_miim_ctrl/start_cnt_6_s0/CLK
0.871	0.011	tHld		1	R25C22[0][A]	u_miim_ctrl/start_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 24.299%; route: 0.764, 59.868%; tC2Q: 0.202, 15.833%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	1.265
Data Arrival Time	2.136
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/start_cnt_7_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.136	0.381	tNET	RR	1	R25C22[0][B]	u_miim_ctrl/start_cnt_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C22[0][B]	u_miim_ctrl/start_cnt_7_s0/CLK
0.871	0.011	tHld		1	R25C22[0][B]	u_miim_ctrl/start_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 24.299%; route: 0.764, 59.868%; tC2Q: 0.202, 15.833%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	1.270
Data Arrival Time	2.141
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/wrdata_reg_6_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.141	0.386	tNET	RR	1	R27C20[0][B]	u_miim_ctrl/wrdata_reg_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C20[0][B]	u_miim_ctrl/wrdata_reg_6_s0/CLK
0.871	0.011	tHld		1	R27C20[0][B]	u_miim_ctrl/wrdata_reg_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 24.205%; route: 0.769, 60.023%; tC2Q: 0.202, 15.772%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	1.270
Data Arrival Time	2.141
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/wrdata_reg_7_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.141	0.386	tNET	RR	1	R27C20[1][A]	u_miim_ctrl/wrdata_reg_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C20[1][A]	u_miim_ctrl/wrdata_reg_7_s0/CLK
0.871	0.011	tHld		1	R27C20[1][A]	u_miim_ctrl/wrdata_reg_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 24.205%; route: 0.769, 60.023%; tC2Q: 0.202, 15.772%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	1.270
Data Arrival Time	2.141
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/wrdata_reg_8_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.141	0.386	tNET	RR	1	R27C20[0][A]	u_miim_ctrl/wrdata_reg_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C20[0][A]	u_miim_ctrl/wrdata_reg_8_s0/CLK
0.871	0.011	tHld		1	R27C20[0][A]	u_miim_ctrl/wrdata_reg_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 24.205%; route: 0.769, 60.023%; tC2Q: 0.202, 15.772%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	1.270
Data Arrival Time	2.141
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/wrdata_reg_15_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.141	0.386	tNET	RR	1	R27C20[1][B]	u_miim_ctrl/wrdata_reg_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C20[1][B]	u_miim_ctrl/wrdata_reg_15_s0/CLK
0.871	0.011	tHld		1	R27C20[1][B]	u_miim_ctrl/wrdata_reg_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 24.205%; route: 0.769, 60.023%; tC2Q: 0.202, 15.772%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	1.277
Data Arrival Time	2.148
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/op_cnt_0_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.148	0.394	tNET	RR	1	R26C21[0][B]	u_miim_ctrl/op_cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C21[0][B]	u_miim_ctrl/op_cnt_0_s1/CLK
0.871	0.011	tHld		1	R26C21[0][B]	u_miim_ctrl/op_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 24.066%; route: 0.776, 60.253%; tC2Q: 0.202, 15.682%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	1.282
Data Arrival Time	2.153
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/start_cnt_0_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.153	0.399	tNET	RR	1	R26C20[1][B]	u_miim_ctrl/start_cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C20[1][B]	u_miim_ctrl/start_cnt_0_s1/CLK
0.871	0.011	tHld		1	R26C20[1][B]	u_miim_ctrl/start_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.976%; route: 0.781, 60.401%; tC2Q: 0.202, 15.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	1.282
Data Arrival Time	2.153
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_wrdata_15_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.153	0.399	tNET	RR	1	R26C20[0][A]	u_miim_ctrl/miim_wrdata_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C20[0][A]	u_miim_ctrl/miim_wrdata_15_s0/CLK
0.871	0.011	tHld		1	R26C20[0][A]	u_miim_ctrl/miim_wrdata_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.976%; route: 0.781, 60.401%; tC2Q: 0.202, 15.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	1.282
Data Arrival Time	2.153
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_phyad_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.153	0.399	tNET	RR	1	R26C20[0][B]	u_miim_ctrl/miim_phyad_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C20[0][B]	u_miim_ctrl/miim_phyad_0_s0/CLK
0.871	0.011	tHld		1	R26C20[0][B]	u_miim_ctrl/miim_phyad_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.976%; route: 0.781, 60.401%; tC2Q: 0.202, 15.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	1.282
Data Arrival Time	2.153
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_rden_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.153	0.399	tNET	RR	1	R26C20[2][A]	u_miim_ctrl/miim_rden_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C20[2][A]	u_miim_ctrl/miim_rden_s0/CLK
0.871	0.011	tHld		1	R26C20[2][A]	u_miim_ctrl/miim_rden_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.976%; route: 0.781, 60.401%; tC2Q: 0.202, 15.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	1.282
Data Arrival Time	2.153
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_wren_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.153	0.399	tNET	RR	1	R26C20[2][B]	u_miim_ctrl/miim_wren_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C20[2][B]	u_miim_ctrl/miim_wren_s0/CLK
0.871	0.011	tHld		1	R26C20[2][B]	u_miim_ctrl/miim_wren_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.976%; route: 0.781, 60.401%; tC2Q: 0.202, 15.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	1.282
Data Arrival Time	2.153
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/start_flag_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.153	0.399	tNET	RR	1	R26C20[1][A]	u_miim_ctrl/start_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C20[1][A]	u_miim_ctrl/start_flag_s0/CLK
0.871	0.011	tHld		1	R26C20[1][A]	u_miim_ctrl/start_flag_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.976%; route: 0.781, 60.401%; tC2Q: 0.202, 15.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	1.283
Data Arrival Time	2.154
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/start_cnt_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.154	0.400	tNET	RR	1	R25C21[0][B]	u_miim_ctrl/start_cnt_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[0][B]	u_miim_ctrl/start_cnt_1_s0/CLK
0.871	0.011	tHld		1	R25C21[0][B]	u_miim_ctrl/start_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.954%; route: 0.782, 60.437%; tC2Q: 0.202, 15.609%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	1.283
Data Arrival Time	2.154
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/start_cnt_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.154	0.400	tNET	RR	1	R25C21[1][A]	u_miim_ctrl/start_cnt_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[1][A]	u_miim_ctrl/start_cnt_2_s0/CLK
0.871	0.011	tHld		1	R25C21[1][A]	u_miim_ctrl/start_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.954%; route: 0.782, 60.437%; tC2Q: 0.202, 15.609%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	1.283
Data Arrival Time	2.154
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/start_cnt_3_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.154	0.400	tNET	RR	1	R25C21[1][B]	u_miim_ctrl/start_cnt_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[1][B]	u_miim_ctrl/start_cnt_3_s0/CLK
0.871	0.011	tHld		1	R25C21[1][B]	u_miim_ctrl/start_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.954%; route: 0.782, 60.437%; tC2Q: 0.202, 15.609%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	1.283
Data Arrival Time	2.154
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/start_cnt_4_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.154	0.400	tNET	RR	1	R25C21[2][A]	u_miim_ctrl/start_cnt_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[2][A]	u_miim_ctrl/start_cnt_4_s0/CLK
0.871	0.011	tHld		1	R25C21[2][A]	u_miim_ctrl/start_cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.954%; route: 0.782, 60.437%; tC2Q: 0.202, 15.609%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	1.283
Data Arrival Time	2.154
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/start_cnt_5_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.154	0.400	tNET	RR	1	R25C21[2][B]	u_miim_ctrl/start_cnt_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[2][B]	u_miim_ctrl/start_cnt_5_s0/CLK
0.871	0.011	tHld		1	R25C21[2][B]	u_miim_ctrl/start_cnt_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.954%; route: 0.782, 60.437%; tC2Q: 0.202, 15.609%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	1.286
Data Arrival Time	2.157
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_wrdata_9_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.157	0.403	tNET	RR	1	R27C19[1][B]	u_miim_ctrl/miim_wrdata_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C19[1][B]	u_miim_ctrl/miim_wrdata_9_s0/CLK
0.871	0.011	tHld		1	R27C19[1][B]	u_miim_ctrl/miim_wrdata_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.899%; route: 0.785, 60.529%; tC2Q: 0.202, 15.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	1.286
Data Arrival Time	2.157
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_regad_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.157	0.403	tNET	RR	1	R27C19[1][A]	u_miim_ctrl/miim_regad_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C19[1][A]	u_miim_ctrl/miim_regad_0_s0/CLK
0.871	0.011	tHld		1	R27C19[1][A]	u_miim_ctrl/miim_regad_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.899%; route: 0.785, 60.529%; tC2Q: 0.202, 15.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	1.286
Data Arrival Time	2.157
Data Required Time	0.871
From	u_set_phyic_mode/out_s0
To	u_miim_ctrl/miim_regad_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/CLK
1.062	0.202	tC2Q	RR	1	R30C25[0][A]	u_set_phyic_mode/out_s0/Q
1.444	0.382	tNET	RR	1	R29C22[0][A]	u_miim_ctrl/n6_s1/I1
1.754	0.310	tINS	RR	53	R29C22[0][A]	u_miim_ctrl/n6_s1/F
2.157	0.403	tNET	RR	1	R27C19[0][A]	u_miim_ctrl/miim_regad_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	293	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C19[0][A]	u_miim_ctrl/miim_regad_1_s0/CLK
0.871	0.011	tHld		1	R27C19[0][A]	u_miim_ctrl/miim_regad_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.310, 23.899%; route: 0.785, 60.529%; tC2Q: 0.202, 15.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.641
Actual Width:	3.641
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rgmii_rxc1
Objects:	gao_rx_frm_byte_cnt_15_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rgmii_rxc1
4.000	0.000	tCL	FF	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	gao_rx_frm_byte_cnt_15_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rgmii_rxc1
8.000	0.000	tCL	RR	rgmii_rxc_ibuf/I
8.675	0.675	tINS	RR	rgmii_rxc_ibuf/O
9.268	0.593	tNET	RR	gao_rx_frm_byte_cnt_15_s0/CLK

MPW2

MPW Summary:

Slack:	2.641
Actual Width:	3.641
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rgmii_rxc1
Objects:	dut/u_triple_speed_mac/u_mac_rx_if_block/u_mac_rx_if_mux/gmii_rxd_int_Z[1]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rgmii_rxc1
4.000	0.000	tCL	FF	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	dut/u_triple_speed_mac/u_mac_rx_if_block/u_mac_rx_if_mux/gmii_rxd_int_Z[1]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rgmii_rxc1
8.000	0.000	tCL	RR	rgmii_rxc_ibuf/I
8.675	0.675	tINS	RR	rgmii_rxc_ibuf/O
9.268	0.593	tNET	RR	dut/u_triple_speed_mac/u_mac_rx_if_block/u_mac_rx_if_mux/gmii_rxd_int_Z[1]/CLK

MPW3

MPW Summary:

Slack:	2.641
Actual Width:	3.641
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rgmii_rxc1
Objects:	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_statistics_valid_o_tmp_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rgmii_rxc1
4.000	0.000	tCL	FF	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_statistics_valid_o_tmp_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rgmii_rxc1
8.000	0.000	tCL	RR	rgmii_rxc_ibuf/I
8.675	0.675	tINS	RR	rgmii_rxc_ibuf/O
9.268	0.593	tNET	RR	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_statistics_valid_o_tmp_Z/CLK

MPW4

MPW Summary:

Slack:	2.641
Actual Width:	3.641
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rgmii_rxc1
Objects:	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_dv_reg_Z[0]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rgmii_rxc1
4.000	0.000	tCL	FF	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_dv_reg_Z[0]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rgmii_rxc1
8.000	0.000	tCL	RR	rgmii_rxc_ibuf/I
8.675	0.675	tINS	RR	rgmii_rxc_ibuf/O
9.268	0.593	tNET	RR	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_dv_reg_Z[0]/CLK

MPW5

MPW Summary:

Slack:	2.641
Actual Width:	3.641
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rgmii_rxc1
Objects:	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_er_reg_Z[6]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rgmii_rxc1
4.000	0.000	tCL	FF	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_er_reg_Z[6]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rgmii_rxc1
8.000	0.000	tCL	RR	rgmii_rxc_ibuf/I
8.675	0.675	tINS	RR	rgmii_rxc_ibuf/O
9.268	0.593	tNET	RR	dut/u_triple_speed_mac/u_mac_rx_ctrl/rx_er_reg_Z[6]/CLK

MPW6

MPW Summary:

Slack:	2.641
Actual Width:	3.641
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rgmii_rxc1
Objects:	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[20]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rgmii_rxc1
4.000	0.000	tCL	FF	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[20]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rgmii_rxc1
8.000	0.000	tCL	RR	rgmii_rxc_ibuf/I
8.675	0.675	tINS	RR	rgmii_rxc_ibuf/O
9.268	0.593	tNET	RR	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[20]/CLK

MPW7

MPW Summary:

Slack:	2.641
Actual Width:	3.641
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rgmii_rxc1
Objects:	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[16]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rgmii_rxc1
4.000	0.000	tCL	FF	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[16]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rgmii_rxc1
8.000	0.000	tCL	RR	rgmii_rxc_ibuf/I
8.675	0.675	tINS	RR	rgmii_rxc_ibuf/O
9.268	0.593	tNET	RR	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[16]/CLK

MPW8

MPW Summary:

Slack:	2.641
Actual Width:	3.641
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rgmii_rxc1
Objects:	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[14]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rgmii_rxc1
4.000	0.000	tCL	FF	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[14]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rgmii_rxc1
8.000	0.000	tCL	RR	rgmii_rxc_ibuf/I
8.675	0.675	tINS	RR	rgmii_rxc_ibuf/O
9.268	0.593	tNET	RR	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[14]/CLK

MPW9

MPW Summary:

Slack:	2.641
Actual Width:	3.641
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rgmii_rxc1
Objects:	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[13]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rgmii_rxc1
4.000	0.000	tCL	FF	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[13]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rgmii_rxc1
8.000	0.000	tCL	RR	rgmii_rxc_ibuf/I
8.675	0.675	tINS	RR	rgmii_rxc_ibuf/O
9.268	0.593	tNET	RR	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[13]/CLK

MPW10

MPW Summary:

Slack:	2.641
Actual Width:	3.641
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rgmii_rxc1
Objects:	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[15]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rgmii_rxc1
4.000	0.000	tCL	FF	rgmii_rxc_ibuf/I
4.688	0.688	tINS	FF	rgmii_rxc_ibuf/O
5.627	0.940	tNET	FF	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[15]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rgmii_rxc1
8.000	0.000	tCL	RR	rgmii_rxc_ibuf/I
8.675	0.675	tINS	RR	rgmii_rxc_ibuf/O
9.268	0.593	tNET	RR	dut/u_triple_speed_mac/u_mac_rx_ctrl/rxd_reg_Z[15]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
645	tx_mac_clk	0.053	0.261
460	rx_mac_clk_d	1.950	1.106
293	clk_d	14.982	0.261
208	control0[0]	7.760	0.912
128	n1073_6	2.548	2.142
79	hd_state_enable	5.152	1.464
69	speedis1000_reg3	5.530	1.496
64	tx_pause_source_addr_latch_1_sqmuxa_i	5.219	1.566
56	shift_reg_63_8	2.256	0.946
53	n6_5	17.649	0.977

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C5	100.00%
R2C7	100.00%
R2C8	100.00%
R2C24	100.00%
R3C2	100.00%
R4C12	100.00%
R6C32	100.00%
R11C52	100.00%
R21C43	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name rgmii_rxc1 -period 8 -waveform {0 4} [get_ports {rgmii_rxc}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 20 -waveform {0 10} [get_ports {tck_pad_i}]
TC_CLOCK	Actived	create_clock -name clkin -period 20 -waveform {0 10} [get_ports {clk}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name gtx_clk -source [get_ports {clk}] -master_clock clkin -divide_by 2 -multiply_by 5 [get_pins {u_GW_PLL/pll_inst/CLKOUT}]
TC_CLOCK_GROUP	Actived	set_clock_groups -exclusive -group [get_clocks {clkin}] -group [get_clocks {rgmii_rxc1}] -group [get_clocks {gtx_clk}] -group [get_clocks {tck_pad_i}]