Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\src\top.v E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\src\user_mac_tx_ctrl.v E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\src\gw_pll\gw_pll.v E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\src\miim_ctrl.v E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\src\button.v E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\src\user_mac_rx_ctrl.v E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\src\gw_rom\data_rom.v E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\src\triple_speed_ethernet_mac\triple_speed_ethernet_mac.v D:\Gowin\Gowin_V1.9.8.05\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Gowin\Gowin_V1.9.8.05\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Gowin\Gowin_V1.9.8.05\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Gowin\Gowin_V1.9.8.05\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Gowin\Gowin_V1.9.8.05\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\Gowin\Gowin_V1.9.8.05\IDE\data\ipcores\gw_jtag.v E:\work\2022\9_Triple_Speed_Ethernet_MAC_RefDesign\Gowin_Triple_Speed_Ethernet_MAC_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.05 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Mon Mar 21 09:36:53 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.921s, Elapsed time = 0h 0m 1s, Peak memory usage = 345.016MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 345.016MB Optimizing Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 345.016MB Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 345.016MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 345.016MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 345.016MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 345.016MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 345.016MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.182s, Peak memory usage = 345.016MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 345.016MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 345.016MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 345.016MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 345.016MB Generate output files: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.17s, Peak memory usage = 345.016MB |
| Total Time and Memory Usage | CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 345.016MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 49 |
| I/O Buf | 49 |
| IBUF | 18 |
| OBUF | 24 |
| TBUF | 6 |
| IOBUF | 1 |
| Register | 1573 |
| DFF | 37 |
| DFFP | 6 |
| DFFPE | 105 |
| DFFC | 645 |
| DFFCE | 774 |
| DFFNP | 2 |
| DFFNC | 4 |
| LUT | 2114 |
| LUT2 | 449 |
| LUT3 | 512 |
| LUT4 | 1153 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 170 |
| ALU | 170 |
| SSRAM | 2 |
| RAM16S4 | 2 |
| INV | 14 |
| INV | 14 |
| IOLOGIC | 16 |
| IDDR | 5 |
| ODDR | 6 |
| IODELAY | 5 |
| BSRAM | 7 |
| ROM | 6 |
| SDPB | 1 |
| CLOCK | 1 |
| PLL | 1 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2318(2136 LUTs, 170 ALUs, 2 SSRAMs) / 20736 | 11% |
| Register | 1573 / 16173 | 10% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 1573 / 16173 | 10% |
| BSRAM | 7 / 46 | 15% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
| rgmii_rxc | Base | 10.000 | 100.0 | 0.000 | 5.000 | rgmii_rxc_ibuf/I | ||
| u_GW_PLL/pll_inst/CLKOUT.default_gen_clk | Generated | 8.000 | 125.0 | 0.000 | 4.000 | clk_ibuf/I | clk | u_GW_PLL/pll_inst/CLKOUT |
| u_GW_PLL/pll_inst/CLKOUTP.default_gen_clk | Generated | 8.000 | 125.0 | 0.000 | 4.000 | clk_ibuf/I | clk | u_GW_PLL/pll_inst/CLKOUTP |
| u_GW_PLL/pll_inst/CLKOUTD.default_gen_clk | Generated | 16.000 | 62.5 | 0.000 | 8.000 | clk_ibuf/I | clk | u_GW_PLL/pll_inst/CLKOUTD |
| u_GW_PLL/pll_inst/CLKOUTD3.default_gen_clk | Generated | 24.000 | 41.7 | 0.000 | 12.000 | clk_ibuf/I | clk | u_GW_PLL/pll_inst/CLKOUTD3 |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.0(MHz) | 245.3(MHz) | 6 | TOP |
| 2 | rgmii_rxc | 100.0(MHz) | 241.1(MHz) | 5 | TOP |
| 3 | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk | 125.0(MHz) | 169.3(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.016 |
| Data Arrival Time | 32.124 |
| Data Required Time | 33.139 |
| From | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/gmii_rx_er_o |
| To | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_col_reg1_Z |
| Launch Clk | rgmii_rxc[R] |
| Latch Clk | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | rgmii_rxc | |||
| 30.000 | 0.000 | tCL | RR | 1 | rgmii_rxc_ibuf/I |
| 30.683 | 0.683 | tINS | RR | 460 | rgmii_rxc_ibuf/O |
| 30.862 | 0.180 | tNET | RR | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/gmii_rx_er_o/CLK |
| 31.094 | 0.232 | tC2Q | RF | 3 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/gmii_rx_er_o/Q |
| 31.332 | 0.237 | tNET | FF | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/gmii_col_o/I1 |
| 31.886 | 0.555 | tINS | FF | 2 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/gmii_col_o/F |
| 32.124 | 0.237 | tNET | FF | 1 | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_col_reg1_Z/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 32.000 | 0.000 | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk | |||
| 33.029 | 1.029 | tCL | RR | 645 | u_GW_PLL/pll_inst/CLKOUT |
| 33.209 | 0.180 | tNET | RR | 1 | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_col_reg1_Z/CLK |
| 33.174 | -0.035 | tUnc | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_col_reg1_Z | ||
| 33.139 | -0.035 | tSu | 1 | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_col_reg1_Z |
| Clock Skew: | 0.347 |
| Setup Relationship: | 2.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 1.016 |
| Data Arrival Time | 32.124 |
| Data Required Time | 33.139 |
| From | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/gmii_rx_er_o |
| To | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_crs_reg1_Z |
| Launch Clk | rgmii_rxc[R] |
| Latch Clk | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | rgmii_rxc | |||
| 30.000 | 0.000 | tCL | RR | 1 | rgmii_rxc_ibuf/I |
| 30.683 | 0.683 | tINS | RR | 460 | rgmii_rxc_ibuf/O |
| 30.862 | 0.180 | tNET | RR | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/gmii_rx_er_o/CLK |
| 31.094 | 0.232 | tC2Q | RF | 3 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/gmii_rx_er_o/Q |
| 31.332 | 0.237 | tNET | FF | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/gmii_crs_o/I1 |
| 31.886 | 0.555 | tINS | FF | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/gmii_crs_o/F |
| 32.124 | 0.237 | tNET | FF | 1 | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_crs_reg1_Z/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 32.000 | 0.000 | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk | |||
| 33.029 | 1.029 | tCL | RR | 645 | u_GW_PLL/pll_inst/CLKOUT |
| 33.209 | 0.180 | tNET | RR | 1 | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_crs_reg1_Z/CLK |
| 33.174 | -0.035 | tUnc | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_crs_reg1_Z | ||
| 33.139 | -0.035 | tSu | 1 | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_crs_reg1_Z |
| Clock Skew: | 0.347 |
| Setup Relationship: | 2.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 1.114 |
| Data Arrival Time | 9.678 |
| Data Required Time | 10.792 |
| From | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_tx_en |
| To | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/tx_en_from_mac_delay_Z[0] |
| Launch Clk | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | rgmii_rxc[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.000 | 0.000 | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk | |||
| 9.029 | 1.029 | tCL | RR | 645 | u_GW_PLL/pll_inst/CLKOUT |
| 9.209 | 0.180 | tNET | RR | 1 | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_tx_en/CLK |
| 9.441 | 0.232 | tC2Q | RF | 3 | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_tx_en/Q |
| 9.678 | 0.237 | tNET | FF | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/tx_en_from_mac_delay_Z[0]/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | rgmii_rxc | |||
| 10.000 | 0.000 | tCL | RR | 1 | rgmii_rxc_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 460 | rgmii_rxc_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/tx_en_from_mac_delay_Z[0]/CLK |
| 10.828 | -0.035 | tUnc | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/tx_en_from_mac_delay_Z[0] | ||
| 10.793 | -0.035 | tSu | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/tx_en_from_mac_delay_Z[0] |
| Clock Skew: | -0.347 |
| Setup Relationship: | 2.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 4
Path Summary:| Slack | 1.114 |
| Data Arrival Time | 9.678 |
| Data Required Time | 10.792 |
| From | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_tx_er |
| To | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/tx_er_from_mac_delay_Z[0] |
| Launch Clk | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | rgmii_rxc[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.000 | 0.000 | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk | |||
| 9.029 | 1.029 | tCL | RR | 645 | u_GW_PLL/pll_inst/CLKOUT |
| 9.209 | 0.180 | tNET | RR | 1 | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_tx_er/CLK |
| 9.441 | 0.232 | tC2Q | RF | 2 | dut/u_triple_speed_mac/u_mac_tx_ctrl/gmii_tx_er/Q |
| 9.678 | 0.237 | tNET | FF | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/tx_er_from_mac_delay_Z[0]/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | rgmii_rxc | |||
| 10.000 | 0.000 | tCL | RR | 1 | rgmii_rxc_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 460 | rgmii_rxc_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/tx_er_from_mac_delay_Z[0]/CLK |
| 10.828 | -0.035 | tUnc | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/tx_er_from_mac_delay_Z[0] | ||
| 10.793 | -0.035 | tSu | 1 | dut/u_triple_speed_mac/u_mac_rx_if_block/u_rgmii_rx_if/tx_er_from_mac_delay_Z[0] |
| Clock Skew: | -0.347 |
| Setup Relationship: | 2.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 5
Path Summary:| Slack | 1.901 |
| Data Arrival Time | 23.239 |
| Data Required Time | 25.139 |
| From | u_duplex_status/out_s0 |
| To | u_user_mac_tx_ctrl/frm_cnt_0_s0 |
| Launch Clk | clk[R] |
| Latch Clk | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 293 | clk_ibuf/O |
| 20.862 | 0.180 | tNET | RR | 1 | u_duplex_status/out_s0/CLK |
| 21.094 | 0.232 | tC2Q | RF | 7 | u_duplex_status/out_s0/Q |
| 21.332 | 0.237 | tNET | FF | 1 | u_user_mac_tx_ctrl/n_state_3_s26/I1 |
| 21.886 | 0.555 | tINS | FF | 3 | u_user_mac_tx_ctrl/n_state_3_s26/F |
| 22.124 | 0.237 | tNET | FF | 1 | u_user_mac_tx_ctrl/n652_s4/I3 |
| 22.494 | 0.371 | tINS | FF | 1 | u_user_mac_tx_ctrl/n652_s4/F |
| 22.732 | 0.237 | tNET | FF | 1 | u_user_mac_tx_ctrl/n652_s0/I3 |
| 23.059 | 0.327 | tINS | FR | 8 | u_user_mac_tx_ctrl/n652_s0/F |
| 23.239 | 0.180 | tNET | RR | 1 | u_user_mac_tx_ctrl/frm_cnt_0_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | u_GW_PLL/pll_inst/CLKOUT.default_gen_clk | |||
| 25.029 | 1.029 | tCL | RR | 645 | u_GW_PLL/pll_inst/CLKOUT |
| 25.209 | 0.180 | tNET | RR | 1 | u_user_mac_tx_ctrl/frm_cnt_0_s0/CLK |
| 25.174 | -0.035 | tUnc | u_user_mac_tx_ctrl/frm_cnt_0_s0 | ||
| 25.139 | -0.035 | tSu | 1 | u_user_mac_tx_ctrl/frm_cnt_0_s0 |
| Clock Skew: | 0.347 |
| Setup Relationship: | 4.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.253, 52.736%; route: 0.891, 37.500%; tC2Q: 0.232, 9.764% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |