Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW2A : GW2A_18
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 28 0 - 00m:01s - 5/26/20
3:19 PM
(premap)Complete 6 0 0 0m:01s 0m:01s 335MB 5/26/20
3:19 PM
(fpga_mapper)Complete 9 2 0 0m:04s 0m:05s 359MB 5/26/20
3:19 PM
Multi-srs Generator Complete5/26/20
3:19 PM

Area Summary
I/O ports (io_port) 23 Non I/O Register bits (non_io_reg) 283 (1%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 1 (46) Block Multipliers (dsp_used) 0 (24)
LUTs (total_luts) 409 (1%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top_0|clk_i230.9 MHz196.3 MHz-0.764
ao_top_0|control[0]186.0 MHz158.1 MHz-0.949

Optimizations Summary
Combined Clock Conversion 2 / 0