#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020 #install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro #OS: Linux #Hostname: JINAN3041.sdgowin.com # Tue May 26 15:19:02 2020 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: JINAN3041.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: JINAN3041.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/generic/gw2a.v" (library work) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps) @I::"/home/yandong/mywork/2020Y/Triple_Speed_Ethernet_MAC_RefDesign_Update/RGMII/project/impl/gao/ao_0/gw_ao_parameter.v" (library work) @I::"/home/yandong/mywork/2020Y/Triple_Speed_Ethernet_MAC_RefDesign_Update/RGMII/project/impl/gao/ao_0/gw_ao_top_define.v" (library work) @I::"/home/yandong/mywork/2020Y/Triple_Speed_Ethernet_MAC_RefDesign_Update/RGMII/project/impl/gao/ao_0/gw_ao_expression.v" (library work) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/data/ipcores/GAO/GW_AO_0/gw_ao_crc32.v" (library work) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/data/ipcores/GAO/GW_AO_0/gw_ao_define.v" (library work) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/data/ipcores/GAO/GW_AO_0/gw_ao_match.v" (library work) @W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared. @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/data/ipcores/GAO/GW_AO_0/gw_ao_mem_ctrl.v" (library work) @W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared. @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/data/ipcores/GAO/GW_AO_0/gw_ao_top.v" (library work) @W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared. @W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared. @W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared. @W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared. @W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared. @W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared. @W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared. @W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared. @W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared. @W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared. @W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared. @W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared. @W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared. @W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared. @W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared. @W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared. @W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared. @W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared. @W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared. @W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared. @W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared. @W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared. Verilog syntax check successful! @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_/home/yandong/mywork/2020Y/Triple_Speed_Ethernet_MAC_RefDesign_Update/RGMII/project/impl/gao/ao_0/gw_ao_parameter.v_unit in library work. Selecting top level module ao_top_0 Running optimization stage 1 on ao_mem_ctrl_0_1024s_12s_10s ....... Running optimization stage 1 on ao_crc32_0 ....... Running optimization stage 1 on ao_match_0_0s_1s_16s_1_1_0_1_2_3_4 ....... Running optimization stage 1 on ao_top_0 ....... Running optimization stage 2 on ao_match_0_0s_1s_16s_1_1_0_1_2_3_4 ....... Running optimization stage 2 on ao_top_0 ....... Extracted state machine for register module_state State machine has 11 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1001 1010 1011 Running optimization stage 2 on ao_crc32_0 ....... Running optimization stage 2 on ao_mem_ctrl_0_1024s_12s_10s ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 164MB peak: 166MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 26 15:19:03 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: JINAN3041.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 26 15:19:03 2020 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: ao_0_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 26 15:19:03 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: JINAN3041.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 26 15:19:04 2020 ###########################################################] Premap Report # Tue May 26 15:19:04 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: JINAN3041.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1620R, Built May 18 2020 06:01:43, @999365 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 223MB peak: 224MB) @A:MF827 : | No constraint file specified. Linked File: ao_0_scck.rpt See clock summary report "/home/yandong/mywork/2020Y/Triple_Speed_Ethernet_MAC_RefDesign_Update/RGMII/project/impl/gao/ao_0/rev_1/ao_0_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 238MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 239MB) @N:BN133 : | Ignoring syn_hier=hard property on top-level design. Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 239MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 249MB peak: 250MB) Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog)) original code -> new code 0000 -> 00000000001 0001 -> 00000000010 0010 -> 00000000100 0011 -> 00000001000 0100 -> 00000010000 0101 -> 00000100000 0110 -> 00001000000 0111 -> 00010000000 1001 -> 00100000000 1010 -> 01000000000 1011 -> 10000000000 Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 333MB peak: 333MB) Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 333MB peak: 334MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 333MB peak: 334MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 333MB peak: 334MB) Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 333MB peak: 334MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------- 0 - ao_top_0|control[0] 186.5 MHz 5.362 inferred Autoconstr_clkgroup_1 245 0 - ao_top_0|clk_i 237.7 MHz 4.207 inferred Autoconstr_clkgroup_0 66 ========================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------- ao_top_0|control[0] 245 control[0](port) data_register[36:0].C - - ao_top_0|clk_i 66 clk_i(port) internal_reg_force_triger_syn[1:0].C - clk_ao.I[0](keepbuf) ====================================================================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 2 non-gated/non-generated clock tree(s) driving 300 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 ENCRYPTED port 55 ENCRYPTED ClockId_0_1 ENCRYPTED IO_port 245 ENCRYPTED ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file /home/yandong/mywork/2020Y/Triple_Speed_Ethernet_MAC_RefDesign_Update/RGMII/project/impl/gao/ao_0/rev_1/ao_0.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 333MB peak: 335MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 333MB peak: 335MB) Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 333MB peak: 335MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 333MB peak: 335MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue May 26 15:19:05 2020 ###########################################################] Map & Optimize Report # Tue May 26 15:19:05 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: JINAN3041.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1620R, Built May 18 2020 06:01:43, @999365 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 223MB peak: 224MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 234MB peak: 234MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 234MB peak: 235MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 234MB peak: 235MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 249MB peak: 250MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 329MB peak: 331MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 330MB peak: 331MB) Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 330MB peak: 332MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 330MB peak: 332MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 330MB peak: 332MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 330MB peak: 332MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 332MB peak: 332MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 332MB peak: 333MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 332MB peak: 333MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 351MB peak: 351MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s -2.45ns 425 / 281 2 0h:00m:01s -2.16ns 428 / 281 Timing driven replication report Added 2 Registers via timing driven replication Added 2 LUTs via timing driven replication 3 0h:00m:02s -2.16ns 444 / 283 4 0h:00m:02s -2.30ns 446 / 283 5 0h:00m:02s -2.16ns 445 / 283 6 0h:00m:02s -2.30ns 446 / 283 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 353MB peak: 353MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 353MB peak: 354MB) Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 354MB peak: 354MB) Writing Analyst data base /home/yandong/mywork/2020Y/Triple_Speed_Ethernet_MAC_RefDesign_Update/RGMII/project/impl/gao/ao_0/rev_1/synwork/ao_0_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 355MB peak: 355MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 355MB peak: 356MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 355MB peak: 357MB) Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 355MB peak: 357MB) @W:MT420 : | Found inferred clock ao_top_0|clk_i with period 4.33ns. Please declare a user-defined clock on port clk_i. @W:MT420 : | Found inferred clock ao_top_0|control[0] with period 5.38ns. Please declare a user-defined clock on port control[0]. ##### START OF TIMING REPORT #####[ # Timing report written on Tue May 26 15:19:10 2020 # Top view: ao_top_0 Requested Frequency: 186.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.949 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------- ao_top_0|clk_i 230.9 MHz 196.3 MHz 4.331 5.095 -0.764 inferred Autoconstr_clkgroup_0 ao_top_0|control[0] 186.0 MHz 158.1 MHz 5.378 6.327 -0.949 inferred Autoconstr_clkgroup_1 ============================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------- ao_top_0|clk_i ao_top_0|clk_i | 4.331 -0.764 | 4.331 3.492 | No paths - | 2.166 1.327 ao_top_0|clk_i ao_top_0|control[0] | Diff grp - | No paths - | No paths - | No paths - ao_top_0|control[0] ao_top_0|clk_i | Diff grp - | No paths - | No paths - | No paths - ao_top_0|control[0] ao_top_0|control[0] | 5.378 -0.949 | No paths - | No paths - | No paths - ================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: ao_top_0|clk_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- internal_reg_force_triger_syn[1] ao_top_0|clk_i DFFC Q internal_reg_force_triger_syn[1] 0.243 -0.764 genblk1\.u_ao_match_0.match_sep ao_top_0|clk_i DFFC Q match 0.243 -0.743 u_ao_mem_ctrl.capture_length[0] ao_top_0|clk_i DFFC Q capture_length[0] 0.243 -0.727 u_ao_mem_ctrl.capture_length[1] ao_top_0|clk_i DFFC Q capture_length[1] 0.243 -0.692 u_ao_mem_ctrl.capture_length[2] ao_top_0|clk_i DFFC Q capture_length[2] 0.243 -0.657 triger_level_cnt[0] ao_top_0|clk_i DFFC Q triger_level_cnt[0] 0.243 -0.656 u_ao_mem_ctrl.capture_length[3] ao_top_0|clk_i DFFP Q capture_length[3] 0.243 -0.622 u_ao_mem_ctrl.capture_length[4] ao_top_0|clk_i DFFC Q capture_length[4] 0.243 -0.587 triger_level_cnt[1] ao_top_0|clk_i DFFC Q triger_level_cnt[1] 0.243 -0.565 u_ao_mem_ctrl.capture_length[5] ao_top_0|clk_i DFFC Q capture_length[5] 0.243 -0.552 ================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr ao_top_0|clk_i DFFCE CE g0_0 4.270 -0.764 u_ao_mem_ctrl.mem_addr_inc_en ao_top_0|clk_i DFFCE CE g0_3 4.270 -0.727 triger_level_cnt[2] ao_top_0|clk_i DFFC D triger_level_cnt_4[2] 4.270 -0.173 triger_level_cnt[3] ao_top_0|clk_i DFFC D triger_level_cnt_4[3] 4.270 -0.065 u_ao_mem_ctrl.capture_loop ao_top_0|clk_i DFFCE CE un1_mem_addr_inc_en6 4.270 -0.020 u_ao_mem_ctrl.capture_mem_addr[0] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[0] 4.270 -0.020 u_ao_mem_ctrl.capture_mem_addr[1] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[1] 4.270 -0.020 u_ao_mem_ctrl.capture_mem_addr[2] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[2] 4.270 -0.020 u_ao_mem_ctrl.capture_mem_addr[3] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[3] 4.270 -0.020 u_ao_mem_ctrl.capture_mem_addr[4] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[4] 4.270 -0.020 ========================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.331 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.270 - Propagation time: 5.034 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.764 Number of logic level(s): 5 Starting point: internal_reg_force_triger_syn[1] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] (rise=0.000 fall=2.166 period=4.331) on pin CLK The end point is clocked by ao_top_0|clk_i [rising] (rise=0.000 fall=2.166 period=4.331) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------ internal_reg_force_triger_syn[1] DFFC Q Out 0.243 0.243 r - internal_reg_force_triger_syn[1] Net - - 0.535 - 1 un1_match_final_3 LUT4 I1 In - 0.778 r - un1_match_final_3 LUT4 F Out 0.570 1.348 r - un1_match_final_3 Net - - 0.535 - 2 triger_level_cnt_0_sqmuxa_1 LUT4 I3 In - 1.883 r - triger_level_cnt_0_sqmuxa_1 LUT4 F Out 0.371 2.254 f - triger_level_cnt_0_sqmuxa_1 Net - - 0.401 - 1 triger_level_cnt_0_sqmuxa LUT4 I2 In - 2.655 f - triger_level_cnt_0_sqmuxa LUT4 F Out 0.462 3.117 r - triger_level_cnt_0_sqmuxa Net - - 0.596 - 16 u_ao_mem_ctrl.g0_0_1 LUT4 I3 In - 3.713 r - u_ao_mem_ctrl.g0_0_1 LUT4 F Out 0.371 4.084 f - g0_0_1 Net - - 0.401 - 1 u_ao_mem_ctrl.g0_0 LUT4 I0 In - 4.485 f - u_ao_mem_ctrl.g0_0 LUT4 F Out 0.549 5.034 r - g0_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.034 r - ================================================================================================ Total path delay (propagation time + setup) of 5.095 is 2.627(51.6%) logic and 2.468(48.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.331 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.270 - Propagation time: 5.013 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.743 Number of logic level(s): 5 Starting point: genblk1\.u_ao_match_0.match_sep / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] (rise=0.000 fall=2.166 period=4.331) on pin CLK The end point is clocked by ao_top_0|clk_i [rising] (rise=0.000 fall=2.166 period=4.331) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- genblk1\.u_ao_match_0.match_sep DFFC Q Out 0.243 0.243 r - match Net - - 0.535 - 1 un1_match_final_3 LUT4 I0 In - 0.778 r - un1_match_final_3 LUT4 F Out 0.549 1.327 r - un1_match_final_3 Net - - 0.535 - 2 triger_level_cnt_0_sqmuxa_1 LUT4 I3 In - 1.862 r - triger_level_cnt_0_sqmuxa_1 LUT4 F Out 0.371 2.233 f - triger_level_cnt_0_sqmuxa_1 Net - - 0.401 - 1 triger_level_cnt_0_sqmuxa LUT4 I2 In - 2.634 f - triger_level_cnt_0_sqmuxa LUT4 F Out 0.462 3.096 r - triger_level_cnt_0_sqmuxa Net - - 0.596 - 16 u_ao_mem_ctrl.g0_0_1 LUT4 I3 In - 3.692 r - u_ao_mem_ctrl.g0_0_1 LUT4 F Out 0.371 4.063 f - g0_0_1 Net - - 0.401 - 1 u_ao_mem_ctrl.g0_0 LUT4 I0 In - 4.464 f - u_ao_mem_ctrl.g0_0 LUT4 F Out 0.549 5.013 r - g0_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.013 r - =============================================================================================== Total path delay (propagation time + setup) of 5.074 is 2.606(51.4%) logic and 2.468(48.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.331 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.270 - Propagation time: 4.997 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.727 Number of logic level(s): 13 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] (rise=0.000 fall=2.166 period=4.331) on pin CLK The end point is clocked by ao_top_0|clk_i [rising] (rise=0.000 fall=2.166 period=4.331) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 r - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 r - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 r - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 r - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 r - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 r - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 r - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 r - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 r - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 r - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 r - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 r - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 r - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 r - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 r - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 r - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 r - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 r - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU SUM Out 0.470 2.042 f - capture_length_zero[8] Net - - 0.535 - 2 u_ao_mem_ctrl.g0_3_N_6L10 LUT3 I1 In - 2.577 f - u_ao_mem_ctrl.g0_3_N_6L10 LUT3 F Out 0.570 3.147 r - g0_3_N_6L10 Net - - 0.535 - 4 u_ao_mem_ctrl.g0_3_0_0 LUT4 I1 In - 3.682 r - u_ao_mem_ctrl.g0_3_0_0 LUT4 F Out 0.570 4.252 r - g0_3_0_0 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3_0 MUX2_LUT5 I0 In - 4.252 r - u_ao_mem_ctrl.g0_3_0 MUX2_LUT5 O Out 0.105 4.357 r - g0_3_0 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3 MUX2_LUT6 I0 In - 4.357 r - u_ao_mem_ctrl.g0_3 MUX2_LUT6 O Out 0.105 4.462 r - g0_3 Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 4.997 r - ============================================================================================================= Total path delay (propagation time + setup) of 5.058 is 2.918(57.7%) logic and 2.140(42.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.331 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.270 - Propagation time: 4.997 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.727 Number of logic level(s): 13 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] (rise=0.000 fall=2.166 period=4.331) on pin CLK The end point is clocked by ao_top_0|clk_i [rising] (rise=0.000 fall=2.166 period=4.331) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 r - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 r - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 r - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 r - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 r - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 r - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 r - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 r - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 r - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 r - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 r - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 r - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 r - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 r - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 r - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 r - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 r - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 r - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU SUM Out 0.470 2.042 f - capture_length_zero[8] Net - - 0.535 - 2 u_ao_mem_ctrl.g0_3_N_6L10 LUT3 I1 In - 2.577 f - u_ao_mem_ctrl.g0_3_N_6L10 LUT3 F Out 0.570 3.147 r - g0_3_N_6L10 Net - - 0.535 - 4 u_ao_mem_ctrl.g0_3_0_1 LUT4 I1 In - 3.682 r - u_ao_mem_ctrl.g0_3_0_1 LUT4 F Out 0.570 4.252 r - g0_3_0_1 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3_0 MUX2_LUT5 I1 In - 4.252 r - u_ao_mem_ctrl.g0_3_0 MUX2_LUT5 O Out 0.105 4.357 r - g0_3_0 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3 MUX2_LUT6 I0 In - 4.357 r - u_ao_mem_ctrl.g0_3 MUX2_LUT6 O Out 0.105 4.462 r - g0_3 Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 4.997 r - ============================================================================================================= Total path delay (propagation time + setup) of 5.058 is 2.918(57.7%) logic and 2.140(42.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.331 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.270 - Propagation time: 4.997 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.727 Number of logic level(s): 13 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] (rise=0.000 fall=2.166 period=4.331) on pin CLK The end point is clocked by ao_top_0|clk_i [rising] (rise=0.000 fall=2.166 period=4.331) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 r - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 r - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 r - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 r - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 r - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 r - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 r - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 r - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 r - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 r - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 r - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 r - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 r - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 r - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 r - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 r - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 r - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 r - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU SUM Out 0.470 2.042 f - capture_length_zero[8] Net - - 0.535 - 2 u_ao_mem_ctrl.g0_3_N_6L10 LUT3 I1 In - 2.577 f - u_ao_mem_ctrl.g0_3_N_6L10 LUT3 F Out 0.570 3.147 r - g0_3_N_6L10 Net - - 0.535 - 4 u_ao_mem_ctrl.g0_3_1_1 LUT4 I1 In - 3.682 r - u_ao_mem_ctrl.g0_3_1_1 LUT4 F Out 0.570 4.252 r - g0_3_1_1 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3_1 MUX2_LUT5 I1 In - 4.252 r - u_ao_mem_ctrl.g0_3_1 MUX2_LUT5 O Out 0.105 4.357 r - g0_3_1 Net - - 0.000 - 1 u_ao_mem_ctrl.g0_3 MUX2_LUT6 I1 In - 4.357 r - u_ao_mem_ctrl.g0_3 MUX2_LUT6 O Out 0.105 4.462 r - g0_3 Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 4.997 r - ============================================================================================================= Total path delay (propagation time + setup) of 5.058 is 2.918(57.7%) logic and 2.140(42.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: ao_top_0|control[0] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ internal_register_select[9] ao_top_0|control[0] DFFCE Q internal_register_select[9] 0.243 -0.949 internal_register_select[7] ao_top_0|control[0] DFFCE Q internal_register_select[7] 0.243 -0.928 internal_register_select[13] ao_top_0|control[0] DFFCE Q internal_register_select[13] 0.243 -0.928 internal_register_select[12] ao_top_0|control[0] DFFCE Q internal_register_select[12] 0.243 -0.907 internal_register_select[10] ao_top_0|control[0] DFFCE Q internal_register_select[10] 0.243 -0.841 internal_register_select[14] ao_top_0|control[0] DFFCE Q internal_register_select[14] 0.243 -0.820 internal_register_select[11] ao_top_0|control[0] DFFCE Q internal_register_select[11] 0.243 -0.750 internal_register_select[15] ao_top_0|control[0] DFFCE Q internal_register_select[15] 0.243 -0.729 bit_count[1] ao_top_0|control[0] DFFC Q bit_count[1] 0.243 -0.682 bit_count[0] ao_top_0|control[0] DFFC Q bit_count[0] 0.243 -0.661 ============================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------- data_out_shift_reg[0] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[0] 5.317 -0.949 data_out_shift_reg[2] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[2] 5.317 -0.750 address_counter[0] ao_top_0|control[0] DFFCE CE addr_ct_en 5.317 -0.682 address_counter[1] ao_top_0|control[0] DFFCE CE addr_ct_en 5.317 -0.682 address_counter[2] ao_top_0|control[0] DFFCE CE addr_ct_en 5.317 -0.682 address_counter[3] ao_top_0|control[0] DFFCE CE addr_ct_en 5.317 -0.682 address_counter[4] ao_top_0|control[0] DFFCE CE addr_ct_en 5.317 -0.682 address_counter[5] ao_top_0|control[0] DFFCE CE addr_ct_en 5.317 -0.682 address_counter[6] ao_top_0|control[0] DFFCE CE addr_ct_en 5.317 -0.682 address_counter[7] ao_top_0|control[0] DFFCE CE addr_ct_en 5.317 -0.682 =================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.378 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.317 - Propagation time: 6.266 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.949 Number of logic level(s): 6 Starting point: internal_register_select[9] / Q Ending point: data_out_shift_reg[0] / D The start point is clocked by ao_top_0|control[0] [rising] (rise=0.000 fall=2.689 period=5.378) on pin CLK The end point is clocked by ao_top_0|control[0] [rising] (rise=0.000 fall=2.689 period=5.378) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[9] DFFCE Q Out 0.243 0.243 r - internal_register_select[9] Net - - 0.535 - 1 data_from_internal_reg77_i_o7_5 LUT4 I1 In - 0.778 r - data_from_internal_reg77_i_o7_5 LUT4 F Out 0.570 1.348 r - data_from_internal_reg77_i_o7_5 Net - - 0.535 - 6 data_from_internal_reg77_i_o7 LUT2 I1 In - 1.883 r - data_from_internal_reg77_i_o7 LUT2 F Out 0.570 2.453 r - N_27 Net - - 0.657 - 21 internal_reg_start_m LUT4 I0 In - 3.110 r - internal_reg_start_m LUT4 F Out 0.549 3.659 r - internal_reg_start_m Net - - 0.401 - 1 data_from_ao_reg_2[0] LUT4 I3 In - 4.060 r - data_from_ao_reg_2[0] LUT4 F Out 0.371 4.431 f - data_from_ao_reg_2[0] Net - - 0.401 - 1 data_from_ao_reg_6[0] LUT4 I1 In - 4.832 f - data_from_ao_reg_6[0] LUT4 F Out 0.570 5.402 r - data_from_ao_reg_6[0] Net - - 0.401 - 1 data_out_shift_reg_4[0] LUT4 I2 In - 5.804 r - data_out_shift_reg_4[0] LUT4 F Out 0.462 6.266 r - data_out_shift_reg_4[0] Net - - 0.000 - 1 data_out_shift_reg[0] DFFCE D In - 6.266 r - =============================================================================================== Total path delay (propagation time + setup) of 6.327 is 3.396(53.7%) logic and 2.931(46.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 5.378 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.317 - Propagation time: 6.245 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.928 Number of logic level(s): 6 Starting point: internal_register_select[7] / Q Ending point: data_out_shift_reg[0] / D The start point is clocked by ao_top_0|control[0] [rising] (rise=0.000 fall=2.689 period=5.378) on pin CLK The end point is clocked by ao_top_0|control[0] [rising] (rise=0.000 fall=2.689 period=5.378) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[7] DFFCE Q Out 0.243 0.243 r - internal_register_select[7] Net - - 0.535 - 1 data_from_internal_reg77_i_o7_5 LUT4 I0 In - 0.778 r - data_from_internal_reg77_i_o7_5 LUT4 F Out 0.549 1.327 r - data_from_internal_reg77_i_o7_5 Net - - 0.535 - 6 data_from_internal_reg77_i_o7 LUT2 I1 In - 1.862 r - data_from_internal_reg77_i_o7 LUT2 F Out 0.570 2.432 r - N_27 Net - - 0.657 - 21 internal_reg_start_m LUT4 I0 In - 3.089 r - internal_reg_start_m LUT4 F Out 0.549 3.638 r - internal_reg_start_m Net - - 0.401 - 1 data_from_ao_reg_2[0] LUT4 I3 In - 4.039 r - data_from_ao_reg_2[0] LUT4 F Out 0.371 4.410 f - data_from_ao_reg_2[0] Net - - 0.401 - 1 data_from_ao_reg_6[0] LUT4 I1 In - 4.811 f - data_from_ao_reg_6[0] LUT4 F Out 0.570 5.381 r - data_from_ao_reg_6[0] Net - - 0.401 - 1 data_out_shift_reg_4[0] LUT4 I2 In - 5.783 r - data_out_shift_reg_4[0] LUT4 F Out 0.462 6.245 r - data_out_shift_reg_4[0] Net - - 0.000 - 1 data_out_shift_reg[0] DFFCE D In - 6.245 r - =============================================================================================== Total path delay (propagation time + setup) of 6.306 is 3.375(53.5%) logic and 2.931(46.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.378 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.317 - Propagation time: 6.245 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.928 Number of logic level(s): 6 Starting point: internal_register_select[13] / Q Ending point: data_out_shift_reg[0] / D The start point is clocked by ao_top_0|control[0] [rising] (rise=0.000 fall=2.689 period=5.378) on pin CLK The end point is clocked by ao_top_0|control[0] [rising] (rise=0.000 fall=2.689 period=5.378) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[13] DFFCE Q Out 0.243 0.243 r - internal_register_select[13] Net - - 0.535 - 1 data_from_internal_reg77_i_o7_4 LUT4 I1 In - 0.778 r - data_from_internal_reg77_i_o7_4 LUT4 F Out 0.570 1.348 r - data_from_internal_reg77_i_o7_4 Net - - 0.535 - 6 data_from_internal_reg77_i_o7 LUT2 I0 In - 1.883 r - data_from_internal_reg77_i_o7 LUT2 F Out 0.549 2.432 r - N_27 Net - - 0.657 - 21 internal_reg_start_m LUT4 I0 In - 3.089 r - internal_reg_start_m LUT4 F Out 0.549 3.638 r - internal_reg_start_m Net - - 0.401 - 1 data_from_ao_reg_2[0] LUT4 I3 In - 4.039 r - data_from_ao_reg_2[0] LUT4 F Out 0.371 4.410 f - data_from_ao_reg_2[0] Net - - 0.401 - 1 data_from_ao_reg_6[0] LUT4 I1 In - 4.811 f - data_from_ao_reg_6[0] LUT4 F Out 0.570 5.381 r - data_from_ao_reg_6[0] Net - - 0.401 - 1 data_out_shift_reg_4[0] LUT4 I2 In - 5.783 r - data_out_shift_reg_4[0] LUT4 F Out 0.462 6.245 r - data_out_shift_reg_4[0] Net - - 0.000 - 1 data_out_shift_reg[0] DFFCE D In - 6.245 r - =============================================================================================== Total path delay (propagation time + setup) of 6.306 is 3.375(53.5%) logic and 2.931(46.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.378 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.317 - Propagation time: 6.224 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.907 Number of logic level(s): 6 Starting point: internal_register_select[12] / Q Ending point: data_out_shift_reg[0] / D The start point is clocked by ao_top_0|control[0] [rising] (rise=0.000 fall=2.689 period=5.378) on pin CLK The end point is clocked by ao_top_0|control[0] [rising] (rise=0.000 fall=2.689 period=5.378) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[12] DFFCE Q Out 0.243 0.243 r - internal_register_select[12] Net - - 0.535 - 1 data_from_internal_reg77_i_o7_4 LUT4 I0 In - 0.778 r - data_from_internal_reg77_i_o7_4 LUT4 F Out 0.549 1.327 r - data_from_internal_reg77_i_o7_4 Net - - 0.535 - 6 data_from_internal_reg77_i_o7 LUT2 I0 In - 1.862 r - data_from_internal_reg77_i_o7 LUT2 F Out 0.549 2.411 r - N_27 Net - - 0.657 - 21 internal_reg_start_m LUT4 I0 In - 3.068 r - internal_reg_start_m LUT4 F Out 0.549 3.617 r - internal_reg_start_m Net - - 0.401 - 1 data_from_ao_reg_2[0] LUT4 I3 In - 4.018 r - data_from_ao_reg_2[0] LUT4 F Out 0.371 4.389 f - data_from_ao_reg_2[0] Net - - 0.401 - 1 data_from_ao_reg_6[0] LUT4 I1 In - 4.790 f - data_from_ao_reg_6[0] LUT4 F Out 0.570 5.360 r - data_from_ao_reg_6[0] Net - - 0.401 - 1 data_out_shift_reg_4[0] LUT4 I2 In - 5.762 r - data_out_shift_reg_4[0] LUT4 F Out 0.462 6.224 r - data_out_shift_reg_4[0] Net - - 0.000 - 1 data_out_shift_reg[0] DFFCE D In - 6.224 r - =============================================================================================== Total path delay (propagation time + setup) of 6.285 is 3.354(53.4%) logic and 2.931(46.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.378 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.317 - Propagation time: 6.190 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.874 Number of logic level(s): 6 Starting point: internal_register_select[9] / Q Ending point: data_out_shift_reg[0] / D The start point is clocked by ao_top_0|control[0] [rising] (rise=0.000 fall=2.689 period=5.378) on pin CLK The end point is clocked by ao_top_0|control[0] [rising] (rise=0.000 fall=2.689 period=5.378) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[9] DFFCE Q Out 0.243 0.243 r - internal_register_select[9] Net - - 0.535 - 1 data_from_internal_reg77_i_o7_5 LUT4 I1 In - 0.778 r - data_from_internal_reg77_i_o7_5 LUT4 F Out 0.570 1.348 r - data_from_internal_reg77_i_o7_5 Net - - 0.535 - 6 match_unit_rd_en_0_a7[0] LUT3 I1 In - 1.883 r - match_unit_rd_en_0_a7[0] LUT3 F Out 0.570 2.453 r - match_unit_rd_en[0] Net - - 0.535 - 1 genblk1\.u_ao_match_0.m9 LUT4 I3 In - 2.988 r - genblk1\.u_ao_match_0.m9 LUT4 F Out 0.371 3.359 f - data_from_match_unit[0] Net - - 0.535 - 1 data_from_ao_reg_2[0] LUT4 I2 In - 3.894 f - data_from_ao_reg_2[0] LUT4 F Out 0.462 4.356 r - data_from_ao_reg_2[0] Net - - 0.401 - 1 data_from_ao_reg_6[0] LUT4 I1 In - 4.757 r - data_from_ao_reg_6[0] LUT4 F Out 0.570 5.327 r - data_from_ao_reg_6[0] Net - - 0.401 - 1 data_out_shift_reg_4[0] LUT4 I2 In - 5.728 r - data_out_shift_reg_4[0] LUT4 F Out 0.462 6.190 r - data_out_shift_reg_4[0] Net - - 0.000 - 1 data_out_shift_reg[0] DFFCE D In - 6.190 r - =============================================================================================== Total path delay (propagation time + setup) of 6.251 is 3.309(52.9%) logic and 2.942(47.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 357MB peak: 358MB) Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 357MB peak: 358MB) --------------------------------------- Resource Usage Report for ao_top_0 Mapping to part: gw2a_18pbga256-8 Cell usage: ALU 64 uses DFF 11 uses DFFC 53 uses DFFCE 180 uses DFFNP 2 uses DFFP 5 uses DFFPE 32 uses GSR 1 use INV 2 uses MUX2_LUT5 10 uses MUX2_LUT6 4 uses SDP 1 use LUT2 49 uses LUT3 104 uses LUT4 256 uses I/O ports: 23 I/O primitives: 23 IBUF 21 uses OBUF 2 uses I/O Register bits: 0 Register bits not including I/Os: 283 of 15552 (1%) RAM/ROM usage summary Block Rams : 1 of 46 (2%) Total load per clock: ao_top_0|clk_i: 1 ao_top_0|control[0]: 230 @S |Mapping Summary: Total LUTs: 409 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 357MB peak: 359MB) Process took 0h:00m:05s realtime, 0h:00m:04s cputime # Tue May 26 15:19:10 2020 ###########################################################]