Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\GOCONFIGI2C_2K\data\GW_BACKGROUND_I2C_2k_top.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\GOCONFIGI2C_2K\data\GW_BACKGROUND_I2C_2k.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW1N-LV2LQ144XC7/I6
Device GW1N-2
Device Version C
Created Time Fri Aug 8 16:25:41 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module goConfig_I2C_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.174s, Peak memory usage = 62.469MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 62.469MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 62.469MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 62.469MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 62.469MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 62.469MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 62.469MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 62.469MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 62.469MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 62.469MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 62.469MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 62.469MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 92.934MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.178s, Peak memory usage = 92.934MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.278s, Peak memory usage = 92.934MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 92.934MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 5
I/O Buf 5
    IBUF 2
    OBUF 2
    IOBUF 1
Register 241
    DFF 4
    DFFE 42
    DFFP 5
    DFFPE 3
    DFFC 45
    DFFCE 142
LUT 487
    LUT2 56
    LUT3 144
    LUT4 287
ALU 119
    ALU 119
INV 4
    INV 4
BSRAM 1
    SDPB 1
CLOCK 1
    OSCO 1

Resource Utilization Summary

Resource Usage Utilization
Logic 610(491 LUT, 119 ALU) / 2304 27%
Register 241 / 2646 10%
  --Register as Latch 0 / 2646 0%
  --Register as FF 241 / 2358 11%
BSRAM 1 / 4 25%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk Base 40.000 25.000 0.000 20.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk 25.000(MHz) 103.935(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 30.379
Data Arrival Time 9.863
Data Required Time 40.242
From u_GW_BACKGROUND_I2C/U2/rden_s0
To u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Empty_s0
Launch Clk u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk[R]
Latch Clk u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 244 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT
0.538 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U2/rden_s0/CLK
0.878 0.340 tC2Q RF 1 u_GW_BACKGROUND_I2C/U2/rden_s0/Q
1.589 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/FIFO_rden_s0/I1
2.403 0.814 tINS FF 6 u_GW_BACKGROUND_I2C/U3/FIFO_rden_s0/F
3.115 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n101_s0/I1
3.929 0.814 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n101_s0/F
4.640 0.711 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/I1
5.415 0.774 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/COUT
5.415 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/CIN
5.457 0.042 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/COUT
5.457 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/CIN
5.874 0.417 tINS FF 3 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/SUM
6.586 0.711 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n240_s0/I0
7.295 0.710 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n240_s0/COUT
7.295 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n241_s0/CIN
7.338 0.042 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n241_s0/COUT
7.338 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n242_s0/CIN
7.380 0.042 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n242_s0/COUT
7.380 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n243_s0/CIN
7.422 0.042 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n243_s0/COUT
7.422 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n244_s0/CIN
7.464 0.042 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n244_s0/COUT
7.464 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n245_s0/CIN
7.507 0.042 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n245_s0/COUT
7.507 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n246_s0/CIN
7.549 0.042 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n246_s0/COUT
7.549 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n247_s0/CIN
7.591 0.042 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n247_s0/COUT
7.591 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n248_s0/CIN
7.633 0.042 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n248_s0/COUT
7.633 0.000 tNET FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n249_s0/CIN
7.676 0.042 tINS FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n249_s0/COUT
8.387 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rempty_val_s1/I0
9.152 0.765 tINS FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rempty_val_s1/F
9.863 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 244 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT
40.538 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK
40.242 -0.296 tSu 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 4.717, 50.587%; route: 4.268, 45.771%; tC2Q: 0.340, 3.642%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 30.556
Data Arrival Time 9.950
Data Required Time 40.506
From u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1
To u_GW_BACKGROUND_I2C/U3/checksum_add_0_s1
Launch Clk u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk[R]
Latch Clk u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 244 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT
0.538 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK
0.878 0.340 tC2Q RF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/Q
1.589 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/I1
2.403 0.814 tINS FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/F
3.115 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/I1
3.929 0.814 tINS FF 28 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.640 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/n1640_s4/I0
5.405 0.765 tINS FF 9 u_GW_BACKGROUND_I2C/U3/n1640_s4/F
6.116 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/n1486_s3/I3
6.580 0.464 tINS FF 3 u_GW_BACKGROUND_I2C/U3/n1486_s3/F
7.292 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/n1486_s1/I1
8.106 0.814 tINS FF 1 u_GW_BACKGROUND_I2C/U3/n1486_s1/F
8.817 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/n1486_s0/I2
9.412 0.594 tINS FR 2 u_GW_BACKGROUND_I2C/U3/n1486_s0/F
9.950 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/checksum_add_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 244 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT
40.538 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/checksum_add_0_s1/CLK
40.506 -0.032 tSu 1 u_GW_BACKGROUND_I2C/U3/checksum_add_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 4.266, 45.326%; route: 4.806, 51.065%; tC2Q: 0.340, 3.609%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 30.556
Data Arrival Time 9.950
Data Required Time 40.506
From u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1
To u_GW_BACKGROUND_I2C/U3/checksum_add_1_s1
Launch Clk u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk[R]
Latch Clk u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 244 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT
0.538 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK
0.878 0.340 tC2Q RF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/Q
1.589 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/I1
2.403 0.814 tINS FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/F
3.115 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/I1
3.929 0.814 tINS FF 28 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.640 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/n1640_s4/I0
5.405 0.765 tINS FF 9 u_GW_BACKGROUND_I2C/U3/n1640_s4/F
6.116 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/n1486_s3/I3
6.580 0.464 tINS FF 3 u_GW_BACKGROUND_I2C/U3/n1486_s3/F
7.292 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/n1486_s1/I1
8.106 0.814 tINS FF 1 u_GW_BACKGROUND_I2C/U3/n1486_s1/F
8.817 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/n1486_s0/I2
9.412 0.594 tINS FR 2 u_GW_BACKGROUND_I2C/U3/n1486_s0/F
9.950 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/checksum_add_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 244 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT
40.538 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/checksum_add_1_s1/CLK
40.506 -0.032 tSu 1 u_GW_BACKGROUND_I2C/U3/checksum_add_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 4.266, 45.326%; route: 4.806, 51.065%; tC2Q: 0.340, 3.609%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 30.610
Data Arrival Time 9.632
Data Required Time 40.242
From u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1
To u_GW_BACKGROUND_I2C/U2/sda_out_s2
Launch Clk u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk[R]
Latch Clk u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 244 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT
0.538 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK
0.878 0.340 tC2Q RF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/Q
1.589 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/I1
2.403 0.814 tINS FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/F
3.115 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/I1
3.929 0.814 tINS FF 28 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.640 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U2/n853_s50/I2
5.249 0.609 tINS FF 1 u_GW_BACKGROUND_I2C/U2/n853_s50/F
5.961 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U2/n853_s44/I2
6.570 0.609 tINS FF 1 u_GW_BACKGROUND_I2C/U2/n853_s44/F
7.281 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U2/n853_s38/I3
7.745 0.464 tINS FF 1 u_GW_BACKGROUND_I2C/U2/n853_s38/F
8.457 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U2/n853_s34/I3
8.920 0.464 tINS FF 1 u_GW_BACKGROUND_I2C/U2/n853_s34/F
9.632 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U2/sda_out_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 244 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT
40.538 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U2/sda_out_s2/CLK
40.242 -0.296 tSu 1 u_GW_BACKGROUND_I2C/U2/sda_out_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.775, 41.508%; route: 4.980, 54.757%; tC2Q: 0.340, 3.735%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 30.737
Data Arrival Time 9.769
Data Required Time 40.506
From u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1
To u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_0_s0
Launch Clk u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk[R]
Latch Clk u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 244 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT
0.538 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK
0.878 0.340 tC2Q RF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/Q
1.589 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/I1
2.403 0.814 tINS FF 2 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/F
3.115 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/I1
3.929 0.814 tINS FF 28 u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.640 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/n1640_s4/I0
5.405 0.765 tINS FF 9 u_GW_BACKGROUND_I2C/U3/n1640_s4/F
6.116 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/n1486_s3/I3
6.580 0.464 tINS FF 3 u_GW_BACKGROUND_I2C/U3/n1486_s3/F
7.292 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_7_s8/I0
8.056 0.765 tINS FF 8 u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_7_s8/F
8.768 0.711 tNET FF 1 u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_0_s5/I3
9.231 0.463 tINS FR 1 u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_0_s5/F
9.769 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 244 u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT
40.538 0.538 tNET RR 1 u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_0_s0/CLK
40.506 -0.032 tSu 1 u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 4.085, 44.255%; route: 4.806, 52.066%; tC2Q: 0.340, 3.679%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%