PnR Messages

Report Title PnR Report
Design File E:\work_files\IP_A_new\GoConfig\00_2025\I2C_jtag\ref_design\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\work_files\IP_A_new\GoConfig\00_2025\I2C_jtag\ref_design\fpga_project\src\fpga_project.cst
Timing Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW1N-LV2LQ144XC7/I6
Device GW1N-2
Device Version C
Created Time Fri Aug 8 16:30:08 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.163s, Elapsed time = 0h 0m 0.163s Placement Phase 1: CPU time = 0h 0m 0.114s, Elapsed time = 0h 0m 0.114s Placement Phase 2: CPU time = 0h 0m 0.092s, Elapsed time = 0h 0m 0.092s Placement Phase 3: CPU time = 0h 0m 0.503s, Elapsed time = 0h 0m 0.503s Total Placement: CPU time = 0h 0m 0.872s, Elapsed time = 0h 0m 0.872s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.119s, Elapsed time = 0h 0m 0.119s Routing Phase 2: CPU time = 0h 0m 0.211s, Elapsed time = 0h 0m 0.211s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.331s, Elapsed time = 0h 0m 0.331s Generate output files: CPU time = 0h 0m 0.57s, Elapsed time = 0h 0m 0.569s
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 264MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 680/2304 30%
    --LUT,ALU,ROM16 680(549 LUT, 131 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 274/2646 11%
    --Logic Register as Latch 0/2304 0%
    --Logic Register as FF 271/2016 14%
    --I/O Register as Latch 0/342 0%
    --I/O Register as FF 3/342 <1%
CLS 409/1152 36%
I/O Port 7/114 7%
I/O Buf 7 -
    --Input Buf 3 -
    --Output Buf 3 -
    --Inout Buf 1 -
BSRAM 1 SDPB
 25%

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 1/294%
bank 1 4/2815%
bank 2 1/294%
bank 3 1/813%
bank 4 0/100%
bank 5 0/100%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 1/8 13%
LW 2/8 25%
GCLK_PIN 2/8 25%
OSCO 1/1 100%

Global Clock Signals:

Signal Global Clock Location
GW_OSC_CLK_d PRIMARY LEFT RIGHT
rstn_d LW -
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
rstn - 92/1 N in IOR11[A] GCLKT_2 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
GW_BACKGROUND_SCL_INR - 86/1 Y in IOR14[A] - LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
GW_BACKGROUND_SEL_INR - 83/1 Y in IOR15[B] - LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
Test_LED - 41/2 Y out IOB3[B] - LVCMOS18 8 DOWN NA NA OFF NA NA NA 1.8
GW_BACKGROUND_RECONFIG_N - 119/0 N out IOT16[B] RECONFIG_N LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
GW_OSC_CLK - 27/3 N out IOL16[A] GCLKT_5 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
GW_BACKGROUND_SDA_INR - 85/1 Y io IOR14[B] - LVCMOS18 8 UP NA NONE OFF NA OFF NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
143/0 - in IOT4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
142/0 - in IOT4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
141/0 - in IOT5[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
140/0 - in IOT5[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
139/0 - in IOT6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
138/0 - in IOT6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
137/0 - out IOT7[A] TDO LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
136/0 - in IOT7[B] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
133/0 - in IOT8[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
132/0 - in IOT8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
131/0 - in IOT9[A] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
130/0 - in IOT9[B] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
128/0 - in IOT11[A] GCLKT_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
127/0 - in IOT11[B] GCLKC_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
129/0 - in IOT12[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
122/0 - in IOT13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
121/0 - in IOT13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
126/0 - in IOT14[A] GCLKT_1/SCL LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
125/0 - in IOT14[B] GCLKC_1/SDA LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
117/0 - in IOT15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
115/0 - in IOT15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
120/0 - in IOT16[A] JTAGSEL_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
119/0 GW_BACKGROUND_RECONFIG_N out IOT16[B] RECONFIG_N LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
114/0 - in IOT17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
113/0 - in IOT17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
110/0 - in IOT18[A] READY LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
109/0 - in IOT18[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
112/0 - in IOT19[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
111/0 - in IOT19[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
38/2 - in IOB2[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/2 - in IOB2[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/2 - in IOB3[A] DIN/CLKHOLD_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/2 Test_LED out IOB3[B] - LVCMOS18 8 DOWN NA NA OFF NA NA NA 1.8
42/2 - in IOB4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
43/2 - in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
44/2 - in IOB5[A] SCLK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
45/2 - in IOB5[B] SO LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
47/2 - in IOB6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/2 - in IOB6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
49/2 - in IOB7[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
50/2 - in IOB7[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
52/2 - in IOB8[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
54/2 - in IOB8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
55/2 - in IOB9[A] GCLKT_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
56/2 - in IOB9[B] GCLKC_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
57/2 - in IOB11[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
58/2 - in IOB11[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
59/2 - in IOB12[A] FASTRD_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
60/2 - in IOB12[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
61/2 - in IOB13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
62/2 - in IOB13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
63/2 - in IOB14[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
65/2 - in IOB15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
67/2 - in IOB15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
68/2 - in IOB16[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
69/2 - in IOB16[B] DOUT/WE_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
70/2 - in IOB18[A] SSPI_CS_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
71/2 - in IOB18[B] SI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
1/5 - in IOL4[A] LPLL_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/5 - in IOL4[B] LPLL_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
3/5 - in IOL5[A] LPLL_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/5 - in IOL5[B] LPLL_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
5/5 - in IOL6[A] GCLKT_7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
6/5 - in IOL6[B] GCLKC_7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
9/5 - in IOL7[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/5 - in IOL7[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
11/5 - in IOL8[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
12/5 - in IOL8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/4 - in IOL9[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/4 - in IOL9[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/4 - in IOL11[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/4 - in IOL11[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/4 - in IOL12[A] GCLKT_6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
20/4 - in IOL12[B] GCLKC_6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/4 - in IOL13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
22/4 - in IOL13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/4 - in IOL14[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
24/4 - in IOL14[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
25/3 - in IOL15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
26/3 - in IOL15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/3 GW_OSC_CLK out IOL16[A] GCLKT_5 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
28/3 - in IOL16[B] GCLKC_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/3 - in IOL17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
33/3 - in IOL17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
34/3 - in IOL18[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
35/3 - in IOL18[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
107/1 - in IOR1[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
106/1 - in IOR1[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
105/1 - in IOR2[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
104/1 - in IOR2[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
100/1 - in IOR3[A] D2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
99/1 - in IOR3[B] D3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
98/1 - in IOR4[A] D0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
97/1 - in IOR4[B] D1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
96/1 - in IOR5[A] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
95/1 - in IOR5[B] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
94/1 - in IOR6[A] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
93/1 - in IOR6[B] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
92/1 rstn in IOR11[A] GCLKT_2 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
91/1 - in IOR11[B] GCLKC_2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
89/1 - in IOR13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
87/1 - in IOR13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
86/1 GW_BACKGROUND_SCL_INR in IOR14[A] - LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
85/1 GW_BACKGROUND_SDA_INR io IOR14[B] - LVCMOS18 8 UP NA NONE OFF NA OFF NA 1.8
84/1 - in IOR15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
83/1 GW_BACKGROUND_SEL_INR in IOR15[B] - LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
82/1 - in IOR16[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
81/1 - in IOR16[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
78/1 - in IOR17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
77/1 - in IOR17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
76/1 - in IOR18[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
75/1 - in IOR18[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
74/1 - in IOR19[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
73/1 - in IOR19[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8