#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep 3 2018 #install: D:\Gowin\1.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-042 # Wed Sep 19 08:46:27 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\temp\gao\ao_0\gw_ao_parameter.v" (library work) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\temp\gao\ao_0\gw_ao_top_define.v" (library work) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\temp\gao\ao_0\gw_ao_expression.v" (library work) @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work) @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work) @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work) @W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared. @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work) @W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared. @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work) @W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared. @W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared. @W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared. @W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared. @W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared. @W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared. @W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared. @W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared. @W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared. @W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared. @W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared. @W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared. @W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared. @W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared. @W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared. @W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared. @W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared. @W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared. @W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared. @W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared. @W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared. @W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared. Verilog syntax check successful! @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\temp\gao\ao_0\gw_ao_parameter.v_unit in library work. Selecting top level module ao_top_0 Running optimization stage 1 on ao_mem_ctrl_0_1024s_26s_10s ....... Running optimization stage 1 on ao_crc32_0 ....... Running optimization stage 1 on ao_match_0_0s_9s_26s_4_1_0_1_2_3_4 ....... Running optimization stage 1 on ao_top_0 ....... Running optimization stage 2 on ao_match_0_0s_9s_26s_4_1_0_1_2_3_4 ....... Running optimization stage 2 on ao_top_0 ....... Extracted state machine for register module_state State machine has 11 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1001 1010 1011 Running optimization stage 2 on ao_crc32_0 ....... Running optimization stage 2 on ao_mem_ctrl_0_1024s_26s_10s ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 85MB peak: 88MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 19 08:46:29 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 19 08:46:29 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 19 08:46:29 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Database state : E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\temp\gao\ao_0\rev_1\synwork\|rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 19 08:46:30 2018 ###########################################################] Premap Report # Wed Sep 19 08:46:30 2018 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep 4 2018 10:03:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. @N:MF284 : | Setting synthesis effort to medium for the design Linked File: ao_0_scck.rpt Printing clock summary report in "E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) @N:BN133 : | Ignoring syn_hier=hard property on top-level design. Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Rerun analysis in 0 latches Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) @N:MF974 : | Total number of latches (multibit) processed = 0 @N:MF975 : | Total number of latches (bit blasted) processed = 0 @N:MF976 : | Total number of (multibit) opaque latches found = 0 @N:MF977 : | Total number of (bit blasted) opaque latches found = 0 Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Detailed report for transparent and observable latches in design: Linked File: ao_0_prem_latch_transparency_report.log Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog)) original code -> new code 0000 -> 00000000001 0001 -> 00000000010 0010 -> 00000000100 0011 -> 00000001000 0100 -> 00000010000 0101 -> 00000100000 0110 -> 00001000000 0111 -> 00010000000 1001 -> 00100000000 1010 -> 01000000000 1011 -> 10000000000 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) syn_allowed_resources : blockrams=140 set on top level netlist ao_top_0 Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------- 0 - ao_top_0|control[0] 186.5 MHz 5.362 inferred Autoconstr_clkgroup_1 297 0 - ao_top_0|clk_i 237.7 MHz 4.207 inferred Autoconstr_clkgroup_0 93 ========================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------- ao_top_0|control[0] 297 control[0](port) data_register[46:0].C - - ao_top_0|clk_i 93 clk_i(port) internal_reg_force_triger_syn[1:0].C - clk_ao.I[0](keepbuf) ====================================================================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 2 non-gated/non-generated clock tree(s) driving 365 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================= Non-Gated/Non-Generated Clocks ============================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------ ClockId_0_0 ENCRYPTED Unconstrained_port 68 ENCRYPTED ClockId_0_1 ENCRYPTED Unconstrained_io_port 297 ENCRYPTED ========================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\temp\gao\ao_0\rev_1\ao_0.sap. Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 193MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 193MB) None None Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 193MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Wed Sep 19 08:46:33 2018 ###########################################################] Map & Optimize Report # Wed Sep 19 08:46:33 2018 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep 4 2018 10:03:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 198MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 198MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 198MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 198MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 198MB) Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 198MB) Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 204MB peak: 207MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -2.87ns 455 / 332 2 0h:00m:02s -2.87ns 449 / 332 3 0h:00m:02s -2.81ns 448 / 332 4 0h:00m:02s -2.73ns 448 / 332 5 0h:00m:02s -2.81ns 448 / 332 6 0h:00m:02s -2.81ns 448 / 332 Timing driven replication report Added 2 Registers via timing driven replication Added 2 LUTs via timing driven replication 7 0h:00m:03s -2.81ns 454 / 334 8 0h:00m:03s -2.60ns 455 / 334 9 0h:00m:03s -2.45ns 461 / 334 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 205MB peak: 207MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 205MB peak: 207MB) Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 135MB peak: 207MB) Writing Analyst data base E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 204MB peak: 207MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 205MB peak: 207MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 203MB peak: 207MB) Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 204MB peak: 207MB) @W:MT420 : | Found inferred clock ao_top_0|clk_i with period 4.58ns. Please declare a user-defined clock on port clk_i. @W:MT420 : | Found inferred clock ao_top_0|control[0] with period 6.67ns. Please declare a user-defined clock on port control[0]. ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Sep 19 08:46:40 2018 # Top view: ao_top_0 Requested Frequency: 150.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.330 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------- ao_top_0|clk_i 218.5 MHz 185.7 MHz 4.578 5.385 -0.808 inferred Autoconstr_clkgroup_0 ao_top_0|control[0] 150.0 MHz 125.1 MHz 6.667 7.997 -1.330 inferred Autoconstr_clkgroup_1 System 150.0 MHz 236.4 MHz 6.667 4.231 2.436 system system_clkgroup ============================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------- System ao_top_0|clk_i | 4.578 2.436 | No paths - | No paths - | No paths - System ao_top_0|control[0] | 6.667 4.751 | No paths - | No paths - | No paths - ao_top_0|clk_i System | 4.578 3.800 | No paths - | No paths - | No paths - ao_top_0|clk_i ao_top_0|clk_i | 4.578 -0.808 | 4.578 3.739 | No paths - | 2.289 1.450 ao_top_0|clk_i ao_top_0|control[0] | Diff grp - | No paths - | No paths - | No paths - ao_top_0|control[0] System | 6.667 5.889 | No paths - | No paths - | No paths - ao_top_0|control[0] ao_top_0|clk_i | Diff grp - | No paths - | No paths - | No paths - ao_top_0|control[0] ao_top_0|control[0] | 6.667 -1.330 | No paths - | No paths - | No paths - ================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: ao_top_0|clk_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- internal_reg_force_triger_syn[1] ao_top_0|clk_i DFFC Q internal_reg_force_triger_syn[1] 0.243 -0.808 genblk1\.u_ao_match_0.match_sep ao_top_0|clk_i DFFC Q match 0.243 -0.787 triger_level_cnt[1] ao_top_0|clk_i DFFC Q triger_level_cnt[1] 0.243 -0.700 u_ao_mem_ctrl.capture_length[0] ao_top_0|clk_i DFFC Q capture_length[0] 0.243 -0.630 triger_level_cnt[2] ao_top_0|clk_i DFFC Q triger_level_cnt[2] 0.243 -0.609 capture_window_sel[1] ao_top_0|clk_i DFFC Q capture_window_sel[1] 0.243 -0.569 capture_window_sel[0] ao_top_0|clk_i DFFC Q capture_window_sel[0] 0.243 -0.548 u_ao_mem_ctrl.capture_length[1] ao_top_0|clk_i DFFC Q capture_length[1] 0.243 -0.522 u_ao_mem_ctrl.capture_length[2] ao_top_0|clk_i DFFC Q capture_length[2] 0.243 -0.200 u_ao_mem_ctrl.capture_length[3] ao_top_0|clk_i DFFP Q capture_length[3] 0.243 -0.165 ================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------ u_ao_mem_ctrl.capture_mem_wr ao_top_0|clk_i DFFCE CE un1_start_reg 4.517 -0.808 u_ao_mem_ctrl.mem_addr_inc_en ao_top_0|clk_i DFFCE CE un1_capture_length_zero 4.517 -0.630 u_ao_mem_ctrl.mem_addr_inc_en ao_top_0|clk_i DFFCE D mem_addr_inc_en7 4.517 -0.053 triger_level_cnt[0] ao_top_0|clk_i DFFC D triger_level_cnt_4[0] 4.517 0.029 triger_level_cnt[1] ao_top_0|clk_i DFFC D triger_level_cnt_4[1] 4.517 0.029 triger_level_cnt[2] ao_top_0|clk_i DFFC D triger_level_cnt_4[2] 4.517 0.029 triger_level_cnt[3] ao_top_0|clk_i DFFC D triger_level_cnt_4[3] 4.517 0.029 trigger_seq_start ao_top_0|clk_i DFFCE CE N_12_0_i 4.517 0.029 u_ao_mem_ctrl.capture_length[0] ao_top_0|clk_i DFFC D capture_length_5[0] 4.517 0.055 u_ao_mem_ctrl.capture_length[1] ao_top_0|clk_i DFFC D capture_length_5[1] 4.517 0.055 ======================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.578 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.517 - Propagation time: 5.324 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.808 Number of logic level(s): 5 Starting point: internal_reg_force_triger_syn[1] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- internal_reg_force_triger_syn[1] DFFC Q Out 0.243 0.243 - internal_reg_force_triger_syn[1] Net - - 0.535 - 1 internal_reg_force_triger_syn_RNIM8QT[1] LUT4 I1 In - 0.778 - internal_reg_force_triger_syn_RNIM8QT[1] LUT4 F Out 0.570 1.348 - m5_1 Net - - 0.401 - 1 u_ao_mem_ctrl_capture_loop_RNIR3MV1 LUT4 I1 In - 1.749 - u_ao_mem_ctrl_capture_loop_RNIR3MV1 LUT4 F Out 0.570 2.319 - N_272_mux Net - - 0.535 - 6 trigger_seq_start_RNIS6PU3_0 LUT4 I0 In - 2.854 - trigger_seq_start_RNIS6PU3_0 LUT4 F Out 0.549 3.403 - triger_level_cnt_0_sqmuxa Net - - 0.596 - 15 u_ao_mem_ctrl.un1_start_reg_1 LUT4 I2 In - 3.999 - u_ao_mem_ctrl.un1_start_reg_1 LUT4 F Out 0.462 4.461 - un1_start_reg_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_start_reg LUT4 I2 In - 4.862 - u_ao_mem_ctrl.un1_start_reg LUT4 F Out 0.462 5.324 - un1_start_reg Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.324 - ======================================================================================================== Total path delay (propagation time + setup) of 5.385 is 2.917(54.2%) logic and 2.468(45.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.578 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.517 - Propagation time: 5.303 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.787 Number of logic level(s): 5 Starting point: genblk1\.u_ao_match_0.match_sep / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- genblk1\.u_ao_match_0.match_sep DFFC Q Out 0.243 0.243 - match Net - - 0.535 - 1 internal_reg_force_triger_syn_RNIM8QT[1] LUT4 I0 In - 0.778 - internal_reg_force_triger_syn_RNIM8QT[1] LUT4 F Out 0.549 1.327 - m5_1 Net - - 0.401 - 1 u_ao_mem_ctrl_capture_loop_RNIR3MV1 LUT4 I1 In - 1.728 - u_ao_mem_ctrl_capture_loop_RNIR3MV1 LUT4 F Out 0.570 2.298 - N_272_mux Net - - 0.535 - 6 trigger_seq_start_RNIS6PU3_0 LUT4 I0 In - 2.833 - trigger_seq_start_RNIS6PU3_0 LUT4 F Out 0.549 3.382 - triger_level_cnt_0_sqmuxa Net - - 0.596 - 15 u_ao_mem_ctrl.un1_start_reg_1 LUT4 I2 In - 3.978 - u_ao_mem_ctrl.un1_start_reg_1 LUT4 F Out 0.462 4.440 - un1_start_reg_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_start_reg LUT4 I2 In - 4.841 - u_ao_mem_ctrl.un1_start_reg LUT4 F Out 0.462 5.303 - un1_start_reg Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.303 - ======================================================================================================== Total path delay (propagation time + setup) of 5.364 is 2.896(54.0%) logic and 2.468(46.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.578 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.517 - Propagation time: 5.216 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.700 Number of logic level(s): 5 Starting point: triger_level_cnt[1] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- triger_level_cnt[1] DFFC Q Out 0.243 0.243 - triger_level_cnt[1] Net - - 0.535 - 4 internal_reg_force_triger_syn_RNIM8QT[1] LUT4 I2 In - 0.778 - internal_reg_force_triger_syn_RNIM8QT[1] LUT4 F Out 0.462 1.240 - m5_1 Net - - 0.401 - 1 u_ao_mem_ctrl_capture_loop_RNIR3MV1 LUT4 I1 In - 1.641 - u_ao_mem_ctrl_capture_loop_RNIR3MV1 LUT4 F Out 0.570 2.211 - N_272_mux Net - - 0.535 - 6 trigger_seq_start_RNIS6PU3_0 LUT4 I0 In - 2.746 - trigger_seq_start_RNIS6PU3_0 LUT4 F Out 0.549 3.295 - triger_level_cnt_0_sqmuxa Net - - 0.596 - 15 u_ao_mem_ctrl.un1_start_reg_1 LUT4 I2 In - 3.891 - u_ao_mem_ctrl.un1_start_reg_1 LUT4 F Out 0.462 4.353 - un1_start_reg_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_start_reg LUT4 I2 In - 4.754 - u_ao_mem_ctrl.un1_start_reg LUT4 F Out 0.462 5.216 - un1_start_reg Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.216 - ======================================================================================================== Total path delay (propagation time + setup) of 5.277 is 2.809(53.2%) logic and 2.468(46.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.578 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.517 - Propagation time: 5.147 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.630 Number of logic level(s): 5 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 - capture_length[0] Net - - 0.535 - 3 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU SUM Out 0.470 1.797 - capture_length_zero[1] Net - - 0.535 - 1 u_ao_mem_ctrl.capture_length_zero_1_7_1_0 LUT3 I1 In - 2.332 - u_ao_mem_ctrl.capture_length_zero_1_7_1_0 LUT3 F Out 0.570 2.902 - capture_length_zero_1_7_1 Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_1_7 LUT4 I3 In - 3.437 - u_ao_mem_ctrl.capture_length_zero_1_7 LUT4 F Out 0.371 3.808 - capture_length_zero_1_7 Net - - 0.535 - 1 u_ao_mem_ctrl.un1_capture_length_zero MUX2_LUT5 S0 In - 4.343 - u_ao_mem_ctrl.un1_capture_length_zero MUX2_LUT5 O Out 0.269 4.612 - un1_capture_length_zero Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 5.147 - ============================================================================================================= Total path delay (propagation time + setup) of 5.208 is 2.533(48.6%) logic and 2.675(51.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.578 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.517 - Propagation time: 5.125 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.609 Number of logic level(s): 5 Starting point: triger_level_cnt[2] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- triger_level_cnt[2] DFFC Q Out 0.243 0.243 - triger_level_cnt[2] Net - - 0.535 - 4 internal_reg_force_triger_syn_RNIM8QT[1] LUT4 I3 In - 0.778 - internal_reg_force_triger_syn_RNIM8QT[1] LUT4 F Out 0.371 1.149 - m5_1 Net - - 0.401 - 1 u_ao_mem_ctrl_capture_loop_RNIR3MV1 LUT4 I1 In - 1.550 - u_ao_mem_ctrl_capture_loop_RNIR3MV1 LUT4 F Out 0.570 2.120 - N_272_mux Net - - 0.535 - 6 trigger_seq_start_RNIS6PU3_0 LUT4 I0 In - 2.655 - trigger_seq_start_RNIS6PU3_0 LUT4 F Out 0.549 3.204 - triger_level_cnt_0_sqmuxa Net - - 0.596 - 15 u_ao_mem_ctrl.un1_start_reg_1 LUT4 I2 In - 3.800 - u_ao_mem_ctrl.un1_start_reg_1 LUT4 F Out 0.462 4.262 - un1_start_reg_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_start_reg LUT4 I2 In - 4.663 - u_ao_mem_ctrl.un1_start_reg LUT4 F Out 0.462 5.125 - un1_start_reg Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.125 - ======================================================================================================== Total path delay (propagation time + setup) of 5.186 is 2.718(52.4%) logic and 2.468(47.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: ao_top_0|control[0] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------- word_count[10] ao_top_0|control[0] DFFCE Q word_count[10] 0.243 -1.330 word_count[0] ao_top_0|control[0] DFFCE Q word_count[0] 0.243 -1.309 word_count[11] ao_top_0|control[0] DFFCE Q word_count[11] 0.243 -1.222 word_count[13] ao_top_0|control[0] DFFCE Q word_count[13] 0.243 -1.222 word_count[1] ao_top_0|control[0] DFFCE Q word_count[1] 0.243 -1.201 word_count[4] ao_top_0|control[0] DFFCE Q word_count[4] 0.243 -1.175 word_count[3] ao_top_0|control[0] DFFCE Q word_count[3] 0.243 -1.154 word_count[12] ao_top_0|control[0] DFFCE Q word_count[12] 0.243 -1.131 word_count[14] ao_top_0|control[0] DFFCE Q word_count[14] 0.243 -1.114 word_count[5] ao_top_0|control[0] DFFCE Q word_count[5] 0.243 -1.067 ================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------- address_counter[0] ao_top_0|control[0] DFFCE CE addr_ct_en 6.606 -1.330 address_counter[1] ao_top_0|control[0] DFFCE CE addr_ct_en 6.606 -1.330 address_counter[2] ao_top_0|control[0] DFFCE CE addr_ct_en 6.606 -1.330 address_counter[3] ao_top_0|control[0] DFFCE CE addr_ct_en 6.606 -1.330 address_counter[4] ao_top_0|control[0] DFFCE CE addr_ct_en 6.606 -1.330 address_counter[5] ao_top_0|control[0] DFFCE CE addr_ct_en 6.606 -1.330 address_counter[6] ao_top_0|control[0] DFFCE CE addr_ct_en 6.606 -1.330 address_counter[7] ao_top_0|control[0] DFFCE CE addr_ct_en 6.606 -1.330 address_counter[8] ao_top_0|control[0] DFFCE CE addr_ct_en 6.606 -1.330 address_counter[9] ao_top_0|control[0] DFFCE CE addr_ct_en 6.606 -1.330 =================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.667 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.606 - Propagation time: 7.936 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.330 Number of logic level(s): 7 Starting point: word_count[10] / Q Ending point: address_counter[0] / CE The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- word_count[10] DFFCE Q Out 0.243 0.243 - word_count[10] Net - - 0.535 - 2 module_state_ns_0_a2_1_10[0] LUT4 I1 In - 0.778 - module_state_ns_0_a2_1_10[0] LUT4 F Out 0.570 1.348 - module_state_ns_0_a2_1_10[0] Net - - 0.535 - 2 module_state_ns_0_a2_1_x[0] LUT4 I1 In - 1.883 - module_state_ns_0_a2_1_x[0] LUT4 F Out 0.570 2.453 - addr_ct_en_0_sqmuxa_2_s_1 Net - - 0.401 - 1 addr_ct_en_0_sqmuxa_2_s LUT4 I0 In - 2.854 - addr_ct_en_0_sqmuxa_2_s LUT4 F Out 0.549 3.403 - addr_ct_en_0_sqmuxa_2_out Net - - 0.535 - 3 addr_ct_en_N_2L1_sx LUT4 I0 In - 3.938 - addr_ct_en_N_2L1_sx LUT4 F Out 0.549 4.487 - addr_ct_en_N_2L1_sx Net - - 0.401 - 1 addr_ct_en_N_2L1 LUT4 I1 In - 4.888 - addr_ct_en_N_2L1 LUT4 F Out 0.570 5.458 - addr_ct_en_N_4L5_1 Net - - 0.401 - 1 addr_ct_en_N_4L5 LUT4 I1 In - 5.860 - addr_ct_en_N_4L5 LUT4 F Out 0.570 6.430 - addr_ct_en_1_0 Net - - 0.401 - 1 addr_ct_en LUT4 I1 In - 6.831 - addr_ct_en LUT4 F Out 0.570 7.401 - addr_ct_en Net - - 0.535 - 10 address_counter[0] DFFCE CE In - 7.936 - ============================================================================================ Total path delay (propagation time + setup) of 7.997 is 4.252(53.2%) logic and 3.745(46.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 6.667 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.606 - Propagation time: 7.936 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.330 Number of logic level(s): 7 Starting point: word_count[10] / Q Ending point: address_counter[1] / CE The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- word_count[10] DFFCE Q Out 0.243 0.243 - word_count[10] Net - - 0.535 - 2 module_state_ns_0_a2_1_10[0] LUT4 I1 In - 0.778 - module_state_ns_0_a2_1_10[0] LUT4 F Out 0.570 1.348 - module_state_ns_0_a2_1_10[0] Net - - 0.535 - 2 module_state_ns_0_a2_1_x[0] LUT4 I1 In - 1.883 - module_state_ns_0_a2_1_x[0] LUT4 F Out 0.570 2.453 - addr_ct_en_0_sqmuxa_2_s_1 Net - - 0.401 - 1 addr_ct_en_0_sqmuxa_2_s LUT4 I0 In - 2.854 - addr_ct_en_0_sqmuxa_2_s LUT4 F Out 0.549 3.403 - addr_ct_en_0_sqmuxa_2_out Net - - 0.535 - 3 addr_ct_en_N_2L1_sx LUT4 I0 In - 3.938 - addr_ct_en_N_2L1_sx LUT4 F Out 0.549 4.487 - addr_ct_en_N_2L1_sx Net - - 0.401 - 1 addr_ct_en_N_2L1 LUT4 I1 In - 4.888 - addr_ct_en_N_2L1 LUT4 F Out 0.570 5.458 - addr_ct_en_N_4L5_1 Net - - 0.401 - 1 addr_ct_en_N_4L5 LUT4 I1 In - 5.860 - addr_ct_en_N_4L5 LUT4 F Out 0.570 6.430 - addr_ct_en_1_0 Net - - 0.401 - 1 addr_ct_en LUT4 I1 In - 6.831 - addr_ct_en LUT4 F Out 0.570 7.401 - addr_ct_en Net - - 0.535 - 10 address_counter[1] DFFCE CE In - 7.936 - ============================================================================================ Total path delay (propagation time + setup) of 7.997 is 4.252(53.2%) logic and 3.745(46.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 6.667 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.606 - Propagation time: 7.936 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.330 Number of logic level(s): 7 Starting point: word_count[10] / Q Ending point: address_counter[2] / CE The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- word_count[10] DFFCE Q Out 0.243 0.243 - word_count[10] Net - - 0.535 - 2 module_state_ns_0_a2_1_10[0] LUT4 I1 In - 0.778 - module_state_ns_0_a2_1_10[0] LUT4 F Out 0.570 1.348 - module_state_ns_0_a2_1_10[0] Net - - 0.535 - 2 module_state_ns_0_a2_1_x[0] LUT4 I1 In - 1.883 - module_state_ns_0_a2_1_x[0] LUT4 F Out 0.570 2.453 - addr_ct_en_0_sqmuxa_2_s_1 Net - - 0.401 - 1 addr_ct_en_0_sqmuxa_2_s LUT4 I0 In - 2.854 - addr_ct_en_0_sqmuxa_2_s LUT4 F Out 0.549 3.403 - addr_ct_en_0_sqmuxa_2_out Net - - 0.535 - 3 addr_ct_en_N_2L1_sx LUT4 I0 In - 3.938 - addr_ct_en_N_2L1_sx LUT4 F Out 0.549 4.487 - addr_ct_en_N_2L1_sx Net - - 0.401 - 1 addr_ct_en_N_2L1 LUT4 I1 In - 4.888 - addr_ct_en_N_2L1 LUT4 F Out 0.570 5.458 - addr_ct_en_N_4L5_1 Net - - 0.401 - 1 addr_ct_en_N_4L5 LUT4 I1 In - 5.860 - addr_ct_en_N_4L5 LUT4 F Out 0.570 6.430 - addr_ct_en_1_0 Net - - 0.401 - 1 addr_ct_en LUT4 I1 In - 6.831 - addr_ct_en LUT4 F Out 0.570 7.401 - addr_ct_en Net - - 0.535 - 10 address_counter[2] DFFCE CE In - 7.936 - ============================================================================================ Total path delay (propagation time + setup) of 7.997 is 4.252(53.2%) logic and 3.745(46.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 6.667 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.606 - Propagation time: 7.936 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.330 Number of logic level(s): 7 Starting point: word_count[10] / Q Ending point: address_counter[3] / CE The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- word_count[10] DFFCE Q Out 0.243 0.243 - word_count[10] Net - - 0.535 - 2 module_state_ns_0_a2_1_10[0] LUT4 I1 In - 0.778 - module_state_ns_0_a2_1_10[0] LUT4 F Out 0.570 1.348 - module_state_ns_0_a2_1_10[0] Net - - 0.535 - 2 module_state_ns_0_a2_1_x[0] LUT4 I1 In - 1.883 - module_state_ns_0_a2_1_x[0] LUT4 F Out 0.570 2.453 - addr_ct_en_0_sqmuxa_2_s_1 Net - - 0.401 - 1 addr_ct_en_0_sqmuxa_2_s LUT4 I0 In - 2.854 - addr_ct_en_0_sqmuxa_2_s LUT4 F Out 0.549 3.403 - addr_ct_en_0_sqmuxa_2_out Net - - 0.535 - 3 addr_ct_en_N_2L1_sx LUT4 I0 In - 3.938 - addr_ct_en_N_2L1_sx LUT4 F Out 0.549 4.487 - addr_ct_en_N_2L1_sx Net - - 0.401 - 1 addr_ct_en_N_2L1 LUT4 I1 In - 4.888 - addr_ct_en_N_2L1 LUT4 F Out 0.570 5.458 - addr_ct_en_N_4L5_1 Net - - 0.401 - 1 addr_ct_en_N_4L5 LUT4 I1 In - 5.860 - addr_ct_en_N_4L5 LUT4 F Out 0.570 6.430 - addr_ct_en_1_0 Net - - 0.401 - 1 addr_ct_en LUT4 I1 In - 6.831 - addr_ct_en LUT4 F Out 0.570 7.401 - addr_ct_en Net - - 0.535 - 10 address_counter[3] DFFCE CE In - 7.936 - ============================================================================================ Total path delay (propagation time + setup) of 7.997 is 4.252(53.2%) logic and 3.745(46.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 6.667 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.606 - Propagation time: 7.936 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.330 Number of logic level(s): 7 Starting point: word_count[10] / Q Ending point: address_counter[4] / CE The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- word_count[10] DFFCE Q Out 0.243 0.243 - word_count[10] Net - - 0.535 - 2 module_state_ns_0_a2_1_10[0] LUT4 I1 In - 0.778 - module_state_ns_0_a2_1_10[0] LUT4 F Out 0.570 1.348 - module_state_ns_0_a2_1_10[0] Net - - 0.535 - 2 module_state_ns_0_a2_1_x[0] LUT4 I1 In - 1.883 - module_state_ns_0_a2_1_x[0] LUT4 F Out 0.570 2.453 - addr_ct_en_0_sqmuxa_2_s_1 Net - - 0.401 - 1 addr_ct_en_0_sqmuxa_2_s LUT4 I0 In - 2.854 - addr_ct_en_0_sqmuxa_2_s LUT4 F Out 0.549 3.403 - addr_ct_en_0_sqmuxa_2_out Net - - 0.535 - 3 addr_ct_en_N_2L1_sx LUT4 I0 In - 3.938 - addr_ct_en_N_2L1_sx LUT4 F Out 0.549 4.487 - addr_ct_en_N_2L1_sx Net - - 0.401 - 1 addr_ct_en_N_2L1 LUT4 I1 In - 4.888 - addr_ct_en_N_2L1 LUT4 F Out 0.570 5.458 - addr_ct_en_N_4L5_1 Net - - 0.401 - 1 addr_ct_en_N_4L5 LUT4 I1 In - 5.860 - addr_ct_en_N_4L5 LUT4 F Out 0.570 6.430 - addr_ct_en_1_0 Net - - 0.401 - 1 addr_ct_en LUT4 I1 In - 6.831 - addr_ct_en LUT4 F Out 0.570 7.401 - addr_ct_en Net - - 0.535 - 10 address_counter[4] DFFCE CE In - 7.936 - ============================================================================================ Total path delay (propagation time + setup) of 7.997 is 4.252(53.2%) logic and 3.745(46.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 System INV O capture_end 0.000 2.436 address_counter_cry_0_RNO[0] System INV O address_counter 0.000 4.751 ============================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------- capture_window_sel[2] System DFFC D capture_window_sel_3[2] 4.517 2.436 capture_window_sel[3] System DFFC D capture_window_sel_3[3] 4.517 2.436 capture_window_sel[1] System DFFC D capture_window_sel_3[1] 4.517 2.482 capture_window_sel[0] System DFFC D capture_window_sel_3[0] 4.517 3.433 internal_reg_start_dly[0] System DFFC D internal_reg_start_dly_2[0] 4.517 3.433 capture_end_dly System DFFP D capture_end 4.517 3.982 address_counter[9] System DFFCE D address_counter_s[9] 6.606 4.751 address_counter[8] System DFFCE D address_counter_s[8] 6.606 4.786 address_counter[7] System DFFCE D address_counter_s[7] 6.606 4.821 address_counter[6] System DFFCE D address_counter_s[6] 6.606 4.856 ================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.578 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.517 - Propagation time: 2.081 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 2.436 Number of logic level(s): 2 Starting point: u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O Ending point: capture_window_sel[2] / D The start point is clocked by System [rising] The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 INV O Out 0.000 0.000 - capture_end Net - - 0.535 - 6 un1_capture_window_sel_ac0_1 LUT4 I0 In - 0.535 - un1_capture_window_sel_ac0_1 LUT4 F Out 0.549 1.084 - un1_capture_window_sel_c2 Net - - 0.535 - 2 capture_window_sel_3[2] LUT3 I2 In - 1.619 - capture_window_sel_3[2] LUT3 F Out 0.462 2.081 - capture_window_sel_3[2] Net - - 0.000 - 1 capture_window_sel[2] DFFC D In - 2.081 - =================================================================================================== Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 205MB peak: 207MB) Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 205MB peak: 207MB) --------------------------------------- Resource Usage Report for ao_top_0 Mapping to part: gw2a_55pbga484-8 Cell usage: ALU 87 uses DFF 25 uses DFFC 37 uses DFFCE 233 uses DFFNP 2 uses DFFP 5 uses DFFPE 32 uses GSR 1 use INV 2 uses MUX2_LUT5 32 uses MUX2_LUT6 4 uses SDPX9 2 uses LUT2 51 uses LUT3 100 uses LUT4 253 uses I/O ports: 45 I/O primitives: 45 IBUF 43 uses OBUF 2 uses I/O Register bits: 0 Register bits not including I/Os: 334 of 41040 (0%) RAM/ROM usage summary Block Rams : 2 of 140 (1%) Total load per clock: ao_top_0|clk_i: 1 ao_top_0|control[0]: 269 @S |Mapping Summary: Total LUTs: 404 (0%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 45MB peak: 207MB) Process took 0h:00m:07s realtime, 0h:00m:06s cputime # Wed Sep 19 08:46:41 2018 ###########################################################]