@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N:: Running Verilog Compiler in System Verilog mode
@N:: Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":6:30:6:30|Synthesizing module RAM_based_shift_reg_top in library work.
@N|Running in 64-bit mode
@N: NF107 :"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":6:30:6:30|Selected library: work cell: RAM_based_shift_reg_top view verilog as top level
@N: NF107 :"C:\Gowin\1.8\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v":6:30:6:30|Selected library: work cell: RAM_based_shift_reg_top view verilog as top level

