voDir:=			../project/src/RAM_based_shift_reg_top
designDir:=		../project/src
tbDir:=			../tb
voFile:=		$(voDir)/RAM_based_shift_reg_top.vo
designFile:=		$(designDir)/TOP.v			\
			$(designDir)/gw_osc/gw_osc.v		\
			$(designDir)/gw_pll/gw_pll.v 		
tbFile:=		$(tbDir)/tb.v
vcs:
	vcs -debug_all -R -full64 -fsdb -sverilog	\
	-v ./prim_sim.v 				\
	$(tbFile)					\
	$(voFile)					\
	$(designFile)					
vd:
	verdi -sverilog					\
	-v ./prim_sim.v 				\
	$(tbFile)					\
	$(voFile)					\
	$(designFile)					\
	-ssf tb.fsdb					\
	&

clean:
	rm -rf compile  *.err *.log csrc  run.do  simv  simv.daidir  ucli.key  vc_hdrs.h  work novas.rc  nWaveLog   vcd2fsdbLog  verilog.vcd  verilog.vcd.fsdb vsim.wlf simv.vdb INCA_libs waves.shm .simvision *.rc cov_work dataset.asdb  fcover.acdb  library.cfg elab_file *.ucdb verdiLog inter.vpd novas.conf wave.ses.png tb.fsdb data
