Project Settings
Project Name RAM_Based_Shift_Register Device Name rev_1: GOWIN-GW2A : GW2A_55
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 1 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 8 0 0 - 00m:01s - 2018/9/14
15:15:13
(premap)Complete 7 0 0 0m:01s 0m:01s 191MB 2018/9/14
15:15:16
(fpga_mapper)Complete 9 1 0 0m:03s 0m:03s 191MB 2018/9/14
15:15:19
Multi-srs Generator Complete2018/9/14
15:15:14

Area Summary
Non I/O Register bits (non_io_reg) 3 (0%) I/O Register bits (total_io_reg) 0
Block Rams (v_ram) 1 (140) Block Multipliers (dsp_used) 0 (20)
LUTs (total_luts) 11 (0%)

Timing Summary
Clock NameReq FreqEst FreqSlack
RAM_based_shift_reg_top|clk834.9 MHz709.7 MHz-0.211